PDP-10 Clone Microprocessor in an FPGA

Project Basics

It is based on the information provided in the DECsystem-10/DECSYSTEM-20 Processor Reference Manual.

This is actual hardware (clone), as opposed to software (emulators), such as the ts10 or SIMH or KLH10 programs.

This project grow out of multiple of my interests:

• My decades old interest in making an computer myself. Originally an self-build microprocessor-based system. Then an self-designed processor from 74xx logic. Then ideas of using an large PAL (PAL64R32)
• My 10 year old interest in programmable logic (then knew about PALs, saw early Xilinx, then Algotronix CAL1024) and using it for an own microprocessor. Re-awakend by multiple magazine articles on how far FPGAs have come
• An interest in the PDP-10 stemming from reading a lot about it in the Jargon File. And also an general interest in old DEC computers from growing up on PDP-11 and VAX machines
• The announcement of Doug Conroy's PDP-8/X clone on 20000819, that brought all the previous parts together, igniting interest in making an processor
• Reading about Jan Gray's xr16 CPU Core and how to implement single cycle RISC machines in FPGAs on 20000822, convincing me that one can make fast microprocessors that are actually usable for daily work, not just toy/experiment/teaching systems
• Frustration with the (then) non-availability of PDP-10 emulators (ts10 was then "permanently near finished" with no code out, SIMH pdp10 mode was not yet announced and so unknown to be in the making, KLH10 was known to exist but regarded as "lost inside DEC jailled by copyright")
• Deciding on 20001230 that making an other PDP-8 (with no own PDP-8 background or software) or an PDP-11 (with PDP-11 Unix to run, but already SIMH capable of doing that at more then original speed) or an own processor design (with no software to run) would just be toy projects. So better go for making an PDP-10, which may one day run an today usable OS (be that native TOPS-20 or Linux or NetBSD (which is being ported))

Since the project start the situation has changed by the appearance/release of the 3 emulators (regarded by many, me inclusive, as PDP-10 microcode implementations running on Intel micromachine). But a real hardware PDP-10 is still attractive.
Also Doug Conroy has announced his expected 10 clone project, but this is a small/toy microcoded machine roughly at original speed, not the usable 10-30 times original, that this project can grow to.
Also this project has spawned an FPGA Programming Tools sister project called VirtexTools, and has thus become the test case for the tools developed in that.

For more info on this project read the README file. For some questions people have asked or may ask read the FAQ list.

Addendum 2003.12.24: This project and VirtexTools canceled on 2003.12.24. After 1 month of forced break (HD crash, system rebuild) and 1.5 months since then of doing nothing on either this project or on VirtexTools, I have come the the conclusion that I have lost all interest in both of them. Reasons are many:

• FPGA market pricing has an massive ramp between near identical sized $50 and $500 Parts. When I started this project the ramp was at 200kGates (XC2S200). I wanted to stay underneath that ramp. So a 36bit CISC needed to be done at LUT-by-LUT "assembler" programming level. Also FPGA HLLs are awfull anyway, further reason to avoid them
• This meant using JBits+Java, which limits to using single-family Spartan-II parts, and unsure extension to future families (definitive no Spartan-IIE, possibly will have Spartan-III). Also troubles with JBits, and not fixable as it is closed source software
• Making an own open source LUT oriented Compiler (VirtexTools) delays Project. And runs into problems with closed bit streams. Reverse engineering bit streams is a lot of work, would delay even more (years!), and reverse engineering needs redoing for other FPGA families (every few years), and likely no docs for that
• Until reverse engineering and own tools done, the price ramp will have moved to large enough FPGAs to use HLLs. And they are easier to use, faster, portable, vendor independant, no time reverse engineering. So if FPGA, wait until then and redo in HLL. So scratch code done sofar. So end project in its current low-level form. Back to zero
• But until then also x86+emulator as fast as my chip could ever be. Even underclocked fanless miniature VIA parts will be equal fast and low-power and small. And far less work, just install existing emulator. And no Java or awfull FPGA HLLs, just possibly adapt C code. Even todays top x86 are faster than the originals, and as fast as my first iteration would be, and their speed grows "automatically" with new x86 chips. And I could start installing today, upgrade later
• Even getting rid of PC architecture (is anyway hidden under emulator and C compiler) can be had easier by building some ARM based board with an emulator built in. For an computer architecture independant of PC manufacturers whims (DRM and such crap), even if not powerfull, just as contingency, is way better using an ARM (or even non-PC x86) board, that single-source closed FPGAs. Even 74(x)xx+PALs would be better than FPGAs, despite totally underpowered. So no FPGA project at all
• Switching from FPGA to emulator (on an 32bit CPU) makes the 36bit PDP-10 (chosen because simple for FPGA) unattractive (32+4 or 2*18 bit dual computation). OTOH emulators make the more complex VAX possible (and faster single computation). And I know its native VMS (unlike TOPS-10 or TOPS-20). And early Unix also used these. So if restart with emulator do an VAX. So no PDP-10 project at all
• Also my dislike of the x86 CPU is waning, so I could could just build an non-PC architecture x86, and get that up to full speed. So no other high-power to-use-daily CPU FPGA or emulation project at all
• Making an toy CPU just for the act of making one is too much drudge work to be fun (with FPGAs). And while small systems, such as PDP-1 (can run Spacewar) or PDP-8 (simplest) or even an 2*18bit PDP-10, will today fit $50 FPGAs using HLLs, emulation is way fast enough for toys. And my interest in layouting any CPU is largly satisfied from how far I came in this first go. So no FPGA CPU at all
• Only interesting needs-to-be-hardware CPU project remaining would be to recreate an CPU+mem+frontpannel, wire wrapping 74(x)xx+PAL parts or even own transistor modules, all hardware, no software tool (not even PCB layout) frustration getting in the way. That would need to be simple (PDP-12) to reduce design time, solder work and cost. But collecting/restoring originals would be more usefull. And both of these suffer from storage space problems
• Using own CPU to help teach machine code and assembler is not worth making an CPU either. Better use PDP-8 or PDP-11, or DOSemu (8088 PC), or C64 emulator with fitting software for that. If non-PC hardware wanted, put any of these small emulators in an flash based uC, and wire its IO ports as external memory and IO bus. Or if wanting to show internal CPU operation, go for the most transparent wire wrap PDP-8 recreation
• The only remaining reason for this project is just as test case for VirtexTools (as I have used it for the last year). This leads to no extensions (as done none in last year) unless I need new test cases. And even then other test cases may be more effective. And test case for VirtexTools is also only worth it, so long I have an interest in making them, which has now also ceased, due to large problems there. See thats cancelation
• This site and all work done up until now remains online, in case someone wants to continue this project, copy "Current" and work on

Project Status

Done are:

• Temporary program memory (32 words, at address 000..037)
• Central infrastructure for: selecting source for addressing memory, program counter (register and incrementer, instruction and memory address registers, instruction fetch/index/indirect/execute control, arthmetic register for temporary data while doing an instruction
• Instruction unit 100ffffmm boolean logic, a set of 4-input 2-select muxes, driven by the 2 bits to be processed, selecting from the 4 instruction bits that specify the operation

• Massive overhaul of central infrastructure to work with multiple instruction units, provide immediate values from MA without wasting an cycle, use faster distributed arithmetic registers (the present AR becomes a temporary register for for the first of two memory operands
• Instruction unit 011tttmmm arithmetic testing, an ALU for all the comparing/increment/decrement stuff, and an zero/nonzero detector to control conditional skipping or jumping

• Massive overhaul of programming style hiding lots of verbosity, place independant codinf of functions, automatic placing of logic cells
• Fast memory (16 words, at address 000..017) and multiplexer to select between this and normal memory (which has been moved to address 020..057)
• Instruction unit 101tootmm half word, an half word swap mux, and an unchanged/zero/one/extend modifier, followed by an mux that select which of these to take
• Instruction unit 110ooamma bit testing, an half word swap mux for the test pattern, an ALU for all the nothing/zero/complement/one modification, and the test pattern "AND" and zero/nonzero detector to control conditional skipping

• Code tidy up, rewrote memory addressing multiplexer
• Used sister project VirtexTools for making graphic renderings of current and all 3 milestones, and used them to describe this projects chip layout

Doing is:

No changes in this project since 2002.11.13 (over 1 year!).

Todo are:

• Instruction unit 010xxxxxx fixed point
• Larger BRAM memory for large test programs, such as KLAD, to enable bigger programs and do some serious testing
• Instruction unit 001xxxxxx byte operations?
• Instruction unit 111dddddd.dooo input/output for making system control and memory management possible and instruction unit 000mooooo user unimplemented ops for being able to run user vs system mode
• Input/output devices to talk with the world outside, at least RS-232 for console terminal and hard disk drives
• Instruction unit 001xxxxxx floating point
• KL/KS/XKL style paged memory managment and KL/XKL style extended addressing
• Built in PC-keyboard/VGA-screen based console terminal
• Massive speed-up using RISC FPA-CPU style multiple register sets, and multiple read and same time writing

Code Download

• entire project: PDP-10.tar.gz Archive
• single files:
  • Java source code
  • textual memory image for test runs
  • Makefile to drive compilation
  • generated processor state logic diagram
  • generated control logic listing
  • compiled program binary
  • generated run log
  • generated placing listfile
  • generated FPGA bitfile
  • script for running bitfile in BoardScope
  • chip layout description

• entire project: PDP-10-20020625.tar.gz Archive
• single files:
  • Java source code
  • textual memory image for test runs
  • Makefile to drive compilation
  • generated processor state logic diagram
  • generated control logic listing
  • compiled program binary
  • generated run log
  • generated placing listfile
  • generated FPGA bitfile
  • script for running bitfile in BoardScope
  • chip layout description
• alt.sys.pdp10 announcement
  

• entire project: PDP-10-20011229.tar.gz Archive
• single files:
  • Java source file
  • design of processor state logic diagram
  • design of control logic
  • compiled source
  • generator run log file
  • generated bitfile
  • script for auto-generating .sld file
  • script for auto-generating .lf file
  • script for compiling .java and generating .bit
  • script for running .bit in BoardScope
  • chip layout description
• alt.sys.pdp10 announcement
  

• entire project: PDP-10-20010516.tar.gz Archive
• single files:
  • control circuit design
  • Java source file
  • compiled source
  • program for ROM
  • generated bitfile
  • chip layout description
• alt.sys.pdp10 announcement
  

Hardware to Run on

Normally FPGA developement ist done on prototype boards, which are just an FPGA plus power supply and programming circuit on an board, with the IOs run out to headers or prototyping area. These are prototype boards I have looked into, to run my stuff on:

• XS40-010XL+ Prototyping Board. My pinout analysis shows too little pins for anything 36bit with its small 84pin PLCC case. Also XC4010XL (40x20 LUT) chip is too small for my 36bit data path
• XSV Virtex Prototyping Board has enough pins, as pinout analysis shows, but too many are already in use, none free for wide 18/36bit memory (existing memory is 16bit) or for missing hard disk interface. Also requires programming its XC95108 CPLD to program FPGA or use RS23 or LPT
• APS-V240 Virtex FPGA Rapid Development Platform has many free pins, as my pinout analysis shows. But still fairly expensive because of XCVx00 chip, and PC104 layout is non-optimal for my intended use
• BurchED has many free pins. No pinout analysis, but it seems to be all IO pins free from pictures. But can only use 8pin OT-PROMs, not EEPROMs. And the manufacturer obsoletes old offerings (such the old XC2S200 needed for my tools) as soon as now ones appear (XC2S300E which is not supported), which makes it bad for other people wanting to build copies of my system, which requires an steady board supply
• Board Module EVALXC2S/XCV/XCVE-HQ240 an nice flexible board with IO pins on the edge and EEPROM sockets. But very expensive, as it uses XCV chips and in particular the required (large and complex) power supply. No pinout analysis, but it seems to be all IO pins free, possibly some with special plugs on them
• Trenz TE-XC2S Spartan-II Development System an nice board, more in my price range. With EEPROM support, programming circuits built in, 4 identical module sockets. But 2 sockets each are on front and back of board, which makes it impossible to use it as "large component" on an other board. No pinout analysis, but it seems to be all IO pins free
• Quickstart QST0201 is similar to the Trenz above. But all sockets on front (and announced both-side usable in next revision), and at edges, so usable as an large component. And manufacturer is interested in making front pannels (has an interest in PDP-8/10/11 cloning). No pinout analysis, but manufacturer claims all IO pins free (makes point that pre-used pins is equal to lossed pins)

But ultimatively I will want this to run on an custom board for FPGA PCs. For this I have started an separate FPGA PC Project

• I have collected together an Hardware Ideas Braindump
• And then turned that into an FPGA PC Board Specification for an ATX size board based on an XCV2S600E FPGA
• While doing that I also specced an smaller (differential) Board Specification for an small ATX or industrial size board based on an XC2S150 FPGA

Auxillary documents

ASCII graphic of Virtex CLB PIPs
list of Virtex BRAM PIPs

Usenet discussions

My alt.sys.pdp10 archive
Early discussion of cloning an PDP-10 in an FPGA
Announcing this project
Modern IO devices for PDP-10 on a FPGA
Who is working on PDP10 hardware emulators/fpgas?
Links to PDP-10 Emulation Webpages
Doug Conroy's PDP-4 done, mentions his PDP-10 plans
Discussion of emulating/replacing IO devices
Doug Conroy's PDP-10 project is definitive, is going to be microcoded, code stored FPGA-external in SRAMs, KA/KL intersection to run ITS
Doug Conroy's PDP-10 project runs ITS on an microcode emulator
FPGA clone commented graphical renderings available

External Stuff (Links)

PDP-10 index, 36 bits forever!
DEC 36-bit computers
DECsystem-10/DECSYSTEM-20 Processor Reference Manual
DEC PDP-10
PDP-10 Software Archive
Project: ts10 (KS-10 and KL-10, but also VAX)
SIMH (emulates many systems, including PDP-10)
KLH10 (KL-10 and KS-10 with NIA20 networking)

This page is by Neil Franklin, last modification 2003.12.25