From: "David G. Conroy" Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Another DEC computer in an FPGA Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 14 Message-ID: Date: Mon, 05 Nov 2001 01:06:52 GMT NNTP-Posting-Host: 64.171.4.17 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1004922412 64.171.4.17 (Mon, 05 Nov 2001 01:06:52 GMT) NNTP-Posting-Date: Mon, 05 Nov 2001 01:06:52 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!newsfeed.gamma.ru!Gamma.RU!dispose.news.demon.net!demon!shale.ftech.net!news.ftech.net!peer1.news.newnet.co.uk!lon1-news.nildram.net!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.frii.net!easynews!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7375 I finished up the PDP-4/X, my 18-bit DEC computer in an FPGA, some time ago, but I never found the time to put the description, the pictures, and the source code on the web until this weekend. http://www.spies.com/~dgc/pdp4x With the PDP-8/X and PDP-4/X done (and a design for a PDP-1/X which uses the same 18-bit printed circuit board as the PDP-4/X within epsilon of done for some time), perhaps it's time to start thinking about the PDP-10/X ;-) Enjoy. dgc ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 05 Nov 2001 20:44:40 +0100 Organization: My own Private Self Lines: 27 Message-ID: <6ud72xuhnb.fsf@chonsp.franklin.ch> References: NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1004989484 454 10.0.3.2 (5 Nov 2001 19:44:44 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 5 Nov 2001 19:44:44 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7376 "David G. Conroy" writes: > http://www.spies.com/~dgc/pdp4x Cool. More cloned hardware for those not fortunate to own originals. > With the PDP-8/X and PDP-4/X done (and a design for > a PDP-1/X which uses the same 18-bit printed circuit board as the PDP-4/X Will the 8/X also run on the new board (simply ignoring 1/3 of bits)? > within epsilon of done for some time), perhaps it's time to start > thinking about the PDP-10/X ;-) I am awaiting the details, implementation ideas, model to be cloned, ... While I am at it, I am nearing milestone 2. Just need to finish test/debug of CA*/JUMP/SKIP/AO*/SP* unit. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Message-ID: <3BE73260.E916A5E2@jetnet.ab.ca> From: Ben Franchuk X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 21 Date: Mon, 05 Nov 2001 17:44:16 -0700 NNTP-Posting-Host: 207.153.6.39 X-Trace: newsfeed.slurp.net 1005018273 207.153.6.39 (Mon, 05 Nov 2001 21:44:33 CST) NNTP-Posting-Date: Mon, 05 Nov 2001 21:44:33 CST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.slurp.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7377 "David G. Conroy" wrote: > > I finished up the PDP-4/X, my 18-bit DEC computer in > an FPGA, some time ago, but I never found the time to put the description, > the pictures, and the source code on the web until this weekend. > > http://www.spies.com/~dgc/pdp4x Nice page! > With the PDP-8/X and PDP-4/X done (and a design for > a PDP-1/X which uses the same 18-bit printed circuit board as the PDP-4/X > within epsilon of done for some time), perhaps it's time to start > thinking about the PDP-10/X ;-) Too easy. How about a real rare bird - PDP/3. http://www.spies.com/~aek/pdf/dec/pdp3/ Ben Franchuk. -- Standard Disclaimer : 97% speculation 2% bad grammar 1% facts. "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk ###### From: David Razler Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Reply-To: davidrazler@home.com Message-ID: References: <3BE73260.E916A5E2@jetnet.ab.ca> X-Newsreader: Forte Agent 1.8/32.548 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 61 Date: Wed, 07 Nov 2001 20:29:31 GMT NNTP-Posting-Host: 65.8.78.154 X-Complaints-To: abuse@home.net X-Trace: news1.rdc2.pa.home.com 1005164971 65.8.78.154 (Wed, 07 Nov 2001 12:29:31 PST) NNTP-Posting-Date: Wed, 07 Nov 2001 12:29:31 PST Organization: Excite@Home - The Leader in Broadband http://home.com/faster Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!out.nntp.be!propagator-SanJose!in.nntp.be!news-in-sanjose!newshub2.rdc1.sfba.home.com!news.home.com!news1.rdc2.pa.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7411 On Mon, 05 Nov 2001 17:44:16 -0700, Ben Franchuk wrote: >"David G. Conroy" wrote: >> >> I finished up the PDP-4/X, my 18-bit DEC computer in >> an FPGA, some time ago, but I never found the time to put the description, >> the pictures, and the source code on the web until this weekend. >> >> http://www.spies.com/~dgc/pdp4x > >Nice page! > >> With the PDP-8/X and PDP-4/X done (and a design for >> a PDP-1/X which uses the same 18-bit printed circuit board as the PDP-4/X >> within epsilon of done for some time), perhaps it's time to start >> thinking about the PDP-10/X ;-) > >Too easy. How about a real rare bird - PDP/3. >http://www.spies.com/~aek/pdf/dec/pdp3/ >Ben Franchuk. Well, I wouldn't mind a *better* 8, what I really want is the moral equivalent of a PDP-10, say as fast as the fastest CPU made, which can be slowed/dumbed down to play PDP-6 or PDP-3. Must include some wahy to divide a modern drive into several 2Mw sectors, eight 128K-wd sectors (or is that 1/2 wd sectors, 'magtape' paper tape reader/punch and handle 100B/T. Oh, and try for a *real* front panel, too Now, with a standardized size, assuming one PCI board for each really different product made before the magic went away, the PDP-1, the PDP3-6-10-20, 4-7-9-15, LINC, PDP5-8(letters), with its own local memory but using the host system's HDC, video/front panel, NIC to do the heavy lifting we could put Every Important DEC Architecture in a single box, and, with luck, have an open slot for PDP-11-VAXen. Put a handle on top of the tower case and you've got The Complete History of Arguably the world's most important computer company of the 1960s&70s in a Box Travelling Roadshow. If we get lucky and the damned fools who did all the mask work to build about 50 Eniac chips and then just shut the whole production line down because it worked to do it right, we'd have Yet Another Computer to add.... Maybe a rainbow-striped case for DEC (using the colors from each of their machines) and a blue one for IBMs on a grid (though mainframes are more difficult to emulate in tight spaces, grey for Univac, The Official State Color(s) of Massachusetts (or a Route 128 sign stencil) for DG, PR1ME and the host of others I'm forgetting, and we have something everyone involved in computers when computers were (or still are) fun would want. ("None of the Class, None of the Cash, None of the Work, Power or Airconditioning as the Real Thing") (Now, whatever happened to my Windows slide-rule emulator) dmr ###### From: aek@spies.com (Al Kossow) Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: Wed, 07 Nov 2001 12:45:03 -0800 Organization: Apple Computer, Inc. Lines: 11 Message-ID: References: <3BE73260.E916A5E2@jetnet.ab.ca> NNTP-Posting-Host: il0502a-dhcp193.apple.com X-Trace: news.apple.com 1005165901 15940 17.205.24.193 (7 Nov 2001 20:45:01 GMT) X-Complaints-To: usenet@news.apple.com NNTP-Posting-Date: 7 Nov 2001 20:45:01 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!howland.erols.net!cpk-news-hub1.bbnplanet.com!paloalto-snf1.gtei.net!news.gtei.net!forum.apple.com!news.apple.com!il0502a-dhcp193.apple.com!user Xref: chonsp.franklin.ch alt.sys.pdp10:7410 In article , davidrazler@home.com wrote: > Now, with a standardized size, assuming one PCI board for each really > different product made before the magic went away, the PDP-1, the > PDP3-6-10-20, 4-7-9-15, The PDP-3 more like a 36 bit version of the PDP-1 than a 6. There has been some speculation that the PDP-2 would have been a 24 bit version of the same general architecture as the 1 and 3. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 08 Nov 2001 00:38:04 +0100 Organization: My own Private Self Lines: 153 Message-ID: <6uzo5yywwz.fsf@chonsp.franklin.ch> References: <3BE73260.E916A5E2@jetnet.ab.ca> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005176287 667 10.0.3.2 (7 Nov 2001 23:38:07 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 7 Nov 2001 23:38:07 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7413 David Razler writes: > On Mon, 05 Nov 2001 17:44:16 -0700, Ben Franchuk > wrote: > > >"David G. Conroy" wrote: > >> > >> With the PDP-8/X and PDP-4/X done (and a design for > >> a PDP-1/X which uses the same 18-bit printed circuit board as the PDP-4/X > >> within epsilon of done for some time), perhaps it's time to start > >> thinking about the PDP-10/X ;-) > > > >Too easy. How about a real rare bird - PDP/3. > > Well, I wouldn't mind a *better* 8, what I really want is the moral > equivalent of a PDP-10, say as fast as the fastest CPU made, Which is roughly the speed of TS-10 emulator on an 800MHz PIII, IIRC the discussion about 3/4 to 1 year ago. > be slowed/dumbed down to play PDP-6 or PDP-3. Slow down KL-10 -> KI-10 -> KA-10 -> PDP-6 speed is easy, just slow the clock. I am aiming for maximal speed (I expect 3 to 10 KL-10s) in my FPGA 10[1] on exactly the base of that one can slow the clock for "real" spead. [1] http://neil.franklin.ch/Projects/PDP-10/ OTOH dumb down PDP-6 -> PDP-3 means changing the instruction set. That needs an complete separate FPGA config file, and so also design (but possible derived, reusing parts of existing design). > Must include some wahy > to divide a modern drive into several 2Mw sectors, eight 128K-wd > sectors (or is that 1/2 wd sectors, Those sectors seem terribly large. AFAIK 128*36bit is what is to aim for. Use 2*512*8bit to store 1*128*36bit. Then take RP06 or RP20 sector/track/cylinder and compute offsets into an modern HD. To save complex multiplications in the controller, just waste space by pretending that sectors/track and tracks/cylinder and cylinders/drive are rounded up to next 2^n. RP06 still fits in 1GByte HD, so an (small) 8GB HD is enough for an entirely filled Massbus. This is what I am intending to do. > 'magtape' paper > tape reader/punch That one is relatively easy. FDs are fairly simple things to control. Now getting an FD drive in 5 years may be a problem :-). > and handle 100B/T. That one not so. Ethernet (particularly 100Mbit/s) is not that simple. Apart from the HD connection the thing I dread the most. > Oh, and try for a *real* front panel, too That is more mechanical work than electrical. So make it optional (say an second low-logic/high-pincount FPGA linked to the main one). > Now, with a standardized size, assuming one PCI board PCI is difficult. Better use an standallone board with FPGA and memory and IO. Sort of like an all-in-one PC motherboard with FPGA inside instead of Intel inside. > for each really > different product made before the magic went away, Or one board that can run FPGA configs for all systems. Simply needs enough resources (bus width[2], max memory[3], IO device selection[4]) for the largest architecture and then only use (or even insert parts for) those architectures you want to run. [2] 36bit, allows 18bit with interleaved memory, 32bit with 4 wasted bits, 16bit with 4 waste and interleave, 24bit with 12 waste, 12bit with 12 waste and interleave. And those mad 60bit guys will just have to waste 6 and do 2 30bit accesses. [3] offer choice of small/simple SRAM for small machines, larger EDO DRAM for what was large machines, and SDRAM for expanding large old machines to an size that will take todays[5] software. [4] EIDE or SCSI Disk, RS-232 terminal/papertape, FD for fast papertape or magtape, key/video for implementing built in console terminal, expansion connector(s) or prototyping space for extensions. [5] think of an 10 running at roughly 486 speed with 16-64M SDRAM and then porting an modern Mail/News/Web setup to it. Do alt.sys.pdp* and pages referenced here from an clone PDP! A few ideas on this: http://neil.franklin.ch/Projects/PDP-10/Hardware Ideal this would be an standard open source (anyone can manufacture) FPGA IO pinout, so that anyone with an board can run anyone elses systems. Would also generate higher manufacturing volume for the design, making them cheaper. I suppose that is enough for nice ideas overdose. > with its own local > memory but using the host system's HDC, video/front panel, NIC to do > the heavy lifting Why not implement them direct in the FPGA design? Gets rid of the host system and gives an far better look&feel. > we could put Every Important DEC Architecture in > a single box, and, with luck, have an open slot for PDP-11-VAXen. Or just one board and a switchable (or even pluggable) set of FPGA config PROMs. > mother board makers with SLOTS!!!!!> So drop them (the motherboard makers). :-) > If we get lucky and the damned fools > who did all the mask work to build about 50 Eniac chips and then just > shut the whole production line down because it worked to do it right, > we'd have Yet Another Computer to add.... Forget mask and other ASIC stuff. FPGAs are nearly as good. Definitely sufficient for what we need and single part without big (from $10k on) upfront pre-production investment costs. > (Now, whatever happened to my Windows slide-rule emulator) It crashed. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: Thu, 08 Nov 01 09:22:33 GMT Organization: UltraNet Communications, Inc. Lines: 18 Message-ID: <9sdppq$ap2$1@bob.news.rcn.net> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> X-Trace: UmFuZG9tSVbrU35zfCB2xZYUoWhZBSpqwBmZM5SzXEy7XoFc/LMbSD1FDA2Ha6sU X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 8 Nov 2001 11:20:26 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-102-80 Xref: chonsp.franklin.ch alt.sys.pdp10:7416 In article <6uzo5yywwz.fsf@chonsp.franklin.ch>, Neil Franklin wrote: >David Razler writes: > >> On Mon, 05 Nov 2001 17:44:16 -0700, Ben Franchuk >> wrote: >> (Now, whatever happened to my Windows slide-rule emulator) > >It crashed. Huh. Then yours is better than mine. All mine does is display blue with an implied "Guess!" printed behind it. /BAH Subtract a hundred and four for e-mail. ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 8 Nov 2001 18:01:55 GMT Organization: California Institute of Technology, Pasadena Lines: 75 Message-ID: <9sehaj$rm5@gap.cco.caltech.edu> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> NNTP-Posting-Host: lek.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.wirehub.nl!lon1-news.nildram.net!62.24.128.9.MISMATCH!news-1.opaltelecom.net!news-out.spamkiller.net!propagator-la!news-in-la.newsfeeds.com!news-in.superfeed.net!news.exit.com!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch alt.sys.pdp10:7418 Neil Franklin writes: (big snip) >> Now, with a standardized size, assuming one PCI board >PCI is difficult. Better use an standallone board with FPGA and memory >and IO. Sort of like an all-in-one PC motherboard with FPGA inside >instead of Intel inside. The way the IBM P/390 works is to have the processor/memory on a PCI board. A program runs on the host system that loads the microprogram, and then performs all I/O requests through host system resources. Emulated disks are files on the host system. The P/390 issues an I/O instruction which signals (maybe through an interrupt) the host, which processes the I/O operation and signals the P/390 that it is done. While PCI may be difficult, once it is done all the rest of the I/O is done in normal software on the host. All the calculations to find disk sector offsets, etc. Emulated tapes can either be real host tapes or files on the host file system specially formatted as emulated tapes. (To keep the blocking information not normally kept on disk files.) >> for each really >> different product made before the magic went away, >Or one board that can run FPGA configs for all systems. Simply needs >enough resources (bus width[2], max memory[3], IO device selection[4]) >for the largest architecture and then only use (or even insert parts >for) those architectures you want to run. >[2] 36bit, allows 18bit with interleaved memory, 32bit with 4 wasted >bits, 16bit with 4 waste and interleave, 24bit with 12 waste, 12bit >with 12 waste and interleave. And those mad 60bit guys will just have >to waste 6 and do 2 30bit accesses. >[3] offer choice of small/simple SRAM for small machines, larger EDO >DRAM for what was large machines, and SDRAM for expanding large old >machines to an size that will take todays[5] software. >[4] EIDE or SCSI Disk, RS-232 terminal/papertape, FD for fast >papertape or magtape, key/video for implementing built in console >terminal, expansion connector(s) or prototyping space for extensions. >[5] think of an 10 running at roughly 486 speed with 16-64M SDRAM and >then porting an modern Mail/News/Web setup to it. Do alt.sys.pdp* and >pages referenced here from an clone PDP! >A few ideas on this: http://neil.franklin.ch/Projects/PDP-10/Hardware >Ideal this would be an standard open source (anyone can manufacture) >FPGA IO pinout, so that anyone with an board can run anyone elses systems. >Would also generate higher manufacturing volume for the design, making >them cheaper. >I suppose that is enough for nice ideas overdose. >> with its own local >> memory but using the host system's HDC, video/front panel, NIC to do >> the heavy lifting >Why not implement them direct in the FPGA design? Gets rid of the host >system and gives an far better look&feel. Because it is a LOT of work. While processor registers work well in an FPGA, I/O calculations don't. >> we could put Every Important DEC Architecture in >> a single box, and, with luck, have an open slot for PDP-11-VAXen. >Or just one board and a switchable (or even pluggable) set of FPGA >config PROMs. Load from the host file system, not PROMs. -- glen ###### From: jrlatala@shell.golden.net Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Organization: A poorly-installed InterNetNews site Lines: 17 Message-ID: <9sehdt$c6r$1@shell.golden.net> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> Date: 8 Nov 2001 13:03:41 -0500 NNTP-Posting-Host: 199.166.210.115 X-Complaints-To: abuse@golden.net X-Trace: radon.golden.net 1005242623 199.166.210.115 (Thu, 08 Nov 2001 13:03:43 EST) NNTP-Posting-Date: Thu, 08 Nov 2001 13:03:43 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!feed2.onemain.com!feed1.onemain.com!newsswitch.lcs.mit.edu!sunqbc.risq.qc.ca!cpk-news-hub1.bbnplanet.com!news.gtei.net!newsfeed1.cidera.com!Cidera!radon.golden.net!shell.golden.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7417 In article <6uzo5yywwz.fsf@chonsp.franklin.ch>, Neil Franklin wrote: >> Oh, and try for a *real* front panel, too > >That is more mechanical work than electrical. So make it optional (say >an second low-logic/high-pincount FPGA linked to the main one). If you end up sticking this all onto a board that plugs into a bus then how about making a soft front panel? You could use X-Windows to draw a pretty panel that you could then poke at with the mouse. If you had access to a real front panel and a digital camera you could go the extra step for a little more realism. -- john R. Latala jrlatala@golden.net ###### From: enders@bolshoi.cc.misu.nodak.edu (Todd Enders) Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA X-Newsreader: RadicalNews (TM) 1.1(n) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehdt$c6r$1@shell.golden.net> Lines: 16 Message-ID: Date: Thu, 08 Nov 2001 18:43:53 GMT NNTP-Posting-Host: 24.36.5.169 X-Complaints-To: abuse@home.net X-Trace: news1.rdc1.ne.home.com 1005245033 24.36.5.169 (Thu, 08 Nov 2001 10:43:53 PST) NNTP-Posting-Date: Thu, 08 Nov 2001 10:43:53 PST Organization: Excite@Home - The Leader in Broadband http://home.com/faster Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!newshub2.rdc1.sfba.home.com!news.home.com!news1.rdc1.ne.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7423 In <9sehdt$c6r$1@shell.golden.net> jrlatala@shell.golden.net wrote: > If you end up sticking this all onto a board that plugs into a bus then > how about making a soft front panel? You could use X-Windows to draw a > pretty panel that you could then poke at with the mouse. If you had > access to a real front panel and a digital camera you could go the extra > step for a little more realism. > A soft front panel would be OK, if one must, but *I* personally prefer the tactile experience of manipulating real switches, and watching real blinkin' lights. :-) Rather like the difference between watching a concert on TV and attending a live performance. :-) Todd ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 08 Nov 2001 21:56:18 +0100 Organization: My own Private Self Lines: 67 Message-ID: <6ubsidasnh.fsf@chonsp.franklin.ch> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005252981 456 10.0.3.2 (8 Nov 2001 20:56:21 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 8 Nov 2001 20:56:21 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7426 gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > Neil Franklin writes: > > >> Now, with a standardized size, assuming one PCI board > > >PCI is difficult. Better use an standallone board with FPGA and memory > >and IO. Sort of like an all-in-one PC motherboard with FPGA inside > >instead of Intel inside. > > The way the IBM P/390 works is to have the processor/memory on > a PCI board. A program runs on the host system that loads the > microprogram, and then performs all I/O requests through host > system resources. Emulated disks are files on the host system. The same way the Inmos Transputer boards worked (I have a 2nd source manufacturers copy of one of them). The host "server" program gave lousy IO performance, and simply felt like a PC with a bit more processor and different software, instead of like an real different computer. So in the end I wrote client-server code, PC as client, and Transputer as computer server. Just a fast PC in appearance. > >> with its own local > >> memory but using the host system's HDC, video/front panel, NIC to do > >> the heavy lifting > > >Why not implement them direct in the FPGA design? Gets rid of the host > >system and gives an far better look&feel. > > Because it is a LOT of work. While processor registers work well > in an FPGA, I/O calculations don't. But only doing it in real hardware gives the true immediate down in the guts hardware look and feel. If you are going to do all IO in software to save work, then why not get rid of the FPGA and do the processor also in software? Modern CPUs can emulate up to early 1980s machines in real speed. See Simh and TS-10. And connect an real VT terminal to an hidden PCs serial port and run the emulator with that as IO, and even the display is right (even original). So cloning in FPGA is for those that want more realism than an window on an GUI desktop. Real dedicated hardware. So IO also in hardware, how it really was. > >> we could put Every Important DEC Architecture in > >> a single box, and, with luck, have an open slot for PDP-11-VAXen. > > >Or just one board and a switchable (or even pluggable) set of FPGA > >config PROMs. > > Load from the host file system, not PROMs. If you have a host system. Which I prefer to avoid. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: Fri, 09 Nov 01 09:04:23 GMT Organization: UltraNet Communications, Inc. Lines: 21 Message-ID: <9sgd42$6kj$1@bob.news.rcn.net> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> X-Trace: UmFuZG9tSVZYOCrlVbieanOQ+Ja0/srNmzV0oz0afHv8DvJFnHqZtJPNRt4gNcp0 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 9 Nov 2001 11:02:26 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!skynet.be!skynet.be!europa.netcrusader.net!usenetserver.com!207.172.3.44!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-216-4 Xref: chonsp.franklin.ch alt.sys.pdp10:7436 In article <3BEAC3A7.822A3E04@jetnet.ab.ca>, Ben Franchuk wrote: >Neil Franklin wrote: >> And connect an real VT terminal to an hidden PCs serial port and run >> the emulator with that as IO, and even the display is right (even >> original). > >The idea of a huge puter from the 60's on a small PCB feels right. >Plus who wants to boot windows just to run a 8k focal program. >What about real nonvolatile memory. More importantly, you'ld have all sources for the system which isn't true of anything from Misoft. Also, do not underestimate their latest ploy of claiming ownership for anything running on their software layer. /BAH Subtract a hundred and four for e-mail. ###### Message-ID: <3BEAC3A7.822A3E04@jetnet.ab.ca> From: Ben Franchuk X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 36 Date: Thu, 08 Nov 2001 10:40:55 -0700 NNTP-Posting-Host: 207.153.6.46 X-Trace: newsfeed.slurp.net 1005260624 207.153.6.46 (Thu, 08 Nov 2001 17:03:44 CST) NNTP-Posting-Date: Thu, 08 Nov 2001 17:03:44 CST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.slurp.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7433 Neil Franklin wrote: > > Because it is a LOT of work. While processor registers work well > > in an FPGA, I/O calculations don't. This has got me confused? What I/O will not work? > But only doing it in real hardware gives the true immediate down in > the guts hardware look and feel. > If you are going to do all IO in software to save work, then why not > get rid of the FPGA and do the processor also in software? Modern CPUs > can emulate up to early 1980s machines in real speed. See Simh and TS-10. Would not a scsii drive be a better interface than a IDE drive. > And connect an real VT terminal to an hidden PCs serial port and run > the emulator with that as IO, and even the display is right (even > original). The idea of a huge puter from the 60's on a small PCB feels right. Plus who wants to boot windows just to run a 8k focal program. What about real nonvolatile memory. > So cloning in FPGA is for those that want more realism than an window on > an GUI desktop. Real dedicated hardware. So IO also in hardware, how > it really was. > > If you have a host system. Which I prefer to avoid. Use anti-fuse FPGA's. Ben Franchuk. -- Live "Pre-historic Cpu's" -- and you thought they were extinct. www.jetnet.ab.ca/users/bfranchuk/index.html ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 8 Nov 2001 23:40:45 GMT Organization: California Institute of Technology, Pasadena Lines: 70 Message-ID: <9sf55t$btk@gap.cco.caltech.edu> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> NNTP-Posting-Host: yak.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news-stu1.dfn.de!news-koe1.dfn.de!news-fra1.dfn.de!news-lei1.dfn.de!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsswitch.lcs.mit.edu!news.uchicago.edu!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch alt.sys.pdp10:7443 Neil Franklin writes: >gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: >> Neil Franklin writes: >> >> >> Now, with a standardized size, assuming one PCI board >> >> >PCI is difficult. Better use an standallone board with FPGA and memory >> >and IO. Sort of like an all-in-one PC motherboard with FPGA inside >> >instead of Intel inside. >> >> The way the IBM P/390 works is to have the processor/memory on >> a PCI board. A program runs on the host system that loads the >> microprogram, and then performs all I/O requests through host >> system resources. Emulated disks are files on the host system. >The same way the Inmos Transputer boards worked (I have a 2nd source >manufacturers copy of one of them). >The host "server" program gave lousy IO performance, and simply felt >like a PC with a bit more processor and different software, instead >of like an real different computer. >So in the end I wrote client-server code, PC as client, and Transputer >as computer server. Just a fast PC in appearance. >> >> with its own local >> >> memory but using the host system's HDC, video/front panel, NIC to do >> >> the heavy lifting >> >> >Why not implement them direct in the FPGA design? Gets rid of the host >> >system and gives an far better look&feel. >> >> Because it is a LOT of work. While processor registers work well >> in an FPGA, I/O calculations don't. >But only doing it in real hardware gives the true immediate down in >the guts hardware look and feel. >If you are going to do all IO in software to save work, then why not >get rid of the FPGA and do the processor also in software? Modern CPUs >can emulate up to early 1980s machines in real speed. See Simh and TS-10. This is a hard question. What are you going to do for the card reader or paper tape reader or punch? Half-inch tape or DECtape? Real or emulated? Now, one reason for the FPGA is to go faster than the software simulated processor, and in most cases host I/O will be fast enough for an FPGA processor. The goal of P/390 was not as a museum piece, but to run real programs and OS for commercial purposes. IBM also has an I/O board that supports the channel interface for real I/O devices, except for disks and drums. How did the real processor do I/O? Is it all written in microcode, or is it done by external, programmable, boxes? (S/360/370/390 have I/O channels, which are pretty much programmable processors specifically for doing I/O operations.) >And connect an real VT terminal to an hidden PCs serial port and run >the emulator with that as IO, and even the display is right (even >original). >So cloning in FPGA is for those that want more realism than an window on >an GUI desktop. Real dedicated hardware. So IO also in hardware, how >it really was. So, how did PDP-10 I/O really work? I was only ever at the terminal end of one. -- glen ###### From: "Zane H. Healy" Subject: Re: Another DEC computer in an FPGA Newsgroups: alt.sys.pdp10,alt.sys.pdp8 References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> Organization: Aracnet User-Agent: tin/1.4.4-20000803 ("Vet for the Insane") (UNIX) (Linux/2.2.19 (i686)) Lines: 15 Message-ID: X-Complaints-To: abuse@usenetserver.com X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly. NNTP-Posting-Date: Thu, 08 Nov 2001 18:58:25 EST Date: Thu, 08 Nov 2001 23:58:25 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-hub.siol.net!cyclone.bc.net!sjcppf01.usenetserver.com!e420r-sjo4.usenetserver.com!usenetserver.com!sjcpnn01.usenetserver.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7459 In alt.sys.pdp10 Ben Franchuk wrote: > Would not a scsii drive be a better interface than a IDE drive. It seems to me that the best choice would be to create an interface that lets you plug in an interface for the drive of your choice. That way once SCSI and EIDE drives get hard to find, you can build and interface for whatever the current type drive is, and just plug it in. > The idea of a huge puter from the 60's on a small PCB feels right. > Plus who wants to boot windows just to run a 8k focal program. > What about real nonvolatile memory. Agreed, I don't like the idea of a host system. Zane ###### From: "Zane H. Healy" Subject: Re: Another DEC computer in an FPGA Newsgroups: alt.sys.pdp10,alt.sys.pdp8 References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehdt$c6r$1@shell.golden.net> Organization: Aracnet User-Agent: tin/1.4.4-20000803 ("Vet for the Insane") (UNIX) (Linux/2.2.19 (i686)) Lines: 13 Message-ID: X-Complaints-To: abuse@usenetserver.com X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly. NNTP-Posting-Date: Thu, 08 Nov 2001 19:00:26 EST Date: Fri, 09 Nov 2001 00:00:26 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!skynet.be!skynet.be!europa.netcrusader.net!208.184.7.66!newsfeed1.cidera.com!Cidera!sjcppf01.usenetserver.com!e420r-sjo4.usenetserver.com!usenetserver.com!sjcpnn01.usenetserver.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7458 In alt.sys.pdp10 jrlatala@shell.golden.net wrote: > If you end up sticking this all onto a board that plugs into a bus then > how about making a soft front panel? You could use X-Windows to draw a > pretty panel that you could then poke at with the mouse. If you had > access to a real front panel and a digital camera you could go the extra > step for a little more realism. If you're doing a 'soft' front panel, why not just run the entire system under emulation? Why go to the trouble of putting the CPU into an FPGA when you already have emulators? Real hardware is the way to go if you're reimplementing a CPU in FPGA. Zane ###### From: jrlatala@shell.golden.net Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Organization: A poorly-installed InterNetNews site Lines: 29 Message-ID: <9sfml7$eoq$1@shell.golden.net> References: <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehdt$c6r$1@shell.golden.net> Date: 8 Nov 2001 23:39:03 -0500 NNTP-Posting-Host: 199.166.210.115 X-Complaints-To: abuse@golden.net X-Trace: radon.golden.net 1005280747 199.166.210.115 (Thu, 08 Nov 2001 23:39:07 EST) NNTP-Posting-Date: Thu, 08 Nov 2001 23:39:07 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!dca6-feed2.news.digex.net!intermedia!newsfeed1.cidera.com!Cidera!radon.golden.net!shell.golden.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7438 In article , Todd Enders wrote: >In <9sehdt$c6r$1@shell.golden.net> jrlatala@shell.golden.net wrote: >> If you end up sticking this all onto a board that plugs into a bus then >> how about making a soft front panel? You could use X-Windows to draw a >> pretty panel that you could then poke at with the mouse. If you had >> access to a real front panel and a digital camera you could go the extra >> step for a little more realism. >> > A soft front panel would be OK, if one must, but *I* personally prefer the >tactile experience >of manipulating real switches, and watching real blinkin' lights. :-) Rather >like the difference >between watching a concert on TV and attending a live performance. :-) True but if the choice is between a soft front panel and no panel then I'll take the soft panel. The nice thing about the soft panel is that it won't break, doesn't need maintenance and (most of all) doesn't take up any space. How much physical room would you need for the front panels of half a dozen of the early PDPs? My hands on exposure to early PDPs started with the -8 and -12 series. The closest I got to anything before that was looking at a -6 through a window. My memory says the front panel for that was a lot biggr than the panels for the -8 and -12. On the -12 defining the term panel gets tricky depending on whether you consider the analog input knobs as part of the panel or not. -- john R. Latala jrlatala@golden.net ###### From: Tim Shoppa Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 9 Nov 2001 07:43:48 -0800 Organization: Trailing-Edge Technologies Lines: 15 Message-ID: <9sgtjk01ncd@drn.newsguy.com> References: <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehdt$c6r$1@shell.golden.net> <9sfml7$eoq$1@shell.golden.net> NNTP-Posting-Host: p-118.newsdawg.com X-Newsreader: Direct Read News 2.90 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!newsfeed.media.kyoto-u.ac.jp!pln-e!spln!dex!extra.newsguy.com!newsp.newsguy.com!drn Xref: chonsp.franklin.ch alt.sys.pdp10:7437 In article <9sfml7$eoq$1@shell.golden.net>, jrlatala@shell.golden.net says... >True but if the choice is between a soft front panel and no panel then >I'll take the soft panel. The nice thing about the soft panel is that it >won't break, doesn't need maintenance Some of us have kept a set of old bulb-pullers in our toolbox just in case we acquire a machine with real light bulbs on the front panel again. Mine say "JONARD TUCKAHOE N.Y." on the tool handle - is there any chance that they're (where "they" == Jonard) still manufacturing these? I know that I've seen phone company folks with a special set of Jonard pay-phone tools in the past couple of years. Tim. ###### From: Arthur Krewat Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Organization: Kilonet.net Lines: 46 Message-ID: <3BEC0125.798C3186@bartek.dontspamme.net> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.78 [en] (X11; U; SunOS 5.8 i86pc) X-Accept-Language: en Date: Fri, 09 Nov 2001 16:17:54 GMT NNTP-Posting-Host: 24.186.100.134 X-Trace: news02.optonline.net 1005322674 24.186.100.134 (Fri, 09 Nov 2001 11:17:54 EST) NNTP-Posting-Date: Fri, 09 Nov 2001 11:17:54 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!feed2.onemain.com!feed1.onemain.com!cyclone2.usenetserver.com!usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7448 jmfbahciv@aol.com wrote: > > In article <3BEAC3A7.822A3E04@jetnet.ab.ca>, > Ben Franchuk wrote: > >Neil Franklin wrote: > > > >> And connect an real VT terminal to an hidden PCs serial port and run > >> the emulator with that as IO, and even the display is right (even > >> original). > > > >The idea of a huge puter from the 60's on a small PCB feels right. > >Plus who wants to boot windows just to run a 8k focal program. > >What about real nonvolatile memory. > > More importantly, you'ld have all sources for the system which > isn't true of anything from Misoft. Also, do not underestimate > their latest ploy of claiming ownership for anything running on > their software layer. Jeez, talk about microsoft-centric thinking - ever hear of UNIX or LINUX ??? Supposedly, you can even get the source to Solaris now, although I don't know if you could recompile the whole thing. Just because it's a PC (piece-of-crap) doesn't mean that you have to run Windows. Following this thread, it's obvious: Everyone wants something different. If whoever makes the FPGA keeps that in mind, everyone will be happy. Soft front-end, hard front-end (no jokes please), NO front-end, whatever... I still need to get my LA120's out of storage and connect one up to my PC(!) Personally, I'm happy with what I have now, SIMH/TS10 - going too far back into realism is a little too unreal for me :) To me, as long as the simulation is perfect, it's much more cost-effective to run it on a PC as software instead of getting an FPGA PCB built - although I have enough connections, I could probably get it done quickly as long as I had a net list and the VHDL (or whatever the hell they are programming FPGA's in these days :) aak ###### Message-ID: <3BEC0350.DE90B51C@jetnet.ab.ca> From: Ben Franchuk X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehdt$c6r$1@shell.golden.net> <9sfml7$eoq$1@shell.golden.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 31 Date: Fri, 09 Nov 2001 09:24:48 -0700 NNTP-Posting-Host: 207.153.6.36 X-Trace: newsfeed.slurp.net 1005322947 207.153.6.36 (Fri, 09 Nov 2001 10:22:27 CST) NNTP-Posting-Date: Fri, 09 Nov 2001 10:22:27 CST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.slurp.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7432 jrlatala@shell.golden.net wrote: > > True but if the choice is between a soft front panel and no panel then > I'll take the soft panel. The nice thing about the soft panel is that it > won't break, doesn't need maintenance and (most of all) doesn't take up > any space. How much physical room would you need for the front panels of > half a dozen of the early PDPs? My hands on exposure to early PDPs started > with the -8 and -12 series. The closest I got to anything before that was > looking at a -6 through a window. My memory says the front panel for that > was a lot biggr than the panels for the -8 and -12. On the -12 defining > the term panel gets tricky depending on whether you consider the analog > input knobs as part of the panel or not. If you have hardware development of any kind you need a front panel. Developing a 12/24 bit cpu in a FPGA I needed a few leds (6) to tell me important real time information like a wire to a data bit broke in the ribbon cable to memory and other useful stuff. Now that I got the FPGA working ( mostly ) I removed the leds. Here is nice design for a PDP-11 clone? A 486 in custom rack with lights/switchs running a PDP 11 emulator. http://home.hetnet.nl/~tshaj/pdpsite/homebrew/startframe.html If this works for a PDP-11 why not another PDP-??? Ben Franchuk. -- Live "Pre-historic Cpu's" -- and you thought they were extinct. www.jetnet.ab.ca/users/bfranchuk/index.html ###### Message-ID: <3BEC320A.6553BB35@jetnet.ab.ca> From: Ben Franchuk X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 20 Date: Fri, 09 Nov 2001 12:44:10 -0700 NNTP-Posting-Host: 207.153.6.47 X-Trace: newsfeed.slurp.net 1005337493 207.153.6.47 (Fri, 09 Nov 2001 14:24:53 CST) NNTP-Posting-Date: Fri, 09 Nov 2001 14:24:53 CST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.slurp.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7431 Rich Alderson wrote: > > Arthur Krewat writes: > > > To me, as long as the simulation is perfect, it's much more cost-effective to > > run it on a PC as software instead of getting an FPGA PCB built - although I > > have enough connections, I could probably get it done quickly as long as I > > had a net list and the VHDL (or whatever the hell they are programming FPGA's > > in these days :) > > VHDL, in the best homes... At risk at starting a war, schematic entry if done right is best. I like to see what I got, not after some program mangles my data. HDL's are not portable since features to make full use of FPGA's are not portable in my view. Ben Franchuk. -- Live "Pre-historic Cpu's" -- and you thought they were extinct. www.jetnet.ab.ca/users/bfranchuk/index.html ###### From: Rich Alderson Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 09 Nov 2001 14:51:50 -0500 Organization: Systems Administration, XKL LLC, Redmond WA 98052 Lines: 13 Sender: alderson+news@panix1.panix.com Message-ID: References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> NNTP-Posting-Host: panix1.panix.com X-Trace: news.panix.com 1005335513 27756 166.84.1.1 (9 Nov 2001 19:51:53 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: 9 Nov 2001 19:51:53 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsswitch.lcs.mit.edu!bloom-beacon.mit.edu!panix!news.panix.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7444 Arthur Krewat writes: > To me, as long as the simulation is perfect, it's much more cost-effective to > run it on a PC as software instead of getting an FPGA PCB built - although I > have enough connections, I could probably get it done quickly as long as I > had a net list and the VHDL (or whatever the hell they are programming FPGA's > in these days :) VHDL, in the best homes... -- Rich Alderson alderson+news@panix.com "You get what anybody gets. You get a lifetime." --Death, of the Endless ###### From: "Zane H. Healy" Subject: Re: Another DEC computer in an FPGA Newsgroups: alt.sys.pdp10,alt.sys.pdp8 References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> Organization: Aracnet User-Agent: tin/1.4.4-20000803 ("Vet for the Insane") (UNIX) (Linux/2.2.19 (i686)) Lines: 10 Message-ID: X-Complaints-To: abuse@usenetserver.com X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly. NNTP-Posting-Date: Fri, 09 Nov 2001 16:21:11 EST Date: Fri, 09 Nov 2001 21:21:11 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cyclone.bc.net!sjcppf01.usenetserver.com!e420r-sjo4.usenetserver.com!usenetserver.com!sjcpnn01.usenetserver.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7460 In alt.sys.pdp10 Ben Franchuk wrote: > At risk at starting a war, schematic entry if done right is best. > I like to see what I got, not after some program mangles my data. > HDL's are not portable since features to make full use of FPGA's > are not portable in my view. Out of curiousity, what do you like using for schematic entry? There isn't any software for this that runs on Linux is there? Zane ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 10 Nov 2001 19:24:45 +0100 Organization: My own Private Self Lines: 59 Message-ID: <6uvggifpqq.fsf@chonsp.franklin.ch> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005416686 506 10.0.3.2 (10 Nov 2001 18:24:46 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 10 Nov 2001 18:24:46 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7462 gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > Neil Franklin writes: > >gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > > >> >Why not implement them direct in the FPGA design? Gets rid of the host > >> >system and gives an far better look&feel. > >> > >> Because it is a LOT of work. While processor registers work well > >> in an FPGA, I/O calculations don't. > > >But only doing it in real hardware gives the true immediate down in > >the guts hardware look and feel. > > >If you are going to do all IO in software to save work, then why not > >get rid of the FPGA and do the processor also in software? Modern CPUs > >can emulate up to early 1980s machines in real speed. See Simh and TS-10. > > This is a hard question. What are you going to do for the card reader > or paper tape reader or punch? Half-inch tape or DECtape? Real > or emulated? As I have neither original drives (OK, TU-56 should be gettable due to the many made for PDP-8) nor the mechanical abilities to make them, I will be either doing entirely without (just console, tty, disk, net IO) or would have to simulate them using RS232 lines or floppy drives. > Now, one reason for the FPGA is to go faster than the > software simulated processor, and in most cases host I/O will be fast > enough for an FPGA processor. One reason. My reasons are more exploration of FPGAs, fun in programming, wanting to make an processor chip, getting a bit of that old hardware feel of immediacity, etc. Of course having one fast enough and with enough memory to try and use daily, and so get away from todays crap architectures, is an far future aim. > How did the real processor do I/O? Is it all written in microcode, > or is it done by external, programmable, boxes? (S/360/370/390 > > So, how did PDP-10 I/O really work? I was only ever at the terminal > end of one. AFAIK (I am only getting into them now, never used originals) a set of 8 IO instructions triggered 4 types of one-word data transmissions over an IO device bus with max 128 device IDs. Slower devices relied entirely on such transfers, sometimes triggered by interrupts, faster devices only recieve commands ans memory addresses via this way and then fetch/put data directly to memory. Actually nearer to PC IO than to S/360etc IO. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 10 Nov 2001 19:28:46 +0100 Organization: My own Private Self Lines: 29 Message-ID: <6usnbmfpk1.fsf@chonsp.franklin.ch> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005416927 506 10.0.3.2 (10 Nov 2001 18:28:47 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 10 Nov 2001 18:28:47 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7463 "Zane H. Healy" writes: > In alt.sys.pdp10 Ben Franchuk wrote: > > Would not a scsii drive be a better interface than a IDE drive. > > It seems to me that the best choice would be to create an interface that > lets you plug in an interface for the drive of your choice. That way once > SCSI and EIDE drives get hard to find, you can build and interface for > whatever the current type drive is, and just plug it in. And that should be fairly easy, by simply putting both connectors on the board, sharing the same FPGA pins, and then simply compiling in one or the other device into the FPGA. Added that to the hardware ideas file [1]. [1] http://neil.franklin.ch/Projects/PDP-10/Hardware > > The idea of a huge puter from the 60's on a small PCB feels right. Yes! And this small thing is n times faster than the big original. :-) -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 10 Nov 2001 19:32:48 +0100 Organization: My own Private Self Lines: 39 Message-ID: <6upu6qfpdb.fsf@chonsp.franklin.ch> References: <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehdt$c6r$1@shell.golden.net> <9sfml7$eoq$1@shell.golden.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005417169 506 10.0.3.2 (10 Nov 2001 18:32:49 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 10 Nov 2001 18:32:49 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7464 jrlatala@shell.golden.net writes: > In article , > Todd Enders wrote: > >In <9sehdt$c6r$1@shell.golden.net> jrlatala@shell.golden.net wrote: > >> If you end up sticking this all onto a board that plugs into a bus then > >> how about making a soft front panel? You could use X-Windows to draw a > >> > > A soft front panel would be OK, if one must, but *I* personally prefer the > >tactile experience > >of manipulating real switches, and watching real blinkin' lights. :-) > > True but if the choice is between a soft front panel and no panel then > I'll take the soft panel. But making an (optinal) hardware pannel is not a big problem. Take an normal 2.54mm raster board, put in LEDs and switches. Wire in some de-muxers to drive it. Connect to a few lines of the FPGA. > The nice thing about the soft panel is that it > won't break, doesn't need maintenance With LEDs (and yes there exist white ones today) and modern switches they should not break any more often than an keyboard does. > and (most of all) doesn't take up > any space. How much physical room would you need for the front panels of > half a dozen of the early PDPs? Make an single universal pannel and ignore the exxess LEDs and switches. Not optimal but space saving. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: Dave Cherkus Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 10 Nov 2001 21:21:41 GMT Organization: A bit Lines: 53 Message-ID: References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> NNTP-Posting-Host: dsl.cherkus.mv.com X-Trace: pyrite.mv.net 1005427301 802 207.22.21.47 (10 Nov 2001 21:21:41 GMT) X-Complaints-To: abuse@mv.com NNTP-Posting-Date: 10 Nov 2001 21:21:41 GMT User-Agent: Xnews/4.06.22 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!bstnma1-snf1.gtei.net!news.gtei.net!news.mv.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7466 Neil Franklin wrote in news:6uvggifpqq.fsf@chonsp.franklin.ch: > gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: >> How did the real processor do I/O? Is it all written in microcode, or >> is it done by external, programmable, boxes? (S/360/370/390 >> >> So, how did PDP-10 I/O really work? I was only ever at the terminal >> end of one. > > AFAIK (I am only getting into them now, never used originals) a set of > 8 IO instructions triggered 4 types of one-word data transmissions > over an IO device bus with max 128 device IDs. > > Slower devices relied entirely on such transfers, sometimes triggered > by interrupts, faster devices only recieve commands ans memory > addresses via this way and then fetch/put data directly to memory. > Actually nearer to PC IO than to S/360etc IO. Interesting. So if the goal is to support a modern disk drive, an FPGA would have to capture reads and writes to the memory addresses used to control a disk drive, and from these derive the right signals to interface to an IDE and/or SCSI controller chip? I think I see why folks thought this might be a lot of work, but I'm a software guy, not a hardware guy. From what I can tell from the archives, the XKL TOAD-1 team went another way. They had their CPU output control signals to a general purpose bus, then they made boards that are attached to that bus to implement memory, disk and network subsystems. Then they modified the PDP-10 operating systems to include drivers for the modern I/O subsystems so they wouldn't have to emulate the original I/O subsystems in hardware and/or firmware. The software emulators just emulate the original I/O subsystems in software (with help from their underlying operating systems) so they don't need any modification to the PDP-10 operating systems. This emulation is fairly costly in terms of performance. I could see going half way between these approaches and designing a FPGA core to handle the CPU functionality that interfaces to an I/O coprocessor to handle the peripherals. This I/O coprocessor could be another FPGA or it could be a microprocessor running an embedded operating system. The I/O coprocessor could leverage the work that has already been done with regard to emulating the peripherals that were usually found with PDP-10 installations. I hope none of this discussion distracts you. It seems pretty clear to me that you are enjoying the process of designing an FPGA to emulate a PDP-10 CPU and are willing to defer the details of how to do the peripherals to a later point in time. So, keep up the good work, and let us know how it goes. Dave ###### From: "Madman" Newsgroups: alt.sys.pdp10,alt.sys.pdp8 References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> Subject: Re: Another DEC computer in an FPGA Lines: 17 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: <69hH7.11400$XJ4.7924437@news1.sttln1.wa.home.com> Date: Sat, 10 Nov 2001 21:40:18 GMT NNTP-Posting-Host: 65.4.170.57 X-Complaints-To: abuse@home.net X-Trace: news1.sttln1.wa.home.com 1005428418 65.4.170.57 (Sat, 10 Nov 2001 13:40:18 PST) NNTP-Posting-Date: Sat, 10 Nov 2001 13:40:18 PST Organization: Excite@Home - The Leader in Broadband http://home.com/faster Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!out.nntp.be!propagator-SanJose!in.nntp.be!news-in-sanjose!newshub2.rdc1.sfba.home.com!news.home.com!news1.sttln1.wa.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7477 wrote in message news:9sgd42$6kj$1@bob.news.rcn.net... [snip] > More importantly, you'ld have all sources for the system which > isn't true of anything from Misoft. Also, do not underestimate > their latest ploy of claiming ownership for anything running on > their software layer. Nope, that's a Linux trick - GPL and LGPL - for "claiming ownership of anything running on their software layer." Besides, I can just see THAT lawsuit: Microsoft "claiming ownership" of the PDP-n instruction set - get real.... -- Ian (running UNIX 6th Ed. on a PDP-11/34a, and heating my basement to boot!) ###### From: "David G. Conroy" Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <6usnbmfpk1.fsf@chonsp.franklin.ch> Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 15 Message-ID: Date: Sat, 10 Nov 2001 23:49:03 GMT NNTP-Posting-Host: 66.120.161.211 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1005436143 66.120.161.211 (Sat, 10 Nov 2001 23:49:03 GMT) NNTP-Posting-Date: Sat, 10 Nov 2001 23:49:03 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!newsfeed.media.kyoto-u.ac.jp!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7476 >> It seems to me that the best choice would be to create an interface that >> lets you plug in an interface for the drive of your choice. That way once >> SCSI and EIDE drives get hard to find, you can build and interface for >> whatever the current type drive is, and just plug it in. > > And that should be fairly easy, by simply putting both connectors on > the board, sharing the same FPGA pins, and then simply compiling in > one or the other device into the FPGA. Except that SCSI I/O cells need to be able to sink the current from 2 terminators (each of which is 220 ohms to 5 volts, or about 45 mA). The original SCSI drivers were big open-collector gates like the 7438. dgc ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 10 Nov 2001 23:58:27 GMT Organization: California Institute of Technology, Pasadena Lines: 62 Message-ID: <9skev3$fr4@gap.cco.caltech.edu> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> NNTP-Posting-Host: quetzal.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch alt.sys.pdp10:7469 Neil Franklin writes: >gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: >> Neil Franklin writes: >> >gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: >> >> >> >Why not implement them direct in the FPGA design? Gets rid of the host >> >> >system and gives an far better look&feel. >> >> >> >> Because it is a LOT of work. While processor registers work well >> >> in an FPGA, I/O calculations don't. >> >> >But only doing it in real hardware gives the true immediate down in >> >the guts hardware look and feel. >> >> >If you are going to do all IO in software to save work, then why not >> >get rid of the FPGA and do the processor also in software? Modern CPUs >> >can emulate up to early 1980s machines in real speed. See Simh and TS-10. >> >> This is a hard question. What are you going to do for the card reader >> or paper tape reader or punch? Half-inch tape or DECtape? Real >> or emulated? >As I have neither original drives (OK, TU-56 should be gettable due to >the many made for PDP-8) nor the mechanical abilities to make them, I >will be either doing entirely without (just console, tty, disk, net >IO) or would have to simulate them using RS232 lines or floppy drives. So I/O will be emulated. >> Now, one reason for the FPGA is to go faster than the >> software simulated processor, and in most cases host I/O will be fast >> enough for an FPGA processor. >One reason. My reasons are more exploration of FPGAs, fun in >programming, wanting to make an processor chip, getting a bit of that >old hardware feel of immediacity, etc. Of course having one fast >enough and with enough memory to try and use daily, and so get away >from todays crap architectures, is an far future aim. It would seem that just doing the processor and interfacing to host I/O would accomplish this. It also allows many debugging features that would be difficult to implement directly. >> How did the real processor do I/O? Is it all written in microcode, >> or is it done by external, programmable, boxes? (S/360/370/390 >> >> So, how did PDP-10 I/O really work? I was only ever at the terminal >> end of one. >AFAIK (I am only getting into them now, never used originals) a set of >8 IO instructions triggered 4 types of one-word data transmissions >over an IO device bus with max 128 device IDs. Doesn't sound so hard to do through host I/O. I suppose it is that I find processor design more interesting than I/O design. >Slower devices relied entirely on such transfers, sometimes triggered >by interrupts, faster devices only recieve commands ans memory >addresses via this way and then fetch/put data directly to memory. >Actually nearer to PC IO than to S/360etc IO. -- glen ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 11 Nov 2001 22:54:48 +0100 Organization: My own Private Self Lines: 146 Message-ID: <6uk7wxdlcn.fsf@chonsp.franklin.ch> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005515690 1236 10.0.3.2 (11 Nov 2001 21:54:50 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 11 Nov 2001 21:54:50 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7480 Dave Cherkus writes: > Neil Franklin wrote in > news:6uvggifpqq.fsf@chonsp.franklin.ch: > > > > AFAIK (I am only getting into them now, never used originals) a set of > > 8 IO instructions triggered 4 types of one-word data transmissions > > over an IO device bus with max 128 device IDs. > > > > Slower devices relied entirely on such transfers, sometimes triggered > > by interrupts, faster devices only recieve commands ans memory > > addresses via this way and then fetch/put data directly to memory. > > Actually nearer to PC IO than to S/360etc IO. > > Interesting. So if the goal is to support a modern disk drive, an > FPGA would have to capture reads and writes to the memory addresses > used to control a disk drive, Actually capture the IO instructions and then decode the 7 IO address bits. Perhaps I should put up some of the running/planned implementation details. CPU first "level" is the "central part" that fetches next instruction and then presents it to an group of 8 instruction units, togethe rwitn an "now act" signal. CPU second level is that each of these units on recieving "now act" checks the instruction bits 0-2 for their IDs 0-7 and if it is the right one "triggers", takes over the machine, does its job, and then passes control back to the central part for the next instruction. One of these units (7) is the IO unit. Both of these levels are already implementend. Central is running (but lacking the 16 word fast memory, will be next addition). Units: number 4 (SET* AND* XOR IOR EQV ORC*) is running, number 3 (CAI* CAM* JUMP* SKIP* AO* SO*) is in testing, waiting for me to resole an debugger bug with its manufacturer), rest still to do, next after fast memory will be numbers 6 (T*) and 5 (H*). IO unit (unit 7) third level will be to take bits 10-12 (type of IO operation) and derive type of bus access (control out, status in, data out, data in) and take bits 3-9 (device ID and present them to an group of up to 128 IO devices, together with an second "now act". IO device fourth level will be on recieving "now act" to check bits 3-9 for their IDs 0-127 and if it is the right one "trigger", take over machine (with help of IO unit for common stuff) and do their per-word job and then return control to IO unit, which returns it to central. BLK* will lead to multiple "new act"s being issued. > and from these derive the right signals > to interface to an IDE and/or SCSI controller chip? IO hardware fith level will be an actual HD that recieves from HD IO device the neccessary commands (via IDE or SCSI) that it needs to fullfill what the IO device wants). Presently I am more likely to use IDE, because it seem to me more similar to Massbus (not investigated this deeply though). Parallel to this, for the actual data transfer, the IO device will also have an DMA section that, when the HD is ready, transfers data to/from its bus, from/to the PDP-10s memory. For this it will have to use an not yet implemented "stall processor and take over the memory" mechanism. No different from the AT bus busmaster or PCI bus DMA cycles. > I think I see > why folks thought this might be a lot of work, but I'm a software > guy, not a hardware guy. I have so far done education/work as mechanics designer/draftsman, electrical engineer, assembler and high level programmer, sysadmin. Good mixed background for this sort of stuff. And yes it is a lot of work. But satisfying work. So long one if not fighting tool bugs. > From what I can tell from the archives, the XKL TOAD-1 team went > another way. They had their CPU output control signals to a > general purpose bus, then they made boards that are attached to > that bus to implement memory, disk and network subsystems. Then > they modified the PDP-10 operating systems to include drivers for > the modern I/O subsystems so they wouldn't have to emulate the > original I/O subsystems in hardware and/or firmware. Also a way to do it. I want to copy our emulator writers Tim, Bob and Ken and be able to run unchanged original OS images. At least initially, adding features not existant before 1985 (such as bitmapped graphics display, windowed display) will require extensions. > The software emulators just emulate the original I/O subsystems > in software (with help from their underlying operating systems) > so they don't need any modification to the PDP-10 operating > systems. Because they convert operations to the new hardware. > This emulation is fairly costly in terms of performance. Because they are software. Try hardware for this :-). > I could see going half way between these approaches and designing a > FPGA core to handle the CPU functionality that interfaces to an > I/O coprocessor to handle the peripherals. Then the conversion is again in software. Slow. > This I/O coprocessor > could be another FPGA So make the CPU FPGA big enough and put it all inside. Saves pins (and they are the limiting thing, getting signals out of ones chip, I only have 140 data pins, logic space I have to burn, 84*56 elements). > I hope none of this discussion distracts you. It seems pretty > clear to me that you are enjoying the process of designing an > FPGA to emulate a PDP-10 CPU Yes! > and are willing to defer the details > of how to do the peripherals to a later point in time. The basic design is done. "Just" the large big job of implementing to do. And implementing HD access will be heavy. > up the good work, and let us know how it goes. Constantly, online, the day to day working: http://neil.franklin.ch/Projects/PDP-10/Logfile -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 11 Nov 2001 23:05:00 +0100 Organization: My own Private Self Lines: 46 Message-ID: <6uhes1dkvn.fsf@chonsp.franklin.ch> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <9skev3$fr4@gap.cco.caltech.edu> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005516301 1236 10.0.3.2 (11 Nov 2001 22:05:01 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 11 Nov 2001 22:05:01 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7481 gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > Neil Franklin writes: > >gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > >> > >> This is a hard question. What are you going to do for the card reader > >> or paper tape reader or punch? Half-inch tape or DECtape? Real > >> or emulated? > > >As I have neither original drives (OK, TU-56 should be gettable due to > >the many made for PDP-8) nor the mechanical abilities to make them, I > >will be either doing entirely without (just console, tty, disk, net > >IO) or would have to simulate them using RS232 lines or floppy drives. > > So I/O will be emulated. Or limited to those devices I have. Make-myself operators console from switches and LEDs, RS232 for console tty with VT100 (I have an original one), emulated console tty using PC keyboard and VGA monitor, user ttys using same 2 options, disk drive using IDE or SCSI HD, ethernet network. > It would seem that just doing the processor and interfacing to > host I/O would accomplish this. It also allows many debugging > features that would be difficult to implement directly. The debugging features for FPGAs are astonishing. Think of operators console plus all them indicator panels plus clock single/multi stepping. FPGA chip viewer offers roughly equivalent. > >AFAIK (I am only getting into them now, never used originals) a set of > >8 IO instructions triggered 4 types of one-word data transmissions > >over an IO device bus with max 128 device IDs. > > Doesn't sound so hard to do through host I/O. I suppose it is that > I find processor design more interesting than I/O design. I find both interesting, so I want to have a go at both. :-) -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: berdpee@ami.com.au Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: Sun, 11 Nov 2001 21:46:45 GMT Message-ID: <3beef140.3461363@news.ami.com.au> References: <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehdt$c6r$1@shell.golden.net> <9sfml7$eoq$1@shell.golden.net> <6upu6qfpdb.fsf@chonsp.franklin.ch> X-Newsreader: Forte Free Agent 1.21/32.243 NNTP-Posting-Host: comsrvr.ami.com.au X-Trace: 12 Nov 2001 05:43:01 +0800, comsrvr.ami.com.au Lines: 47 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.uncensored-news.com!propagator!feed2.newsfeeds.com!newsfeeds.com!newsfeed.iinet.net.au!nntp.waia.asn.au!usenet.per.paradox.net.au!comsrvr.ami.com.au Xref: chonsp.franklin.ch alt.sys.pdp10:7487 We still have an original PDP-6 front panel here in West Aust. But that is all that is left of our mainframe. On 10 Nov 2001 19:32:48 +0100, Neil Franklin wrote: >jrlatala@shell.golden.net writes: > >> In article , >> Todd Enders wrote: >> >In <9sehdt$c6r$1@shell.golden.net> jrlatala@shell.golden.net wrote: >> >> If you end up sticking this all onto a board that plugs into a bus then >> >> how about making a soft front panel? You could use X-Windows to draw a >> >> >> > A soft front panel would be OK, if one must, but *I* personally prefer the >> >tactile experience >> >of manipulating real switches, and watching real blinkin' lights. :-) >> >> True but if the choice is between a soft front panel and no panel then >> I'll take the soft panel. > >But making an (optinal) hardware pannel is not a big problem. Take an >normal 2.54mm raster board, put in LEDs and switches. Wire in some >de-muxers to drive it. Connect to a few lines of the FPGA. > > >> The nice thing about the soft panel is that it >> won't break, doesn't need maintenance > >With LEDs (and yes there exist white ones today) and modern switches >they should not break any more often than an keyboard does. > > >> and (most of all) doesn't take up >> any space. How much physical room would you need for the front panels of >> half a dozen of the early PDPs? > >Make an single universal pannel and ignore the exxess LEDs and switches. >Not optimal but space saving. > > >-- >Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ >Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer >- Intellectual Property is Intellectual Robbery aeolus ###### From: Rich Alderson Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 12 Nov 2001 22:15:24 -0500 Organization: Systems Administration, XKL LLC, Redmond WA 98052 Lines: 19 Sender: alderson+news@panix1.panix.com Message-ID: References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> NNTP-Posting-Host: panix1.panix.com X-Trace: news.panix.com 1005621328 20059 166.84.1.1 (13 Nov 2001 03:15:28 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: 13 Nov 2001 03:15:28 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed00.sul.t-online.de!t-online.de!diablo.theplanet.net!btnet-peer!btnet-peer0!btnet!newsfeed.mathworks.com!panix!news.panix.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7532 Dave Cherkus writes: > From what I can tell from the archives, the XKL TOAD-1 team went another way. > They had their CPU output control signals to a general purpose bus, then they > made boards that are attached to that bus to implement memory, disk and > network subsystems. Then they modified the PDP-10 operating systems to > include drivers for the modern I/O subsystems so they wouldn't have to > emulate the original I/O subsystems in hardware and/or firmware. Right. After all, the goal was not to produce simply a clone of the KL-10E, but a follow-on system that used modern peripherals, allowed the full use of the extended memory model, and so on. A future single-chip CPU would probably end up on a board with Adaptec and 3Com chips, were one to speculate. -- Rich Alderson alderson+news@panix.com "You get what anybody gets. You get a lifetime." --Death, of the Endless ###### From: Rich Alderson Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 12 Nov 2001 22:17:33 -0500 Organization: Systems Administration, XKL LLC, Redmond WA 98052 Lines: 22 Sender: alderson+news@panix1.panix.com Message-ID: References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> NNTP-Posting-Host: panix1.panix.com X-Trace: news.panix.com 1005621454 20059 166.84.1.1 (13 Nov 2001 03:17:34 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: 13 Nov 2001 03:17:34 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.icl.net!newsfeed1.cidera.com!Cidera!cyclone1.gnilink.net!washdc3-snf1!washdc3-snh1.gtei.net!nycmny1-snh1.gtei.net!news.gtei.net!panix!news.panix.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7535 Neil Franklin writes: > Dave Cherkus writes: >> From what I can tell from the archives, the XKL TOAD-1 team went another >> way. They had their CPU output control signals to a general purpose bus, >> then they made boards that are attached to that bus to implement memory, >> disk and network subsystems. Then they modified the PDP-10 operating >> systems to include drivers for the modern I/O subsystems so they wouldn't >> have to emulate the original I/O subsystems in hardware and/or firmware. > Also a way to do it. I want to copy our emulator writers Tim, Bob and Ken and > be able to run unchanged original OS images. At least initially, adding > features not existant before 1985 (such as bitmapped graphics display, > windowed display) will require extensions. Yes, but all of these are intended to provide a nostalgic look at the past. The purpose of CPU design at XKL is to provide a viable path to the future. -- Rich Alderson alderson+news@panix.com "You get what anybody gets. You get a lifetime." --Death, of the Endless ###### From: "David G. Conroy" Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 13 Message-ID: Date: Tue, 13 Nov 2001 04:27:06 GMT NNTP-Posting-Host: 66.120.160.44 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1005625626 66.120.160.44 (Tue, 13 Nov 2001 04:27:06 GMT) NNTP-Posting-Date: Tue, 13 Nov 2001 04:27:06 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!HSNX.atgi.net!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7562 When I built my FPGA versions of the PDP-8 and PDP-4 I used modern I/O components, designed and implemented programming interfaces appropriate to the modern components (with some exceptions, like the PDP-8 console, where the non-destructive read is fairly fundamental), and fixed the software. I never felt the slightest bit guilty about doing this, since building devices and teaching system software about them was very much a part of the culture surrounding these machines. And besides, there are fair number of (generally more modern) DEC I/O devices which I simply don't have a strong enough stomach to clone. ###### From: Ben Franchuk Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: Mon, 12 Nov 2001 22:07:57 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3BF0AAAD.EE4AD335@jetnet.ab.ca> X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 38 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feeder.qis.net!sn-xit-02!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7505 "David G. Conroy" wrote: > > When I built my FPGA versions of the PDP-8 and PDP-4 > I used modern I/O components, designed and implemented programming > interfaces appropriate to the modern components (with some > exceptions, like the PDP-8 console, where the non-destructive read is > fairly fundamental), and fixed the software. > > I never felt the slightest bit guilty about doing this, > since building devices and teaching system software about them was > very much a part of the culture surrounding these machines. > > And besides, there are fair number of (generally > more modern) DEC I/O devices which I simply don't have a strong > enough stomach to clone. Perhaps it is time to design a Generic Open Source PDP-n mother board. Well maybe two boards - 12 bits and 36/32/16/8 bits to cover DEC'S entire line of CPU's . This could be small mother board with just i/o expansion slots. Sigh what ever happened to nice easy to repair 2 sided mother boards. While most users would want a modern design a "old bus" interface card may be useful for people with old I/O the have but don't have or wish to power up the whole machine. Doing a modern machine may be hard because chips seem to have a Halflife of 6 months or so, and I expect people still would like to have a PDP-N cpu 50 or 60 years from now. Ben Franchuk. PS. Altera FPGA's may have a advantage of Xilinx if dual port ram is not needed, in that it has a good TTL macro library and block ram can be loaded from the config rom (ie micro rom). -- Live "Pre-historic Cpu's" -- and you thought they were extinct. www.jetnet.ab.ca/users/bfranchuk/index.html ###### Reply-To: "Douglas H. Quebbeman" From: "Douglas H. Quebbeman" Newsgroups: alt.sys.pdp10,alt.sys.pdp8 References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> Subject: Re: Another DEC computer in an FPGA Date: Tue, 13 Nov 2001 09:02:52 -0500 Lines: 23 Organization: Full Circle Systems X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 NNTP-Posting-Host: 204.250.0.238 X-Original-NNTP-Posting-Host: 204.250.0.238 Message-ID: <3bf12821_2@news.iglou.com> X-Trace: news.iglou.com 1005660193 204.250.0.238 (13 Nov 2001 09:03:13 -0500) X-Authenticated-User: dougq X-Original-NNTP-Posting-Host: 204.250.0.238 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!newsfeed1.cidera.com!Cidera!portc01.blue.aol.com!wn3feed!worldnet.att.net!198.6.0.8!uunet!ash.uu.net!news.iglou.com Xref: chonsp.franklin.ch alt.sys.pdp10:7499 "Rich Alderson" wrote in message > > > Also a way to do it. I want to copy our emulator writers Tim, Bob and Ken and > > be able to run unchanged original OS images. At least initially, adding > > features not existant before 1985 (such as bitmapped graphics display, > > windowed display) will require extensions. > > Yes, but all of these are intended to provide a nostalgic look at the past. > The purpose of CPU design at XKL is to provide a viable path to the future. Wow... does this include OS-development? -dq -- Surgically Excise the Pig-Latin from my e-mail address in order to reply... No Tourbots ###### Sender: Superuser From: nospam93@parse.com Subject: Re: Another DEC computer in an FPGA Newsgroups: alt.sys.pdp10,alt.sys.pdp8 References: <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> <3BF0AAAD.EE4AD335@jetnet.ab.ca> User-Agent: tin/1.4.5-20010409 ("One More Nightmare") (UNIX) (QNX/6.1.0 (x86pc)) Lines: 38 Message-ID: Date: Tue, 13 Nov 2001 14:22:05 GMT NNTP-Posting-Host: 24.112.170.9 X-Complaints-To: abuse@home.net X-Trace: news4.rdc1.on.home.com 1005661325 24.112.170.9 (Tue, 13 Nov 2001 06:22:05 PST) NNTP-Posting-Date: Tue, 13 Nov 2001 06:22:05 PST Organization: Excite@Home - The Leader in Broadband http://home.com/faster Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news4.rdc1.on.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7564 In alt.sys.pdp8 Ben Franchuk wrote: > "David G. Conroy" wrote: >> >> When I built my FPGA versions of the PDP-8 and PDP-4 >> I used modern I/O components, designed and implemented programming >> interfaces appropriate to the modern components (with some >> exceptions, like the PDP-8 console, where the non-destructive read is >> fairly fundamental), and fixed the software. >> >> I never felt the slightest bit guilty about doing this, >> since building devices and teaching system software about them was >> very much a part of the culture surrounding these machines. >> >> And besides, there are fair number of (generally >> more modern) DEC I/O devices which I simply don't have a strong >> enough stomach to clone. > Perhaps it is time to design a Generic Open Source PDP-n mother board. > Well maybe two boards - 12 bits and 36/32/16/8 bits to cover > DEC'S entire line of CPU's . This could be small > mother board with just i/o expansion slots. Sigh what ever happened to > nice > easy to repair 2 sided mother boards. While most users would want a > modern design a "old bus" interface card may be useful for people > with old I/O the have but don't have or wish to power up the whole > machine. I was actually considering making an "all-in-wonder" universal PDP-8/E peripheral, that would have memory expansion (battery-backed SRAM), a hard disk (EIDE or SRAM), serial ports, ... everything, all on one card. But then, the cost of manufacturing... :-) Cheers, -RK -- Robert Krten, PARSE Software Devices +1 613 599 8316. Realtime Systems Architecture, Consulting and Training at www.parse.com Email my initials at parse dot com. ###### From: Ben Franchuk Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: Tue, 13 Nov 2001 09:58:21 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3BF1512D.DC90E9F0@jetnet.ab.ca> X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 References: <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> <3BF0AAAD.EE4AD335@jetnet.ab.ca> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 13 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.stanford.edu!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7502 nospam93@parse.com wrote: > I was actually considering making an "all-in-wonder" universal PDP-8/E > peripheral, that would have memory expansion (battery-backed SRAM), > a hard disk (EIDE or SRAM), serial ports, ... everything, all on one > card. But then, the cost of manufacturing... :-) Thats true -- 6 inch square CPU card (stuffed) $200 US ... Huge rack with front panel $800 US. Ben Franchuk. -- Live "Pre-historic Cpu's" -- and you thought they were extinct. www.jetnet.ab.ca/users/bfranchuk/index.html ###### From: Rich Alderson Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 13 Nov 2001 12:47:01 -0500 Organization: Systems Administration, XKL LLC, Redmond WA 98052 Lines: 15 Sender: alderson+news@panix1.panix.com Message-ID: References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> <3bf12821_2@news.iglou.com> NNTP-Posting-Host: panix1.panix.com X-Trace: news.panix.com 1005673624 3590 166.84.1.1 (13 Nov 2001 17:47:04 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: 13 Nov 2001 17:47:04 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.bme.hu!andromeda.datanet.hu!newsfeed.gamma.ru!Gamma.RU!nycmny1-snh1.gtei.net!news.gtei.net!panix!news.panix.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7537 "Douglas H. Quebbeman" writes: > "Rich Alderson" wrote in message >> The purpose of CPU design at XKL is to provide a viable path to the future. > Wow... does this include OS-development? -dq Of course. For example, the XKL version of Tops-20 supports the entire 30-bit address space (as opposed to the 23-bit address space of the extended KL), and SCSI peripherals. -- Rich Alderson alderson+news@panix.com "You get what anybody gets. You get a lifetime." --Death, of the Endless ###### From: Ben Franchuk Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: Tue, 13 Nov 2001 10:59:52 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3BF15F98.82844A01@jetnet.ab.ca> X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> <3bf12821_2@news.iglou.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 12 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!isdnet!sn-xit-02!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7500 Rich Alderson wrote: > Of course. For example, the XKL version of Tops-20 supports the entire 30-bit > address space (as opposed to the 23-bit address space of the extended KL), and > SCSI peripherals. Not knowing the details of the many PDP-10 memory management units, can the address space be hacked again to 36 bits of address space and are you limited to 256KW segments? Ben Franchuk. -- Live "Pre-historic Cpu's" -- and you thought they were extinct. www.jetnet.ab.ca/users/bfranchuk/index.html ###### From: Ben Franchuk Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: Tue, 13 Nov 2001 12:01:08 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3BF16DF4.DB850DA5@jetnet.ab.ca> X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> <3BF0AAAD.EE4AD335@jetnet.ab.ca> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 22 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.stanford.edu!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7503 Eric Smith wrote: > > Ben Franchuk writes: > > PS. Altera FPGA's may have a advantage of Xilinx if dual port ram is not > > needed, in that it has a good TTL macro library and block ram can be > > loaded > > from the config rom (ie micro rom). > > Xilinx parts also can load block RAM from the config ROM. > > I don't know whether Xilinx has good TTL macros, but I really don't care > as I much prefer HDL over schematic entry. Yes, I know that this is > a personal preference, and I don't want to start a discussion about it. > People who like schematic entry should use it, and I'm not going to try > to dissuade them. They're not likely to change my preference either. No I was thinking of TTL macros in the case you need to copy a schematic for some purpose, say debugging a new version compared to a old version, or just historical study. Ben Franchuk. -- Live "Pre-historic Cpu's" -- and you thought they were extinct. www.jetnet.ab.ca/users/bfranchuk/index.html ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> <3BF0AAAD.EE4AD335@jetnet.ab.ca> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 13 Nov 2001 11:48:51 -0800 Message-ID: Lines: 13 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 13 Nov 2001 11:49:21 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.bme.hu!andromeda.datanet.hu!newsfeed.gamma.ru!Gamma.RU!news-peer-west.sprintlink.net!news.sprintlink.net!enews.sgi.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch alt.sys.pdp10:7553 Ben Franchuk writes: > PS. Altera FPGA's may have a advantage of Xilinx if dual port ram is not > needed, in that it has a good TTL macro library and block ram can be > loaded > from the config rom (ie micro rom). Xilinx parts also can load block RAM from the config ROM. I don't know whether Xilinx has good TTL macros, but I really don't care as I much prefer HDL over schematic entry. Yes, I know that this is a personal preference, and I don't want to start a discussion about it. People who like schematic entry should use it, and I'm not going to try to dissuade them. They're not likely to change my preference either. ###### From: Rich Alderson Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 13 Nov 2001 17:40:40 -0500 Organization: Systems Administration, XKL LLC, Redmond WA 98052 Lines: 25 Sender: alderson+news@panix2.panix.com Message-ID: References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> <3bf12821_2@news.iglou.com> <3BF15F98.82844A01@jetnet.ab.ca> NNTP-Posting-Host: panix2.panix.com X-Trace: news.panix.com 1005691241 9544 166.84.1.2 (13 Nov 2001 22:40:41 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: 13 Nov 2001 22:40:41 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.mathworks.com!panix!news.panix.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7534 Ben Franchuk writes: > Rich Alderson wrote: >> Of course. For example, the XKL version of Tops-20 supports the entire >> 30-bit address space (as opposed to the 23-bit address space of the extended >> KL), and SCSI peripherals. > Not knowing the details of the many PDP-10 memory management units, can the > address space be hacked again to 36 bits of address space and are you limited > to 256KW segments? As currently constituted, the address space is limited to 30 bits: Bits 0:5 of the word are used for other purposes in the addressing hardware. Segmentation only affects program execution (increment a PC of ,,777777 and you will get ,,0, not ,,0); data access crosses segment boundaries (increment an index register containing ,,777777 and you get ,,0). It is certainly conceivable that the architecture could be changed to allow more than 30 bits of addressing, but that would require a much larger effort in that *every* program ever used would have to be re-compiled. -- Rich Alderson alderson+news@panix.com "You get what anybody gets. You get a lifetime." --Death, of the Endless ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 15 Nov 2001 00:03:31 +0100 Organization: My own Private Self Lines: 76 Message-ID: <6ubsi5dkfw.fsf@chonsp.franklin.ch> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> <3BF0AAAD.EE4AD335@jetnet.ab.ca> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005779013 1425 10.0.3.2 (14 Nov 2001 23:03:33 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 14 Nov 2001 23:03:33 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7589 Ben Franchuk writes: > "David G. Conroy" wrote: > > > > When I built my FPGA versions of the PDP-8 and PDP-4 > > I used modern I/O components, designed and implemented programming > > interfaces appropriate to the modern components (with some > > > > I never felt the slightest bit guilty about doing this, > > since building devices and teaching system software about them was > > very much a part of the culture surrounding these machines. That is also true. Perhaps I will have to reconsider this. > Perhaps it is time to design a Generic Open Source PDP-n mother board. > Well maybe two boards - 12 bits and 36/32/16/8 bits to cover If you want two boards, then better: narrow/small (12/16/18) and wide/large (32/36). For the first you can use Davids now done 18bit PDP-4/X board. His PDP-8/X will surely port to it (wasting 6 data bits, address range is identical for both, 2*32kword). For the later either use the same board with dual memory accesses (and halfed amount of memory words), or make an big board, with lots of DRAM memory (so 1 to 16 MWord). That is what my hardware ideas file[1] is specifying. [1] http://neil.franklin.ch/Projects/PDP-10/Hardware > DEC'S entire line of CPU's . This could be small > mother board with just i/o expansion slots. Or directly put in the usual interface ports (key/video for terminal clone, RS232 for real terminal or comms, disk interface), and then some slot for facultative expansion. Format just like an all-in-one PC Motherboard, fit in PC case, use PC peripherals and power supply. That will make manufacturing the cheapest. > Sigh what ever happened to nice > easy to repair 2 sided mother boards. Too many signals, that needed more space than boards had surface. Did you notice that the largest FPGAs are now at >1100 pins (erm balls, as they are BGA packages). And providing power and ground as separate full-surface planes. Wire impedance kills reliability at 100s of MHz, OK even at 10s it starts being bad. > Doing a modern machine may be hard because chips seem to have a Halflife > of 6 months or so, and I expect people still would like to have > a PDP-N cpu 50 or 60 years from now. Well FPGAs seem to have an EOL at about 10 years, presently. > PS. Altera FPGA's may have a advantage of Xilinx if dual port ram is not > needed, in that it has a good TTL macro library and block ram can be > loaded > from the config rom (ie micro rom). Xilinx also habe BRAM these days, but in both of them it is too small for microcode. At least for an large (KL-10 or VAX) machine. And the small ones had no microcode. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: "David G. Conroy" Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <9sf55t$btk@gap.cco.caltech.edu> <6uvggifpqq.fsf@chonsp.franklin.ch> <6uk7wxdlcn.fsf@chonsp.franklin.ch> <3BF0AAAD.EE4AD335@jetnet.ab.ca> <6ubsi5dkfw.fsf@chonsp.franklin.ch> Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 23 Message-ID: Date: Thu, 15 Nov 2001 05:20:49 GMT NNTP-Posting-Host: 66.120.160.44 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1005801649 66.120.160.44 (Thu, 15 Nov 2001 05:20:49 GMT) NNTP-Posting-Date: Thu, 15 Nov 2001 05:20:49 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!nntp-relay.ihug.net!ihug.co.nz!newsfeed.media.kyoto-u.ac.jp!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7625 In article <6ubsi5dkfw.fsf@chonsp.franklin.ch>, Neil Franklin wrote: > For the first you can use Davids now done 18bit PDP-4/X board. His > PDP-8/X will surely port to it (wasting 6 data bits, address range is > identical for both, 2*32kword). I think it could. You need an extra wire between the I/O chip and the CPU chip to tell the CPU it needs to clear the accumulator on an I/O instruction (on the 4 this is done by a bit in the opcode) but the 8 doesn't need the REQ/ACK used by the clock, so there are a pair of signals to steal. > Too many signals, that needed more space than boards had surface. Did > you notice that the largest FPGAs are now at >1100 pins (erm balls, as > they are BGA packages). > And providing power and ground as separate full-surface planes. Wire > impedance kills reliability at 100s of MHz, OK even at 10s it starts > being bad. Two-layer boards are still alive and well, and even in systems which contain BGA devices with hundreds of pins. Look inside a low-end satellite and/or digital cable settop box. But the chips used in these boxes have pinouts which are the result of a lot of work involving the chip designer and the pcb designer. ###### From: Ben Franchuk Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA Date: Sun, 18 Nov 2001 04:52:05 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3BF7A0E5.BF09A73B@jetnet.ab.ca> X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 21 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feeder.qis.net!sn-xit-02!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7697 SkyWriter wrote: > then you want to netlist, dont you? i've seen more mangled > netlists from schematic capture process than logic synthesis. > could be operator error though (i didn't do the schematics, heh). To tell you the truth I can't easily get at the netlist (Altera). Note even with schematic entry you still have options on how to synthesize and/or pack your netlist. > > HDL's are not portable since features to make full use of FPGA's > > are not portable in my view. > > I would rather do an ASIC anyday. Feel free to do any of my Cpu designs in a ASIC. Dawn II fits nicely in a 40 pin dip. :) Ben Franchuk. -- Live "Pre-historic Cpu's" -- and you thought they were extinct. www.jetnet.ab.ca/users/bfranchuk/index.html ###### Message-ID: <3BF88520.58CE9075@mrnutty.com> From: SkyWriter Organization: NUTTY INDUSTRIES X-Mailer: Mozilla 4.78C-SGI [en] (X11; I; IRIX 6.5 IP32) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: zaphod!unknown@5300-238.024.popsite.net X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Lines: 22 Date: Sun, 18 Nov 2001 20:05:53 -0800 NNTP-Posting-Host: 199.224.11.10 X-Complaints-To: abuse@verio.net X-Trace: iad-read.news.verio.net 1006131548 199.224.11.10 (Mon, 19 Nov 2001 00:59:08 GMT) NNTP-Posting-Date: Mon, 19 Nov 2001 00:59:08 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!t-online.de!newsfeed.media.kyoto-u.ac.jp!sjc-peer.news.verio.net!news.verio.net!iad-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7696 Ben Franchuk wrote: > > At risk at starting a war, schematic entry if done right is best. > I like to see what I got, not after some program mangles my data. then you want to netlist, dont you? i've seen more mangled netlists from schematic capture process than logic synthesis. could be operator error though (i didn't do the schematics, heh). > > HDL's are not portable since features to make full use of FPGA's > are not portable in my view. I would rather do an ASIC anyday. > > Ben Franchuk. > -- > Live "Pre-historic Cpu's" -- and you thought they were extinct. > www.jetnet.ab.ca/users/bfranchuk/index.html ###### Message-ID: <3BFB0B84.50346BCB@mrnutty.com> From: SkyWriter Organization: NUTTY INDUSTRIES X-Mailer: Mozilla 4.78C-SGI [en] (X11; I; IRIX 6.5 IP32) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: zaphod!unknown@5300-238.024.popsite.net X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Lines: 35 Date: Tue, 20 Nov 2001 18:03:48 -0800 NNTP-Posting-Host: 199.224.11.10 X-Complaints-To: abuse@verio.net X-Trace: iad-read.news.verio.net 1006296896 199.224.11.10 (Tue, 20 Nov 2001 22:54:56 GMT) NNTP-Posting-Date: Tue, 20 Nov 2001 22:54:56 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed.nextra.ch!news.nextra.ch!nextra.at!newsfeed4.cidera.com!newsfeed1.cidera.com!Cidera!cpk-news-hub1.bbnplanet.com!nycmny1-snh1.gtei.net!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!cyclone.swbell.net!easynews!sjc-peer.news.verio.net!news.verio.net!iad-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7730 Ben Franchuk wrote: > SkyWriter wrote: > > > then you want to netlist, dont you? i've seen more mangled > > netlists from schematic capture process than logic synthesis. > > could be operator error though (i didn't do the schematics, heh). > > To tell you the truth I can't easily get at the netlist (Altera). Even if you did, you never _really_ know what's going on inside FPGAs. Even with Xilinx cute editing tool only gives you a abstract representation of what your design maps into. > > Note even with schematic entry you still have options on how to > synthesize and/or pack your netlist. > > > > HDL's are not portable since features to make full use of FPGA's > > > are not portable in my view. > > > > I would rather do an ASIC anyday. > > Feel free to do any of my Cpu designs in a ASIC. Dawn II fits nicely > in a 40 pin dip. :) No thanks, my own designs are keeping me busy enough :-) > > Ben Franchuk. > -- > Live "Pre-historic Cpu's" -- and you thought they were extinct. > www.jetnet.ab.ca/users/bfranchuk/index.html ###### From: "David G. Conroy" Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 12 Message-ID: Date: Wed, 21 Nov 2001 05:05:27 GMT NNTP-Posting-Host: 66.120.163.218 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1006319127 66.120.163.218 (Wed, 21 Nov 2001 05:05:27 GMT) NNTP-Posting-Date: Wed, 21 Nov 2001 05:05:27 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed.nextra.ch!news.nextra.ch!nextra.at!newsfeed4.cidera.com!newsfeed1.cidera.com!Cidera!newsfeed.media.kyoto-u.ac.jp!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7744 > Even if you did, you never _really_ know what's going on inside > FPGAs. Even with Xilinx cute editing tool only gives you a > abstract representation of what your design maps into. It's actually quite close, and with some study, you can learn what it doesn't tell you, like the exact locations of things like the long-line repeaters. At the DEC labs we designed for XC4010E devices more-or-less at the CLB level (yes, we hand packed and hand placed every CLB in the design), and our understanding was good enough that we would routinely build designs that were so dense and so fast that the xilinx guys started to worry about things like "do we have enough power contacts". ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA Date: 21 Nov 2001 22:22:54 +0100 Organization: My own Private Self Lines: 46 Message-ID: <6uelmr2501.fsf@chonsp.franklin.ch> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1006377774 689 10.0.3.2 (21 Nov 2001 21:22:54 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 21 Nov 2001 21:22:54 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7747 "David G. Conroy" writes: > > Even if you did, you never _really_ know what's going on inside > > FPGAs. Even with Xilinx cute editing tool only gives you a > > abstract representation of what your design maps into. > > It's actually quite close, and with some study, you can learn > what it doesn't tell you, Yup. Reading the data sheets between the lines gives quite a bit of into. Add other low-level docs in the application notes series and the low level tool sets and you can get a _very_ good idea what they are doing. 2 of my reconstructions (for Virtex): http://neil.franklin.ch/Projects/PDP-10/Virtex-CLB-PIPs (partial, misses long and hex lines) layout of routing in an CLB http://neil.franklin.ch/Projects/VirtexView/vv.c documented control bits layout in CLB, in an just started viewer tool project (scroll down to the line starting with: /* CLB layout of the LUT ) > long-line repeaters. At the DEC labs we designed for XC4010E > devices more-or-less at the CLB level (yes, we hand packed and hand > placed every CLB in the design), That is how I am doing my PDP-10. Using Xilinxes JBits tool to then flip the bits driven from Java code. I a lot of work. But gives ultimate performance. And I prefer the low level "mechanic" approach to using semi-high level languages "descriptive" approach. > good enough that we would routinely build designs that were so dense > and so fast that the xilinx guys started to worry about things > like "do we have enough power contacts". Hmmmm. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Message-ID: <3BFC7282.4557835A@mrnutty.com> From: SkyWriter Organization: NUTTY INDUSTRIES X-Mailer: Mozilla 4.78C-SGI [en] (X11; I; IRIX 6.5 IP32) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: zaphod!unknown@5300-238.024.popsite.net X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Lines: 24 Date: Wed, 21 Nov 2001 19:35:31 -0800 NNTP-Posting-Host: 199.224.11.10 X-Complaints-To: abuse@verio.net X-Trace: iad-read.news.verio.net 1006388760 199.224.11.10 (Thu, 22 Nov 2001 00:26:00 GMT) NNTP-Posting-Date: Thu, 22 Nov 2001 00:26:00 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed.nextra.ch!news.nextra.ch!nextra.at!newsfeed4.cidera.com!newsfeed1.cidera.com!Cidera!portc03.blue.aol.com!news.maxwell.syr.edu!newsfeed.frii.net!easynews!sjc-peer.news.verio.net!news.verio.net!iad-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7751 "David G. Conroy" wrote: > > Even if you did, you never _really_ know what's going on inside > > FPGAs. Even with Xilinx cute editing tool only gives you a > > abstract representation of what your design maps into. > > It's actually quite close, and with some study, you can learn > what it doesn't tell you, like the exact locations of things like the > long-line repeaters. Weren't there a plethora of 'redundant resources' to aid in wafer yields? could you see those in the tools too? > At the DEC labs we designed for XC4010E > devices more-or-less at the CLB level (yes, we hand packed and hand > placed every CLB in the design), and our understanding was > good enough that we would routinely build designs that were so dense > and so fast that the xilinx guys started to worry about things > like "do we have enough power contacts". In my experience, if you got them worried, you were already in trouble. YMMV (with luck). ###### From: "David G. Conroy" Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 21 Message-ID: Date: Thu, 22 Nov 2001 05:14:27 GMT NNTP-Posting-Host: 66.123.169.148 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1006406067 66.123.169.148 (Thu, 22 Nov 2001 05:14:27 GMT) NNTP-Posting-Date: Thu, 22 Nov 2001 05:14:27 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!newsfeed1.cidera.com!Cidera!easynews!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7769 In article <3BFC7282.4557835A@mrnutty.com>, SkyWriter wrote: > Weren't there a plethora of 'redundant resources' to aid in > wafer yields? could you see those in the tools too? The tools only show resources you can actually use, so I would not expect to see redundant resources, if they happened to exist. I don't know if they actually do exist, although I remember admiring the layout in one of the older devices (a 3090, if I remember correctly) and it seemed to look more-or-less as described. > In my experience, if you got them worried, you were already > in trouble. YMMV (with luck). The part that sticks in my mind was a slice of a crossbar chip, built in a 3090A. The design was symmetric, and the designer lavished care on one tile, and then replicated the tile throughout the device. It used all the pins, all the CLBS, all the TBUFS, all the long lines, all the direct interconnect, an a good chunk of the crappy interconnect, and it was pipelined, so it ran fast. At the time it was the highest utilization design they had ever seen, and it may still be. ###### Message-ID: <3BFD3EBF.62DBDB54@mrnutty.com> From: SkyWriter Organization: NUTTY INDUSTRIES X-Mailer: Mozilla 4.78C-SGI [en] (X11; I; IRIX 6.5 IP32) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: zaphod!unknown@5300-238.024.popsite.net X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Lines: 27 Date: Thu, 22 Nov 2001 10:06:56 -0800 NNTP-Posting-Host: 199.224.11.10 X-Complaints-To: abuse@verio.net X-Trace: iad-read.news.verio.net 1006441009 199.224.11.10 (Thu, 22 Nov 2001 14:56:49 GMT) NNTP-Posting-Date: Thu, 22 Nov 2001 14:56:49 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed.nextra.ch!news.nextra.ch!newsfeed1.ulv.nextra.no!nextra.com!news.tele.dk!small.news.tele.dk!193.251.151.101!opentransit.net!newsfeed.media.kyoto-u.ac.jp!sjc-peer.news.verio.net!news.verio.net!iad-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7754 "David G. Conroy" wrote: > In article <3BFC7282.4557835A@mrnutty.com>, SkyWriter > wrote: > > > Weren't there a plethora of 'redundant resources' to aid in > > wafer yields? could you see those in the tools too? > The tools only show resources you can actually use, so I would not > expect to see redundant resources, if they happened to exist. > I don't know if they actually do exist, although I remember admiring the > layout in one of the older devices (a 3090, if I remember correctly) > and it seemed to look more-or-less as described. > > > In my experience, if you got them worried, you were already > > in trouble. YMMV (with luck). > The part that sticks in my mind was a slice of a crossbar chip, > built in a 3090A. The design was symmetric, and the designer lavished > care on one tile, and then replicated the tile throughout the > device. It used all the pins, all the CLBS, all the TBUFS, all the long > lines, all the direct interconnect, an a good chunk of the crappy > interconnect, and it was pipelined, so it ran fast. At the time it was the > highest utilization design they had ever seen, and it may still be. sounds like a lot of work. wouldn't an ASIC have been better in the long run. ###### From: "David G. Conroy" Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 11 Message-ID: <%ibL7.4851$Le.116576@sea-read.news.verio.net> Date: Thu, 22 Nov 2001 18:17:31 GMT NNTP-Posting-Host: 64.171.6.229 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1006453051 64.171.6.229 (Thu, 22 Nov 2001 18:17:31 GMT) NNTP-Posting-Date: Thu, 22 Nov 2001 18:17:31 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.abs.net!newsfeed.cwix.com!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7770 ---------- In article <3BFD3EBF.62DBDB54@mrnutty.com>, SkyWriter wrote: > sounds like a lot of work. wouldn't an ASIC have been better in > the long run. It took a week or two to do. If the design had been high volume enough to make building an ASIC worthwhile (which it didn't) we would have easily spent more time that that struggling with losing ASIC cad tools. ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> <%ibL7.4851$Le.116576@sea-read.news.verio.net> <3BFDA9AE.B8DB4824@mrnutty.com> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 22 Nov 2001 15:32:21 -0800 Message-ID: Lines: 16 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 22 Nov 2001 15:34:30 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed.nextra.ch!news.nextra.ch!nextra.at!peernews.cix.co.uk!shale.ftech.net!news.ftech.net!dispose.news.demon.net!demon!feeder.qis.net!feed2.onemain.com!feed1.onemain.com!cyclone-sf.pbi.net!206.13.28.125!cyclone-transit.snfc21.pbi.net!216.218.192.242!news.he.net!news.kjsl.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch alt.sys.pdp10:7768 SkyWriter writes: > Why do you say 'losing ASIC cad tools'? If you'd ever tried ASIC design, you'd know. Unlike, say, Windows, the ASIC tools are only used by a relatively small number of people, but the people that do use them tend to use them hard. For a low-volume product that's used hard, it's difficult for vendors to maintain consistently high quality. There are always a lot of rough edges. Of course, Microsoft is unable to maintain consistently high quality on Windows either, and it has a lot of rough edges. But that's for an entirely different reason: they don't care about the quality because they can always sell you an update later. In fact, it's in their best interest for there to be a lot of bugs. ###### Message-ID: <3BFDA9AE.B8DB4824@mrnutty.com> From: SkyWriter Organization: NUTTY INDUSTRIES X-Mailer: Mozilla 4.78C-SGI [en] (X11; I; IRIX 6.5 IP32) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> <%ibL7.4851$Le.116576@sea-read.news.verio.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: zaphod!unknown@5300-238.024.popsite.net X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Lines: 17 Date: Thu, 22 Nov 2001 17:43:10 -0800 NNTP-Posting-Host: 199.224.11.10 X-Complaints-To: abuse@verio.net X-Trace: iad-read.news.verio.net 1006468361 199.224.11.10 (Thu, 22 Nov 2001 22:32:41 GMT) NNTP-Posting-Date: Thu, 22 Nov 2001 22:32:41 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed.nextra.ch!news.nextra.ch!nextra.at!newsfeed4.cidera.com!newsfeed1.cidera.com!Cidera!easynews!sjc-peer.news.verio.net!news.verio.net!iad-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7753 "David G. Conroy" wrote: > ---------- > In article <3BFD3EBF.62DBDB54@mrnutty.com>, SkyWriter > wrote: > > > sounds like a lot of work. wouldn't an ASIC have been better in > > the long run. > > It took a week or two to do. If the design had been > high volume enough to make building an ASIC worthwhile (which it didn't) > we would have easily spent more time that that struggling with > losing ASIC cad tools. Why do you say 'losing ASIC cad tools'? ###### From: Arthur Krewat Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA Organization: Kilonet.net Lines: 37 Message-ID: <3BFDB7E8.BA62E8ED@bartek.dontspamme.net> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> <%ibL7.4851$Le.116576@sea-read.news.verio.net> <3BFDA9AE.B8DB4824@mrnutty.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.78 [en] (X11; U; SunOS 5.8 i86pc) X-Accept-Language: en Date: Fri, 23 Nov 2001 02:47:56 GMT NNTP-Posting-Host: 24.186.100.134 X-Trace: news02.optonline.net 1006483676 24.186.100.134 (Thu, 22 Nov 2001 21:47:56 EST) NNTP-Posting-Date: Thu, 22 Nov 2001 21:47:56 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed.nextra.ch!news.nextra.ch!nextra.at!peernews.cix.co.uk!shale.ftech.net!news.ftech.net!dispose.news.demon.net!demon!europa.netcrusader.net!208.184.7.66!newsfeed1.cidera.com!Cidera!cyclone2.usenetserver.com!usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7766 Eric Smith wrote: > > SkyWriter writes: > > Why do you say 'losing ASIC cad tools'? > > If you'd ever tried ASIC design, you'd know. > > Unlike, say, Windows, the ASIC tools are only used by a relatively small > number of people, but the people that do use them tend to use them hard. > For a low-volume product that's used hard, it's difficult for vendors to > maintain consistently high quality. There are always a lot of rough > edges. Add to that mix the fact that they have to produce UNIX and Windows versions and sometimes the Windows version wins out (now THAT's an oxymoron). In the past few years I have maintained systems with multiple versions of every CAD/EE/etc product you can imagine (Lattice/Altera/Xilinx/Powerview/ProE/Cadence/CADDS4x/CADDS5)... Over time, it seems they (collective THEY) have put the Windows versions ahead of the UNIX versions because more and more people accepted NT in the workplace. Can't imagine why, UNIX workstations being so expensive (3 years ago) and the fact that the UNIX version of whatever software costs around 3 times as much as the Windows version... > Of course, Microsoft is unable to maintain consistently high quality on > Windows either, and it has a lot of rough edges. But that's for an > entirely different reason: they don't care about the quality because they > can always sell you an update later. In fact, it's in their best interest > for there to be a lot of bugs. Oh yes - there appears one consistent thread with people using PC's - they never EVER understand that the underlying instability is in the OS and not the hardware... aak ###### From: "David G. Conroy" Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> <%ibL7.4851$Le.116576@sea-read.news.verio.net> <3BFDA9AE.B8DB4824@mrnutty.com> Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 19 Message-ID: Date: Fri, 23 Nov 2001 06:03:36 GMT NNTP-Posting-Host: 64.171.6.229 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1006495416 64.171.6.229 (Fri, 23 Nov 2001 06:03:36 GMT) NNTP-Posting-Date: Fri, 23 Nov 2001 06:03:36 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.bme.hu!andromeda.datanet.hu!newsfeed.gamma.ru!Gamma.RU!newsfeed.media.kyoto-u.ac.jp!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7771 In article , Eric Smith wrote: > SkyWriter writes: >> Why do you say 'losing ASIC cad tools'? > > If you'd ever tried ASIC design, you'd know. > > Unlike, say, Windows, the ASIC tools are only used by a relatively small > number of people, but the people that do use them tend to use them hard. > For a low-volume product that's used hard, it's difficult for vendors to > maintain consistently high quality. There are always a lot of rough > edges. If all I had to deal with was rough edges I'd be delighted. Sadly, the state of the art is stunningly low-quality output, or just-plain-wrong output, or (my favorite) correct output from program N which program N+1 in the same suite won't read in. ###### Message-ID: <3BFEBE71.1A848768@mrnutty.com> From: SkyWriter Organization: NUTTY INDUSTRIES X-Mailer: Mozilla 4.78C-SGI [en] (X11; I; IRIX 6.5 IP32) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> <%ibL7.4851$Le.116576@sea-read.news.verio.net> <3BFDA9AE.B8DB4824@mrnutty.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: zaphod!unknown@5300-238.024.popsite.net X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Lines: 12 Date: Fri, 23 Nov 2001 13:24:01 -0800 NNTP-Posting-Host: 199.224.11.10 X-Complaints-To: abuse@verio.net X-Trace: iad-read.news.verio.net 1006539158 199.224.11.10 (Fri, 23 Nov 2001 18:12:38 GMT) NNTP-Posting-Date: Fri, 23 Nov 2001 18:12:38 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed.nextra.ch!news.nextra.ch!nextra.at!newsfeed4.cidera.com!newsfeed1.cidera.com!Cidera!easynews!sjc-peer.news.verio.net!news.verio.net!iad-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7752 Eric Smith wrote: > SkyWriter writes: > > Why do you say 'losing ASIC cad tools'? > > If you'd ever tried ASIC design, you'd know. > I have been doing it for 13+ years, and will probably keep doing it. ###### Message-ID: <3BFEBEF9.ECEFC994@mrnutty.com> From: SkyWriter Organization: NUTTY INDUSTRIES X-Mailer: Mozilla 4.78C-SGI [en] (X11; I; IRIX 6.5 IP32) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> <%ibL7.4851$Le.116576@sea-read.news.verio.net> <3BFDA9AE.B8DB4824@mrnutty.com> <3BFDB7E8.BA62E8ED@bartek.dontspamme.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: zaphod!unknown@5300-238.024.popsite.net X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Lines: 13 Date: Fri, 23 Nov 2001 13:26:17 -0800 NNTP-Posting-Host: 199.224.11.10 X-Complaints-To: abuse@verio.net X-Trace: iad-read.news.verio.net 1006539293 199.224.11.10 (Fri, 23 Nov 2001 18:14:53 GMT) NNTP-Posting-Date: Fri, 23 Nov 2001 18:14:53 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!dca6-feed2.news.digex.net!intermedia!newsfeed1.cidera.com!Cidera!easynews!sjc-peer.news.verio.net!news.verio.net!iad-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7755 Arthur Krewat wrote: > > Oh yes - there appears one consistent thread with people using PC's - they > never EVER understand that the underlying instability is in the OS and not > the hardware... > As someone that never uses PC's, I don't trust the hardware either. > > aak ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA Date: 23 Nov 2001 22:34:03 +0100 Organization: My own Private Self Lines: 29 Message-ID: <6uelmpuq7o.fsf@chonsp.franklin.ch> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1006551243 399 10.0.3.2 (23 Nov 2001 21:34:03 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 23 Nov 2001 21:34:03 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7776 "David G. Conroy" writes: > In article <3BFC7282.4557835A@mrnutty.com>, SkyWriter > wrote: > > > Weren't there a plethora of 'redundant resources' to aid in > > wafer yields? could you see those in the tools too? > The tools only show resources you can actually use, so I would not > expect to see redundant resources, if they happened to exist. > I don't know if they actually do exist, although I remember admiring the > layout in one of the older devices (a 3090, if I remember correctly) > and it seemed to look more-or-less as described. About 1 week ago that question got asked on comp.arch.fpga. One of the Xilinx guys on the group stated that their chips have no redundant resources at all. Not possible to do sensibly with their architecture. According to him Altera does do it. They even have an patent on using an laser to cut chip traces for this. I assume that to be in the routing, as theirs is very regular long lines, while Xilinx has many small segments that are linked by switch transistors. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> <%ibL7.4851$Le.116576@sea-read.news.verio.net> <3BFDA9AE.B8DB4824@mrnutty.com> <3BFEBE71.1A848768@mrnutty.com> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 23 Nov 2001 14:38:28 -0800 Message-ID: Lines: 11 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 23 Nov 2001 14:40:48 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!newsfeeds.belnet.be!news.belnet.be!feed2.onemain.com!feed1.onemain.com!cyclone-sf.pbi.net!206.13.28.125!cyclone-transit.snfc21.pbi.net!216.218.192.242!news.he.net!news.kjsl.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch alt.sys.pdp10:7788 SkyWriter writes: > Why do you say 'losing ASIC cad tools'? I wrote: > If you'd ever tried ASIC design, you'd know. SkyWriter writes: > I have been doing it for 13+ years, and will probably keep doing it. Well, if you haven't had to deal with 'losing ASIC CAD tools', those of us who have would *love* to know what you've been using. ###### From: Arthur Krewat Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA Organization: Kilonet.net Lines: 17 Message-ID: <3BFFC838.4AAA5BD5@bartek.dontspamme.net> References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> <%ibL7.4851$Le.116576@sea-read.news.verio.net> <3BFDA9AE.B8DB4824@mrnutty.com> <3BFDB7E8.BA62E8ED@bartek.dontspamme.net> <3BFEBEF9.ECEFC994@mrnutty.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.78 [en] (X11; U; SunOS 5.8 i86pc) X-Accept-Language: en Date: Sat, 24 Nov 2001 16:22:57 GMT NNTP-Posting-Host: 24.186.100.134 X-Trace: news02.optonline.net 1006618977 24.186.100.134 (Sat, 24 Nov 2001 11:22:57 EST) NNTP-Posting-Date: Sat, 24 Nov 2001 11:22:57 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed.nextra.ch!news.nextra.ch!nextra.at!newsfeed4.cidera.com!newsfeed1.cidera.com!Cidera!cyclone2.usenetserver.com!usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7787 SkyWriter wrote: > > Arthur Krewat wrote: > > > > > Oh yes - there appears one consistent thread with people using PC's - they > > never EVER understand that the underlying instability is in the OS and not > > the hardware... > > > > As someone that never uses PC's, I don't trust the hardware either. > I agree, although the hardware ain't all that bad... QC stinks on most PC hardware and you have to be your own quality assurance staff :) aak ###### Message-ID: <3C01818B.6A0CCF74@mrnutty.com> From: SkyWriter Organization: NUTTY INDUSTRIES X-Mailer: Mozilla 4.78C-SGI [en] (X11; I; IRIX 6.5 IP32) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> <6uzo5yywwz.fsf@chonsp.franklin.ch> <9sehaj$rm5@gap.cco.caltech.edu> <6ubsidasnh.fsf@chonsp.franklin.ch> <3BEAC3A7.822A3E04@jetnet.ab.ca> <9sgd42$6kj$1@bob.news.rcn.net> <3BEC0125.798C3186@bartek.dontspamme.net> <3BEC320A.6553BB35@jetnet.ab.ca> <3BF88520.58CE9075@mrnutty.com> <3BF7A0E5.BF09A73B@jetnet.ab.ca> <3BFB0B84.50346BCB@mrnutty.com> <3BFC7282.4557835A@mrnutty.com> <3BFD3EBF.62DBDB54@mrnutty.com> <%ibL7.4851$Le.116576@sea-read.news.verio.net> <3BFDA9AE.B8DB4824@mrnutty.com> <3BFEBE71.1A848768@mrnutty.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: zaphod!unknown@5300-238.024.popsite.net X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Lines: 24 Date: Sun, 25 Nov 2001 15:40:59 -0800 NNTP-Posting-Host: 199.224.11.10 X-Complaints-To: abuse@verio.net X-Trace: iad-read.news.verio.net 1006720077 199.224.11.10 (Sun, 25 Nov 2001 20:27:57 GMT) NNTP-Posting-Date: Sun, 25 Nov 2001 20:27:57 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.abs.net!newsfeed.cwix.com!sjc-peer.news.verio.net!news.verio.net!iad-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7802 Eric Smith wrote: > SkyWriter writes: > > Why do you say 'losing ASIC cad tools'? > > I wrote: > > If you'd ever tried ASIC design, you'd know. > > SkyWriter writes: > > I have been doing it for 13+ years, and will probably keep doing it. > > Well, if you haven't had to deal with 'losing ASIC CAD tools', those > of us who have would *love* to know what you've been using. I never had 'critical' problems with Synopsys, Cadence Verilog-XL, or LSI, and Toshiba design kits/silicon. I did have bad experiences with other vendors products that I would class as 'losing ASIC CAD tools' but I won't mention them here, or condemn the design platform. ###### Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: <3BE73260.E916A5E2@jetnet.ab.ca> Organization: Me, Myself and I X-Newsreader: trn 4.0-test74 (May 26, 2000) From: mrr@reistad.priv.no (Morten Reistad) Originator: mrr@reistad.priv.no (Morten Reistad) Message-ID: Lines: 105 Date: Tue, 01 Jan 2002 14:13:02 GMT NNTP-Posting-Host: 193.71.26.5 X-Complaints-To: newsmaster@KPNQwest.no X-Trace: nreader1.kpnqwest.net 1009894382 193.71.26.5 (Tue, 01 Jan 2002 15:13:02 MET) NNTP-Posting-Date: Tue, 01 Jan 2002 15:13:02 MET Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!newsfeeds.belnet.be!news.belnet.be!news2.kpn.net!news.kpn.net!nslave.kpnqwest.net!nloc.kpnqwest.net!nmaster.kpnqwest.net!nreader1.kpnqwest.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:8895 In article , David Razler wrote: > >Well, I wouldn't mind a *better* 8, what I really want is the moral >equivalent of a PDP-10, say as fast as the fastest CPU made, which can >be slowed/dumbed down to play PDP-6 or PDP-3. Must include some wahy [snip] >Now, with a standardized size, assuming one PCI board for each really >different product made before the magic went away, the PDP-1, the >PDP3-6-10-20, 4-7-9-15, LINC, PDP5-8(letters), with its own local >memory but using the host system's HDC, video/front panel, NIC to do >the heavy lifting we could put Every Important DEC Architecture in >a single box, and, with luck, have an open slot for PDP-11-VAXen. [snip] >Put a handle on top of the tower case and you've got The Complete >History of Arguably the world's most important computer company of the >1960s&70s in a Box Travelling Roadshow. > >If we get lucky and the damned fools >who did all the mask work to build about 50 Eniac chips and then just >shut the whole production line down because it worked to do it right, >we'd have Yet Another Computer to add.... > > Maybe a rainbow-striped case for DEC (using the colors from >each of their machines) and a blue one for IBMs on a grid (though >mainframes are more difficult to emulate in tight spaces, grey for >Univac, The Official State Color(s) of Massachusetts (or a Route 128 >sign stencil) for DG, PR1ME and the host of others I'm forgetting, and >we have something everyone involved in computers when computers were >(or still are) fun would want. ("None of the Class, None of the Cash, >None of the Work, Power or Airconditioning as the Real Thing") As a long-time user of Pr1me after DEC canned the '20 (not moving to the VAX was a statement of principle) I can attest to the fact that this architecture will be a REAL challenge to emulate. It has layers of (in)compatability, somewhat like a Pentium. Deepest down it is a Honeywell machine, somewhat similar to the ones found inside the IMPs. Primos-II ran on this up until some version. 16-bit, limited register set. I am not sure if this is what Pr1me called 'I'-mode or 'R'-mode. The other mode is a similar one, but with a more elaborate register set, and with easier segment adaption. Then the Prime 300 was layered outside this. They called that V-mode; 16/32 bit with segments, they made some omissions that really hurt performance; this was fixed in the 450, and that remained they mainstay of the Pr1me architecture for a decade. This 450 architecture was similar to the 8086; except the handling of multiple segments was infinately better; and it was much nearer to a clean 32-bitter than Intel came. This mode was called V-mode; with the builtin ambiguity from the early models. The 750 was the main machine, but there was a two-processor SMP called the 850. This was Pr1me's only pure SMP until the 5000 series. These modes handled C-style flat, pointer accessed memory badly. Enter IX-mode; supported from 2550 onwards. Took them a looong time to get the last bugs out of that microcode. The models showed up in compilers, and there were no less than three full linker environments; LOAD, SEG and BIND. Peripherals were another issue. When IX mode came along the 'plain controller' went away; and there were a host of all kinds of outborded microprocessor controlled controllers; the IDC1,2 and 3 comms controllers replaced trusty old AMLC and MDLC boards; the 4005 SMD controller got replaced with the IDC series of disks, for ESMD, SCSI etc. Ditto for tape and Ringnet; but the URC never got replaced. Ethernet had a lot of TCP/IP outboarded. There was a LOT of microcode for this. The controllers also had separate protocols for everything, and none of this is available in acccessible documentation. Pr1me, CV and the caretakers of Pr1mos has always had a very anal view on licensing. When you sold your box, that was without OS, and licensing terms effectively killed the secondary market; except when Prime itself sold the box. Also, source licenses were always several minor versions behind, and bounded by draconian measures. I probably have one of the very few, legal private Primos based computers; that is because I bought it off the bankrupcy court in an auction. This means I take over ALL rights from the bankrupt party; as if there never was a sale. But; I can NOT sell it. It is a 2350 btw. Emulating all of this is a fairly tall order. -- mrr ###### From: Paul Repacholi Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA Date: 02 Jan 2002 03:57:47 +0800 Organization: iQnet Lines: 22 Sender: prep@k9 Message-ID: <871yh9c090.fsf@prep.synonet.com> References: <3BE73260.E916A5E2@jetnet.ab.ca> NNTP-Posting-Host: news-01.core.usertools.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: nnrp.waia.asn.au 1009927460 20498 203.12.222.155 (1 Jan 2002 23:24:20 GMT) X-Complaints-To: usenet@nnrp.waia.asn.au NNTP-Posting-Date: Tue, 1 Jan 2002 23:24:20 +0000 (UTC) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Cache-Post-Path: angelina!unknown@p244.ch01.auto.usertools.net X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!skynet.be!skynet.be!newsfeed.iinet.net.au!nntp.waia.asn.au!nnrp.waia.asn.au!127.0.0.1!nobody Xref: chonsp.franklin.ch alt.sys.pdp10:8916 mrr@reistad.priv.no (Morten Reistad) writes: > I probably have one of the very few, legal private Primos based > computers; that is because I bought it off the bankrupcy court in an > auction. This means I take over ALL rights from the bankrupt party; > as if there never was a sale. But; I can NOT sell it. It is a 2350 > btw. So I am not the only one who has done this :) Minor difference, over here, full and clear title is garenteed by the Supreme Court. So if the original vendor does not like it, they argue with the court, not me ;) Damm. I had almost managed to forget the horrid mess that writhed around in those cabs. -- Paul Repacholi 1 Crescent Rd., +61 (08) 9257-1001 Kalamunda. West Australia 6076 Raw, Cooked or Well-done, it's all half baked. EPIC, The Architecture of the future, always has been, always will be. ###### Newsgroups: alt.sys.pdp10,alt.sys.pdp8 Subject: Re: Another DEC computer in an FPGA References: <3C31D703.D39FCF27@Empire.Net> Organization: Me, Myself and I X-Newsreader: trn 4.0-test74 (May 26, 2000) From: mrr@reistad.priv.no (Morten Reistad) Originator: mrr@reistad.priv.no (Morten Reistad) Message-ID: Lines: 27 Date: Wed, 02 Jan 2002 20:13:03 GMT NNTP-Posting-Host: 193.71.26.5 X-Complaints-To: newsmaster@KPNQwest.no X-Trace: nreader1.kpnqwest.net 1010002383 193.71.26.5 (Wed, 02 Jan 2002 21:13:03 MET) NNTP-Posting-Date: Wed, 02 Jan 2002 21:13:03 MET Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!193.154.160.102.MISMATCH!newsfeed.Austria.EU.net!newsfeed.kpnqwest.at!nslave.kpnqwest.net!nloc.kpnqwest.net!nmaster.kpnqwest.net!nreader1.kpnqwest.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:8938 In article <3C31D703.D39FCF27@Empire.Net>, John Sauter wrote: >Morten Reistad wrote (in small part): >I probably have one of the very few, legal private >Primos based computers; that is because I bought it >off the bankrupcy court in an auction. This means I >take over ALL rights from the bankrupt party; as if >there never was a sale. But; I can NOT sell it. It >is a 2350 btw. > >John Sauter responded: > >Since you have all rights, why can't you sell it? > John Sauter (J_Sauter@Empire.Net) Not ALL rights; ALL of the original owners rights. Reselling the OS is not among them. It is licensed to the owner only. However, bankrupcy law preempts licensing rights. And I can short-circuit any legal action from Prime etc with a contempt-of-court claim. The hardware can be sold, but the new owner would need an OS license to run Primos on it legally. A sale will end this special protection by the bankrupcy court. - mrr