Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: FPGA clone status, 2nd milestone reached (was Re: Another DEC computer in an FPGA) Date: 30 Dec 2001 02:15:37 +0100 Organization: My own Private Self Lines: 164 Message-ID: <6uadw1y0cm.fsf_-_@chonsp.franklin.ch> References: <6ud72xuhnb.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1009674937 2464 10.0.3.2 (30 Dec 2001 01:15:37 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 30 Dec 2001 01:15:37 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:8826 Neil Franklin writes: > While I am at it, I am nearing milestone 2. Just need to finish > test/debug of CA*/JUMP/SKIP/AO*/SP* unit. Well that "nearing" turned out to be nearly 2 months, thanks to: a) the most fiendish bug I have ever made, took 3 weeks to find, was an missed edit of an X to an Y, in already (insufficiently) tested code, so I was looking in the wrong place, then suspecting an debugger bug. b) an design error in the SOS/SOJ subtractor, combined with being overworked on my job and too tired to get up the needed concentration. Add to that losing another 3 weeks before making that statement, due to an tool bug and redesigning to get round it. That screwed up my plans for this milestone to take less than the 5.5 months of the first, instead it took 6.5 months. Today, after 1 week of holiday, I had again time and concentration, so I have now reached the second milestone, and so am posting the second status report. Target for second Milestone Expand the minimal runnable subset of functionality from the first milestone into an solid foundation for all the rest of functionality, and add an second group of instructions to it. That turned out to be: - an new 8-instruction program and 16 data words for testing - add jump capability to the program counter (skip was already there, from fetching instructions) - redesign instruction register loader mux for more readable code and more robustness and less logic cost - replace arithmetic register and muxes (derived from the original PDP-6 design) with an new system that uses separate ARs for each function unit and an simple mux to write back to memory. This uses more FFs (which are free) and gets rid of an large complex mux (which is expensive and slow and requires complex control logic) - add an mux for direct using of 0,,E instead of first copying to AR (this saving one clock cycle on all 0,,E using instructions) - updated the boolen logic unit to use all the new infrastructure - moved the state machine and logic function design docs into the main source code, made scripts to extract them - added the arithmetic testing unit for the 8 011tttmmm instructions (CAI, CAM, JUMP, SKIP, AOJ, AOS, SOJ, SOS) - analysed (but not yet designed or implemented) 2 more instruction groups 101tootmm (H*) and 110ooamma (T*) - documented decisions on implementation row of all the other groups Test program The mentioned new program and data were thus: ------ // bit 0 1 2 3 // 012345678901234567890123456789012345 // fill the 16 registers // data for C(MA) Rin[000] = "000000000000000000000000000000000000"; Rin[001] = "111111111111111111111111111111111111"; Rin[002] = "010101010101010101010101010101010101"; Rin[003] = "001100110011001100110011001100110011"; Rin[004] = "000111000111000111000111000111000111"; Rin[005] = "000011110000111100001111000011110000"; Rin[006] = "000001111100000111110000011111000001"; Rin[007] = "000000111111000000111111000000111111"; // index registers, for MA(IR.X) Rin[010] = "000000000000000000000000000000000001"; Rin[011] = "000000000000000000000000000000000010"; Rin[012] = "000000000000000000000000000000000100"; Rin[013] = "000000000000000000000000000000001000"; // data space, for C(AC), to process and overwrite Rin[014] = "001110010101010100001010111110110000"; Rin[015] = "001001010101101101100010110111000111"; Rin[016] = "100101011101110000000110110111100001"; Rin[017] = "001111010101000001110110111000000110"; // fill the rest of memory // program code, to execute // OOOOOOOOOAAAAIXXXXYYYYYYYYYYYYYYYYYY // PDP-10 instr format // 100ffffmm........................... // bool logic sub form Rin[020] = "100000000110000000000000000000000001"; // SETZ 14,1 Rin[021] = "100000101110100000010010110001100100"; // AND I 15,226144 Rin[022] = "100001010111000000000000000000000010"; // ANDCA M 16,2 Rin[023] = "100001111110000000000000000000000100"; // SETM B 14,4 Rin[024] = "100010000110101000000000000000000010"; // ANDCM 15,2(10) Rin[025] = "100010101111001001000000000000000101"; // SETA I 16,5(11) Rin[026] = "100100010111010000000000000000000110"; // ANDCB M 16,@7 Rin[027] = "100100111110010000000000000000000010"; // EQV B 14,@2 // 011tttmmm........................... // arith test sub form Rin[030] = "011000011111100000000100101001101000"; // CAI LE 17,45150 Rin[031] = "011001010111000000000000000000000100"; // CAM E 16,4 Rin[032] = "011011001110100000000000000000000011"; // SKIP L 15,3 Rin[033] = "011101000110001010000000000000000110"; // AOS 14,6(12) Rin[034] = "011111111111100000000000000000000001"; // SOS G 17,1 Rin[035] = "011100110000100000000000000000011010"; // AOJ N 1,32 Rin[036] = "011110101110100000000000000000011001"; // SOJ GE 15,31 Rin[037] = "011010100110000000000000000000011000"; // JUMP A 14,30 // where to start, for setting initial program counter int RinStartAt = 037; ------ The program counter is now set to start up at RinStartAt, instead of constant 020, so this tests all 8 011tttmmm instructions (100ffffmm were tested with the old program and start up). This performs now, as far as I can see, without any errors. Speed of the present design Stayed the same, apart from using 0,,E being now faster (parallel to memory read for other operand). Archive of this milestone I have archived this second milestone as: http://neil.franklin.ch/Projects/PDP-10/Milestone-20011229/ The first milestone remains archived at: http://neil.franklin.ch/Projects/PDP-10/Milestone-20010516/ The current work continues in: http://neil.franklin.ch/Projects/PDP-10/ Target for third Milestone - separate memory and registers and decoding between them, allowing KI-10 style parallel writing - multiple register read ports, getting rid of address mux delays and mux control logic and its delays. This also anticipates future pipelined parallel register reads, needed for 486 or above speed - possibly support for memory with wait states - larger 64word LUT or 512word BRAM memory for larger test programs - design and implement the 101tootmm (H*) and 110ooamma (T*) instruction groups This should also take less than the 5.5 months the first milestone took :-). But the problems with my job remain, so it may be delayed by them. And tool trouble may also take its share. Target for further out - both 3 week bugs were due to the tools I am using. I intend to replace them with own ones. This will of course delay the project even further - the impact from my job remains. And I am not enjoying the job either, and I do not even need the money (got enough saved for 3 years). So I am about 95% decided on leaving the job, that should give me a lot of time for tools and this project from May onwards -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery