Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: FPGA clone status, 1st milestone reached (was Re: Dear Friends....) Date: 16 May 2001 23:15:17 +0200 Organization: My own Private Self Lines: 143 Message-ID: <6u4rulq9lm.fsf_-_@chonsp.franklin.ch> References: <4crgftsht3boroqhg89hnp2kg01u16p2df@4ax.com> <3AF87869.9916114B@bartek.dontspamme.net> <6uoft2e6rw.fsf@chonsp.franklin.ch> <3afdc658.6682889@news.m.iinet.net.au> <6ur8xtknhg.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 990047717 2354 10.0.3.2 (16 May 2001 21:15:17 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 16 May 2001 21:15:17 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:5029 Neil Franklin writes: > Getting on nicely. I am about 1 work session [1] away from reaching > the first milestone. I intend to make an post detailing what is running > when that is reached and archived on the web. Today I had time again, and I have now reached the milestone, and so am posting the anticipated status report. Target for first Milestone I am new to both PDP-10 and to FPGAs. So I as first milestone set to learn enough of both to implement an minimal runnable subset of functionality to see if I understood both. PDP-10 wise that has turned out to be: - an 32 word memory (2 sets of 16 registers actually) - an 16-instruction program and 16 data words for testing - an mechanism to load program/data from separate source file into the memory - the multiplexer to control what addresses memory (PC, MA, AC, X) - the program counter (PC register and incrementer) - the instruction register and loader to eliminate evaluated X and I parts - the instruction fetch and E evaluation state machine - the memory address register with indexing adder - the arithmetic register with loading multiplexer for 0,,E/MD/output - the boolen logic unit for the 16 100ffffmm instruction functions - the logic instruction evaluation state machine with 4 modes decoder FPGA wise that turned out to be: - learning the Java language which is used for the programs - learning the JBits functions to program the FPGA - learning the BoardScope and DeviceSimulator tools - calculating the placing of logic - programming most features of CLB logic blocks - routing between the various CLBs Test Program The mentioned program and data were thus: ---------------------- 000000000000000000000000000000000000 - 00 # Projects/PDP-10/pdp10.mem 111111111111111111111111111111111111 # memory image for pdp10.java|.class 010101010101010101010101010101010101 # author Neil Franklin 001100110011001100110011001100110011 # last modification 2001.05.16 000111000111000111000111000111000111 000011110000111100001111000011110000 # 00..07 data patterns of YYY 000001111100000111110000011111000001 000000111111000000111111000000111111 000000000000000000000000000000000001 - 10 # 10..13 index registers 000000000000000000000000000000000010 000000000000000000000000000000000100 000000000000000000000000000000001000 001110010101010100001010111110110000 # 14..17 data to overwrite 001001010101101101100010110111000111 100101011101110000000110110111100001 001111010101000001110110111000000110 100000000110000000000000000000000000 - 20 # SETZ 14,0 set zero 100000101110100000000000000000000100 # AND I 15,4 and 100001010111000000000000000000000000 # ANDCA M 16,0 and compl acc 100001111110000000000000000000000100 # SETM B 14,4 set mem 100010000110101000000000000000000010 # ANDCM 15,2(10) and compl mem 100010101111001001000000000000000100 # SETA I 16,4(11) set acc 100011010110001010000000000000000000 # XOR M 14,0(12) excl or 100011111110101011000000000000000110 # IOR B 15,6(13) incl or 100100000111010000000000000000000110 - 30 # ANDCB 16,@6 and compl both 100100101110010000000000000000000010 # EQV I 14,@2 equiv 100101010110110000000000000000001000 # SETCA M 15,@10 set compl acc 100101111111010000000000000000001100 # ORCA B 16,@14 or compl acc 100110000110011000000000000000000000 # SETCM 14,@0(10) set compl mem 100110101110111001000000000000000100 # ORCM I 15,@4(11) or compl mem 100111010111011010000000000000000010 # ORCB M 16,@2(12) or compl both 100111111110011011000000000000000101 - 37 # SETO B 14,@5(13) set ones OOOOOOOOOAAAAIXXXXYYYYYYYYYYYYYYYYYY # pdp10 instruction format 100FFFFMM # boolean logic instr sub-format -------------------- This program was run using the "BoardScope" interface connected to the "DeviceSimulator" chip simulation tool. Visible output is the flipflops of the chip changing while work is going on. The program counter is fixed to start up at 20, so this tested all 16 100ffffmm instructions, and all possible combinations of indexed and indirect addressing, using the majority of registers. It performs now, as far as I can see, without any errors. Speed of the present design It uses 1 clock pulse for loading an instruction. Each indexing or indirection costs 1 additional clock. All normal/I/M modes of logic instructions cost 3 clocks (2 fetch, 1 store). B mode costs 4 clocks (2 stores). So it uses average 4-6 clocks for normal code, which even at an totally undercritical 24MHz clock (I expect the present top to be 40-80MHz) would give 4-6 MIPS. This is for straight forward code without any speed optimisations, comparable to when TS-10 was doing its 0.8 MIPS. Archive of this milestone I have archived this milestone as: http://neil.franklin.ch/Projects/PDP-10/Milestone-20010516/ The current work continues in: http://neil.franklin.ch/Projects/PDP-10/ Files for people who want to look/try it out are - Logfile - what I am doing at the present time (only in current) - Time-States - analysis of state machine and control logic - pdp10.java - Java/JBits source code to compile to pdp10.class - pdp10.class - compiled Java/JBits for generating pdp10.bit - pdp10.mem - the program to be loaded into memory when running pdp10.class - pdp10.bit - compiled design, for running in BS/DS Target for second Milestone PDP-10 side will be expanded with: - make the instruction decoder more universal for multiple instructions - same for the controls that drive the data path - add an further set of instructions, most likely the 011xxxxxx jump/skip FPGA side will be expanded with: - using BRAMs for an larger 512word memory This should take less than the 5.5 months the first milestone took :-) -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: Mark Garrett Newsgroups: alt.sys.pdp10 Subject: Re: FPGA clone status, 1st milestone reached (was Re: Dear Friends....) Organization: Garetech Computer Solutions Lines: 149 Message-ID: References: <4crgftsht3boroqhg89hnp2kg01u16p2df@4ax.com> <3AF87869.9916114B@bartek.dontspamme.net> <6uoft2e6rw.fsf@chonsp.franklin.ch> <3afdc658.6682889@news.m.iinet.net.au> <6ur8xtknhg.fsf@chonsp.franklin.ch> <6u4rulq9lm.fsf_-_@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit User-Agent: Microsoft-Outlook-Express-Macintosh-Edition/5.02.2022 Date: Thu, 17 May 2001 02:51:03 GMT NNTP-Posting-Host: 144.132.244.163 X-Complaints-To: news@bigpond.net.au X-Trace: news-server.bigpond.net.au 990067863 144.132.244.163 (Thu, 17 May 2001 12:51:03 EST) NNTP-Posting-Date: Thu, 17 May 2001 12:51:03 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!news1.optus.net.au!optus!intgwpad.nntp.telstra.net!news-server.bigpond.net.au!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:5040 in article 6u4rulq9lm.fsf_-_@chonsp.franklin.ch, Neil Franklin at neil@franklin.ch.remove wrote on 17/05/2001 07:15: > Neil Franklin writes: > >> Getting on nicely. I am about 1 work session [1] away from reaching >> the first milestone. I intend to make an post detailing what is running >> when that is reached and archived on the web. > > Today I had time again, and I have now reached the milestone, and so > am posting the anticipated status report. > > > Target for first Milestone > > I am new to both PDP-10 and to FPGAs. So I as first milestone set to > learn enough of both to implement an minimal runnable subset of > functionality to see if I understood both. > > PDP-10 wise that has turned out to be: > > - an 32 word memory (2 sets of 16 registers actually) > - an 16-instruction program and 16 data words for testing > - an mechanism to load program/data from separate source file into the memory > - the multiplexer to control what addresses memory (PC, MA, AC, X) > - the program counter (PC register and incrementer) > - the instruction register and loader to eliminate evaluated X and I parts > - the instruction fetch and E evaluation state machine > - the memory address register with indexing adder > - the arithmetic register with loading multiplexer for 0,,E/MD/output > - the boolen logic unit for the 16 100ffffmm instruction functions > - the logic instruction evaluation state machine with 4 modes decoder > > FPGA wise that turned out to be: > > - learning the Java language which is used for the programs > - learning the JBits functions to program the FPGA > - learning the BoardScope and DeviceSimulator tools > - calculating the placing of logic > - programming most features of CLB logic blocks > - routing between the various CLBs > > > Test Program > > The mentioned program and data were thus: > > ---------------------- > 000000000000000000000000000000000000 - 00 # Projects/PDP-10/pdp10.mem > 111111111111111111111111111111111111 # memory image for pdp10.java|.class > 010101010101010101010101010101010101 # author Neil Franklin > 001100110011001100110011001100110011 # last modification 2001.05.16 > 000111000111000111000111000111000111 > 000011110000111100001111000011110000 # 00..07 data patterns of YYY > 000001111100000111110000011111000001 > 000000111111000000111111000000111111 > 000000000000000000000000000000000001 - 10 # 10..13 index registers > 000000000000000000000000000000000010 > 000000000000000000000000000000000100 > 000000000000000000000000000000001000 > 001110010101010100001010111110110000 # 14..17 data to overwrite > 001001010101101101100010110111000111 > 100101011101110000000110110111100001 > 001111010101000001110110111000000110 > 100000000110000000000000000000000000 - 20 # SETZ 14,0 set zero > 100000101110100000000000000000000100 # AND I 15,4 and > 100001010111000000000000000000000000 # ANDCA M 16,0 and compl acc > 100001111110000000000000000000000100 # SETM B 14,4 set mem > 100010000110101000000000000000000010 # ANDCM 15,2(10) and compl mem > 100010101111001001000000000000000100 # SETA I 16,4(11) set acc > 100011010110001010000000000000000000 # XOR M 14,0(12) excl or > 100011111110101011000000000000000110 # IOR B 15,6(13) incl or > 100100000111010000000000000000000110 - 30 # ANDCB 16,@6 and compl both > 100100101110010000000000000000000010 # EQV I 14,@2 equiv > 100101010110110000000000000000001000 # SETCA M 15,@10 set compl acc > 100101111111010000000000000000001100 # ORCA B 16,@14 or compl acc > 100110000110011000000000000000000000 # SETCM 14,@0(10) set compl mem > 100110101110111001000000000000000100 # ORCM I 15,@4(11) or compl mem > 100111010111011010000000000000000010 # ORCB M 16,@2(12) or compl both > 100111111110011011000000000000000101 - 37 # SETO B 14,@5(13) set ones > > OOOOOOOOOAAAAIXXXXYYYYYYYYYYYYYYYYYY # pdp10 instruction format > 100FFFFMM # boolean logic instr sub-format > -------------------- > > This program was run using the "BoardScope" interface connected to > the "DeviceSimulator" chip simulation tool. Visible output is the > flipflops of the chip changing while work is going on. > > The program counter is fixed to start up at 20, so this tested all 16 > 100ffffmm instructions, and all possible combinations of indexed and > indirect addressing, using the majority of registers. It performs now, > as far as I can see, without any errors. > > > Speed of the present design > > It uses 1 clock pulse for loading an instruction. Each indexing or > indirection costs 1 additional clock. All normal/I/M modes of logic > instructions cost 3 clocks (2 fetch, 1 store). B mode costs 4 clocks > (2 stores). > > So it uses average 4-6 clocks for normal code, which even at an > totally undercritical 24MHz clock (I expect the present top to be > 40-80MHz) would give 4-6 MIPS. This is for straight forward code > without any speed optimisations, comparable to when TS-10 was doing > its 0.8 MIPS. > > > Archive of this milestone > > I have archived this milestone as: > http://neil.franklin.ch/Projects/PDP-10/Milestone-20010516/ > > The current work continues in: > http://neil.franklin.ch/Projects/PDP-10/ > > Files for people who want to look/try it out are > > - Logfile - what I am doing at the present time (only in current) > - Time-States - analysis of state machine and control logic > - pdp10.java - Java/JBits source code to compile to pdp10.class > - pdp10.class - compiled Java/JBits for generating pdp10.bit > - pdp10.mem - the program to be loaded into memory when running pdp10.class > - pdp10.bit - compiled design, for running in BS/DS > > > Target for second Milestone > > PDP-10 side will be expanded with: > > - make the instruction decoder more universal for multiple instructions > - same for the controls that drive the data path > - add an further set of instructions, most likely the 011xxxxxx jump/skip > > FPGA side will be expanded with: > > - using BRAMs for an larger 512word memory > > This should take less than the 5.5 months the first milestone took :-) > An impressive bit of work! gratz Neil. I'm looking forward to you next update. Cheers Mark ###### Message-ID: <3B024B60.572780ED@jetnet.ab.ca> From: Ben Franchuk X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.18 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: FPGA clone status, 1st milestone reached (was Re: Dear Friends....) References: <4crgftsht3boroqhg89hnp2kg01u16p2df@4ax.com> <3AF87869.9916114B@bartek.dontspamme.net> <6uoft2e6rw.fsf@chonsp.franklin.ch> <3afdc658.6682889@news.m.iinet.net.au> <6ur8xtknhg.fsf@chonsp.franklin.ch> <6u4rulq9lm.fsf_-_@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 11 Date: Wed, 16 May 2001 03:41:52 -0600 NNTP-Posting-Host: 207.153.6.49 X-Trace: newsfeed.slurp.net 990060418 207.153.6.49 (Wed, 16 May 2001 19:46:58 CDT) NNTP-Posting-Date: Wed, 16 May 2001 19:46:58 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.slurp.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:5033 Neil Franklin wrote: > ( cut ) > This should take less than the 5.5 months the first milestone took :-) Just watch the size of the FPGA's used. Big chips get very pricey! The PROMS for the big chips are real pricey Too! -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: FPGA clone status, 1st milestone reached (was Re: Dear Friends....) Date: 17 May 2001 23:49:16 +0200 Organization: My own Private Self Lines: 36 Message-ID: <6uwv7faboj.fsf@chonsp.franklin.ch> References: <4crgftsht3boroqhg89hnp2kg01u16p2df@4ax.com> <3AF87869.9916114B@bartek.dontspamme.net> <6uoft2e6rw.fsf@chonsp.franklin.ch> <3afdc658.6682889@news.m.iinet.net.au> <6ur8xtknhg.fsf@chonsp.franklin.ch> <6u4rulq9lm.fsf_-_@chonsp.franklin.ch> <3B024B60.572780ED@jetnet.ab.ca> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 990136156 589 10.0.3.2 (17 May 2001 21:49:16 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 17 May 2001 21:49:16 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:5053 Ben Franchuk writes: > Neil Franklin wrote: > > ( cut ) > > This should take less than the 5.5 months the first milestone took :-) > > Just watch the size of the FPGA's used. Big chips get very pricey! I have seen that. Up to $3000 the largest ones seem to go. Makes even Intel look cheap :-) The one I am aiming for (XC2S200) is $40-50 single part, $120 mounted on a board with 5V -> 3.3V/2.5V power converter and programming mechanism. At the moment I am using 10x46 (COLxROW) of 84x56 logic elements, so I am below 10% of space utilisation. Not to mention that converting to BRAMs will free 2 of them 10 columns of LEs. Add then 9 4bit wide SRAMs. 1Mx4bit chips would give 1MWord, 4Mx4bit even the max 4MWord. And then the keyboard/monitor/rs232 module for $42. The hard disk will most likely be more expensive than the rest. > The PROMS for the big chips are real pricey Too! The XC17S02 needed is $20-30. Unfortunately that is a write-once PROM part, rewritable EEPROMs could be seriously larger priced. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: berd_kalamunda@techemail.com (Rolie Baldock) Newsgroups: alt.sys.pdp10 Subject: Re: FPGA clone status, 1st milestone reached (was Re: Dear Friends....) Date: Thu, 17 May 2001 22:38:23 GMT Message-ID: <3b0452aa.2472119@news.m.iinet.net.au> References: <4crgftsht3boroqhg89hnp2kg01u16p2df@4ax.com> <3AF87869.9916114B@bartek.dontspamme.net> <6uoft2e6rw.fsf@chonsp.franklin.ch> <3afdc658.6682889@news.m.iinet.net.au> <6ur8xtknhg.fsf@chonsp.franklin.ch> <6u4rulq9lm.fsf_-_@chonsp.franklin.ch> X-Newsreader: Forte Free Agent 1.11/16.235 Lines: 155 NNTP-Posting-Host: i177-098.nv.iinet.net.au X-Trace: news.iinet.net.au 990140887 14238 203.59.177.98 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!fr.clara.net!heighliner.fr.clara.net!skynet.be!newsfeed.iinet.net.au!news.iinet.net.au!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:5063 Hello Neil, I am watching your every move and recording same to HDD. Regards, On 16 May 2001 23:15:17 +0200, Neil Franklin wrote: >Neil Franklin writes: > >> Getting on nicely. I am about 1 work session [1] away from reaching >> the first milestone. I intend to make an post detailing what is running >> when that is reached and archived on the web. > >Today I had time again, and I have now reached the milestone, and so >am posting the anticipated status report. > > >Target for first Milestone > >I am new to both PDP-10 and to FPGAs. So I as first milestone set to >learn enough of both to implement an minimal runnable subset of >functionality to see if I understood both. > >PDP-10 wise that has turned out to be: > >- an 32 word memory (2 sets of 16 registers actually) >- an 16-instruction program and 16 data words for testing >- an mechanism to load program/data from separate source file into the memory >- the multiplexer to control what addresses memory (PC, MA, AC, X) >- the program counter (PC register and incrementer) >- the instruction register and loader to eliminate evaluated X and I parts >- the instruction fetch and E evaluation state machine >- the memory address register with indexing adder >- the arithmetic register with loading multiplexer for 0,,E/MD/output >- the boolen logic unit for the 16 100ffffmm instruction functions >- the logic instruction evaluation state machine with 4 modes decoder > >FPGA wise that turned out to be: > >- learning the Java language which is used for the programs >- learning the JBits functions to program the FPGA >- learning the BoardScope and DeviceSimulator tools >- calculating the placing of logic >- programming most features of CLB logic blocks >- routing between the various CLBs > > >Test Program > >The mentioned program and data were thus: > >---------------------- >000000000000000000000000000000000000 - 00 # Projects/PDP-10/pdp10.mem >111111111111111111111111111111111111 # memory image for pdp10.java|.class >010101010101010101010101010101010101 # author Neil Franklin >001100110011001100110011001100110011 # last modification 2001.05.16 >000111000111000111000111000111000111 >000011110000111100001111000011110000 # 00..07 data patterns of YYY >000001111100000111110000011111000001 >000000111111000000111111000000111111 >000000000000000000000000000000000001 - 10 # 10..13 index registers >000000000000000000000000000000000010 >000000000000000000000000000000000100 >000000000000000000000000000000001000 >001110010101010100001010111110110000 # 14..17 data to overwrite >001001010101101101100010110111000111 >100101011101110000000110110111100001 >001111010101000001110110111000000110 >100000000110000000000000000000000000 - 20 # SETZ 14,0 set zero >100000101110100000000000000000000100 # AND I 15,4 and >100001010111000000000000000000000000 # ANDCA M 16,0 and compl acc >100001111110000000000000000000000100 # SETM B 14,4 set mem >100010000110101000000000000000000010 # ANDCM 15,2(10) and compl mem >100010101111001001000000000000000100 # SETA I 16,4(11) set acc >100011010110001010000000000000000000 # XOR M 14,0(12) excl or >100011111110101011000000000000000110 # IOR B 15,6(13) incl or >100100000111010000000000000000000110 - 30 # ANDCB 16,@6 and compl both >100100101110010000000000000000000010 # EQV I 14,@2 equiv >100101010110110000000000000000001000 # SETCA M 15,@10 set compl acc >100101111111010000000000000000001100 # ORCA B 16,@14 or compl acc >100110000110011000000000000000000000 # SETCM 14,@0(10) set compl mem >100110101110111001000000000000000100 # ORCM I 15,@4(11) or compl mem >100111010111011010000000000000000010 # ORCB M 16,@2(12) or compl both >100111111110011011000000000000000101 - 37 # SETO B 14,@5(13) set ones > >OOOOOOOOOAAAAIXXXXYYYYYYYYYYYYYYYYYY # pdp10 instruction format >100FFFFMM # boolean logic instr sub-format >-------------------- > >This program was run using the "BoardScope" interface connected to >the "DeviceSimulator" chip simulation tool. Visible output is the >flipflops of the chip changing while work is going on. > >The program counter is fixed to start up at 20, so this tested all 16 >100ffffmm instructions, and all possible combinations of indexed and >indirect addressing, using the majority of registers. It performs now, >as far as I can see, without any errors. > > >Speed of the present design > >It uses 1 clock pulse for loading an instruction. Each indexing or >indirection costs 1 additional clock. All normal/I/M modes of logic >instructions cost 3 clocks (2 fetch, 1 store). B mode costs 4 clocks >(2 stores). > >So it uses average 4-6 clocks for normal code, which even at an >totally undercritical 24MHz clock (I expect the present top to be >40-80MHz) would give 4-6 MIPS. This is for straight forward code >without any speed optimisations, comparable to when TS-10 was doing >its 0.8 MIPS. > > >Archive of this milestone > >I have archived this milestone as: >http://neil.franklin.ch/Projects/PDP-10/Milestone-20010516/ > >The current work continues in: >http://neil.franklin.ch/Projects/PDP-10/ > >Files for people who want to look/try it out are > >- Logfile - what I am doing at the present time (only in current) >- Time-States - analysis of state machine and control logic >- pdp10.java - Java/JBits source code to compile to pdp10.class >- pdp10.class - compiled Java/JBits for generating pdp10.bit >- pdp10.mem - the program to be loaded into memory when running pdp10.class >- pdp10.bit - compiled design, for running in BS/DS > > >Target for second Milestone > >PDP-10 side will be expanded with: > >- make the instruction decoder more universal for multiple instructions >- same for the controls that drive the data path >- add an further set of instructions, most likely the 011xxxxxx jump/skip > >FPGA side will be expanded with: > >- using BRAMs for an larger 512word memory > >This should take less than the 5.5 months the first milestone took :-) > > >-- >Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ >Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer >- Intellectual Property is Intellectual Robbery -- email: for email delete the thousand and nine ###### From: berd-pee@perthmail.com (Rolie Baldock) Newsgroups: alt.sys.pdp10 Subject: Re: FPGA clone status, 1st milestone reached (was Re: Dear Friends....) Date: Sun, 01 Jul 2001 23:24:19 GMT Message-ID: <3b3fb0c4.6901765@news.m.iinet.net.au> References: <4crgftsht3boroqhg89hnp2kg01u16p2df@4ax.com> <3AF87869.9916114B@bartek.dontspamme.net> <6uoft2e6rw.fsf@chonsp.franklin.ch> <3afdc658.6682889@news.m.iinet.net.au> <6ur8xtknhg.fsf@chonsp.franklin.ch> <6u4rulq9lm.fsf_-_@chonsp.franklin.ch> X-Newsreader: Forte Free Agent 1.11/16.235 Lines: 156 NNTP-Posting-Host: i179-218.nv.iinet.net.au X-Trace: news.iinet.net.au 994031311 18964 203.59.179.218 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!news-peer.gip.net!news.gsl.net!gip.net!news.maxwell.syr.edu!news.stealth.net!nntp1.njy.teleglobe.net!teleglobe.net!nntp.cifnet.net!out.nntp.be!propagator-dallas!news-in-dallas.newsfeeds.com!newsfeed.iinet.net.au!news.iinet.net.au!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:5868 Hello Neil, When can we expect the second milestone to be achieved in the on-going saga of the FPGA version of the PDP-10? Regards, On 16 May 2001 23:15:17 +0200, Neil Franklin wrote: >Neil Franklin writes: > >> Getting on nicely. I am about 1 work session [1] away from reaching >> the first milestone. I intend to make an post detailing what is running >> when that is reached and archived on the web. > >Today I had time again, and I have now reached the milestone, and so >am posting the anticipated status report. > > >Target for first Milestone > >I am new to both PDP-10 and to FPGAs. So I as first milestone set to >learn enough of both to implement an minimal runnable subset of >functionality to see if I understood both. > >PDP-10 wise that has turned out to be: > >- an 32 word memory (2 sets of 16 registers actually) >- an 16-instruction program and 16 data words for testing >- an mechanism to load program/data from separate source file into the memory >- the multiplexer to control what addresses memory (PC, MA, AC, X) >- the program counter (PC register and incrementer) >- the instruction register and loader to eliminate evaluated X and I parts >- the instruction fetch and E evaluation state machine >- the memory address register with indexing adder >- the arithmetic register with loading multiplexer for 0,,E/MD/output >- the boolen logic unit for the 16 100ffffmm instruction functions >- the logic instruction evaluation state machine with 4 modes decoder > >FPGA wise that turned out to be: > >- learning the Java language which is used for the programs >- learning the JBits functions to program the FPGA >- learning the BoardScope and DeviceSimulator tools >- calculating the placing of logic >- programming most features of CLB logic blocks >- routing between the various CLBs > > >Test Program > >The mentioned program and data were thus: > >---------------------- >000000000000000000000000000000000000 - 00 # Projects/PDP-10/pdp10.mem >111111111111111111111111111111111111 # memory image for pdp10.java|.class >010101010101010101010101010101010101 # author Neil Franklin >001100110011001100110011001100110011 # last modification 2001.05.16 >000111000111000111000111000111000111 >000011110000111100001111000011110000 # 00..07 data patterns of YYY >000001111100000111110000011111000001 >000000111111000000111111000000111111 >000000000000000000000000000000000001 - 10 # 10..13 index registers >000000000000000000000000000000000010 >000000000000000000000000000000000100 >000000000000000000000000000000001000 >001110010101010100001010111110110000 # 14..17 data to overwrite >001001010101101101100010110111000111 >100101011101110000000110110111100001 >001111010101000001110110111000000110 >100000000110000000000000000000000000 - 20 # SETZ 14,0 set zero >100000101110100000000000000000000100 # AND I 15,4 and >100001010111000000000000000000000000 # ANDCA M 16,0 and compl acc >100001111110000000000000000000000100 # SETM B 14,4 set mem >100010000110101000000000000000000010 # ANDCM 15,2(10) and compl mem >100010101111001001000000000000000100 # SETA I 16,4(11) set acc >100011010110001010000000000000000000 # XOR M 14,0(12) excl or >100011111110101011000000000000000110 # IOR B 15,6(13) incl or >100100000111010000000000000000000110 - 30 # ANDCB 16,@6 and compl both >100100101110010000000000000000000010 # EQV I 14,@2 equiv >100101010110110000000000000000001000 # SETCA M 15,@10 set compl acc >100101111111010000000000000000001100 # ORCA B 16,@14 or compl acc >100110000110011000000000000000000000 # SETCM 14,@0(10) set compl mem >100110101110111001000000000000000100 # ORCM I 15,@4(11) or compl mem >100111010111011010000000000000000010 # ORCB M 16,@2(12) or compl both >100111111110011011000000000000000101 - 37 # SETO B 14,@5(13) set ones > >OOOOOOOOOAAAAIXXXXYYYYYYYYYYYYYYYYYY # pdp10 instruction format >100FFFFMM # boolean logic instr sub-format >-------------------- > >This program was run using the "BoardScope" interface connected to >the "DeviceSimulator" chip simulation tool. Visible output is the >flipflops of the chip changing while work is going on. > >The program counter is fixed to start up at 20, so this tested all 16 >100ffffmm instructions, and all possible combinations of indexed and >indirect addressing, using the majority of registers. It performs now, >as far as I can see, without any errors. > > >Speed of the present design > >It uses 1 clock pulse for loading an instruction. Each indexing or >indirection costs 1 additional clock. All normal/I/M modes of logic >instructions cost 3 clocks (2 fetch, 1 store). B mode costs 4 clocks >(2 stores). > >So it uses average 4-6 clocks for normal code, which even at an >totally undercritical 24MHz clock (I expect the present top to be >40-80MHz) would give 4-6 MIPS. This is for straight forward code >without any speed optimisations, comparable to when TS-10 was doing >its 0.8 MIPS. > > >Archive of this milestone > >I have archived this milestone as: >http://neil.franklin.ch/Projects/PDP-10/Milestone-20010516/ > >The current work continues in: >http://neil.franklin.ch/Projects/PDP-10/ > >Files for people who want to look/try it out are > >- Logfile - what I am doing at the present time (only in current) >- Time-States - analysis of state machine and control logic >- pdp10.java - Java/JBits source code to compile to pdp10.class >- pdp10.class - compiled Java/JBits for generating pdp10.bit >- pdp10.mem - the program to be loaded into memory when running pdp10.class >- pdp10.bit - compiled design, for running in BS/DS > > >Target for second Milestone > >PDP-10 side will be expanded with: > >- make the instruction decoder more universal for multiple instructions >- same for the controls that drive the data path >- add an further set of instructions, most likely the 011xxxxxx jump/skip > >FPGA side will be expanded with: > >- using BRAMs for an larger 512word memory > >This should take less than the 5.5 months the first milestone took :-) > > >-- >Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ >Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer >- Intellectual Property is Intellectual Robbery -- email: for email delete the thousand and nine ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: FPGA clone status, 1st milestone reached (was Re: Dear Friends....) Date: 11 Jul 2001 23:22:58 +0200 Organization: My own Private Self Lines: 55 Message-ID: <6u7kxfma8d.fsf@chonsp.franklin.ch> References: <4crgftsht3boroqhg89hnp2kg01u16p2df@4ax.com> <3AF87869.9916114B@bartek.dontspamme.net> <6uoft2e6rw.fsf@chonsp.franklin.ch> <3afdc658.6682889@news.m.iinet.net.au> <6ur8xtknhg.fsf@chonsp.franklin.ch> <6u4rulq9lm.fsf_-_@chonsp.franklin.ch> <3b3fb0c4.6901765@news.m.iinet.net.au> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 994886578 890 10.0.3.2 (11 Jul 2001 21:22:58 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 11 Jul 2001 21:22:58 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:5966 Sorry the late answer, I was off-line on holiday for 2 weeks. Am now working through 4000 Usenet posts, after 500 personal mails and 1200 office mails. berd-pee@perthmail.com (Rolie Baldock) writes: > On 16 May 2001 23:15:17 +0200, Neil Franklin > wrote: > > > >Target for second Milestone > > > >PDP-10 side will be expanded with: > > > >- make the instruction decoder more universal for multiple instructions > >- same for the controls that drive the data path Both done now. What I missed there was: make the data path itsself more universal. This one I only discovered while doing designing on holiday. Still needs to be coded. > >- add an further set of instructions, most likely the 011xxxxxx jump/skip 011, 110 and 101 (that order) will go into this milestone. They are all planned out, just need coding. > >FPGA side will be expanded with: > > > >- using BRAMs for an larger 512word memory Only basic look at functioning done so far. But seem easy to use. > >This should take less than the 5.5 months the first milestone took :-) > When can we expect the second milestone to be achieved in the on-going > saga of the FPGA version of the PDP-10? The first took 5.5 months. I hope the second will be shorter. Presently at not quite 2 months. As for how long, I will know that when I arrive there. Any attempt to predict software development times on my part have allways been total faillures, so I do not do that any more! ObURL: http://neil.franklin.ch/Projects/PDP-10/Logfile -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery