Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 31 Dec 2000 22:34:24 +0100 Organization: My own Private Self Lines: 121 Message-ID: <6un1dc9swv.fsf_-_@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978298464 4827 10.0.3.2 (31 Dec 2000 21:34:24 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 31 Dec 2000 21:34:24 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2319 Paul Repacholi writes: > jmfbahciv@aol.com writes: > > > Well, if I could, I'd buy me an XKL. This is really a very One day in the future you may be able to download an clone. > > good exorcise for the kiddies who want to put up a PDP-10 > > system. Just consider me the first field test site. > > I just wish the hardware Logic Design files would fall off > the back of a truck somewhere. They would still be under copyright and so off limits unless you like to be the target of harassment by the legal system. Better just re-develop them. We today have the open source development method to spread development cost among many amateur designers. Linux was re-written from scratch by amateurs, not copied from AT&T Unix. And this way we get just what we want. > I'd say you could fit and entire 30-bit KL into a single FPGA nowdays. The XKL/Toad-1 is hardwarily 2 Xilinx XC4010E-3 FPGAs. They were introduced about 1992-95. On the possibilities of FPGA PDP-10 clones see an thread from October: http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001001_PDP_10_in_an_FPGA_chip > Ah, but could we resist fixing it if we did! That is just what open source is about! The source code is open to everyone. Everyone fixes what they want added. The central developer (called the maintainer) merges the stuff in. We all recieve the sum of all this. Simply start with fixing an empty design file (one that can do nothing = defective). Programming is just debugging an empty program :-). One reason to post this post here is to update information on what has happened here in the last 3 months: I have decided to actually do an FPGA PDP-10 clone. Plans to first do an 8 and/or 11 have been shelved (11 too big an deviation and not really interesting despite historical Unix to run on it, 8 no big usefull stepping stone so it just distracts as I have no 8 code to run). Presently it looks like I will be using an Xilinx Virtex or Spartan-II chip, programming using the JBits tool set. Reason for this choice is that JBits seems to be the only tool that runs 100% on Linux. And JBits only supports these chip families. Most likely is an XC2S200 or XCV200 or XCV300 chip. First on an commercial prototyping board, real later in the project I may go for an custom board. I have since about 1 month installed the tools to program FPGAs and am at the moment learning to use them. Also I have aquired some PDP-10 docs. So I am in the "burried with docs" phase of project specifying. Target will be initially an KI style box (simpler instruction set, and boot from console paper tape (= concealed RS232 to development system) but with the intention of then going on to KL and then on to 30bit addresses like the XKL. Initially I will be doing an LEDs+switches front panel for debugging, but the design should also run without it for users on a small budget (money and time) or with less soldering skills. Processor design will be state machine based (no microcode) like the KI (or in fact later PDP-8s). Initially 10MHz (roughly KL) are to be expected using simplest possible microengine design (D G Conroys PDP-8/X does 10MHz@12bits on cheap XCS10 chips, 12->36bits add 12ns per clock cycle). It looks like 100MHz (ca Jupiter/KC speed) should be attainable in the long run (by using pipelined design, Xilinx claims 200MHz). The complex KL/XKL stuff is intended to be done with trap&emulate [1] (a la IBM 360/44 or 360/95, IIRC the models). Even some of the more complicated KI stuff may end up being trap&emulate, such as: floating point (a la Intel i386/i486SX without i387/i487SX chip), pager (a la MIPS CPUs), console (a la XKL doing KL PDP-11 console in microcode), some IO devices (a la Intel i386SL SMI mode used for emulationg some PC IO on low energy/space notebooks). [1] complex instructions are treated as UUOs, to an 3rd mode lower than MUUOs, I am calling these EmulateUUOs. There simple (= non-EUUO) subset of PDP-10 instructions implement the complex instructions as chip-external "macro-microcode". In the end I want to be able to run my mail/news readers and web site on such an PDP-10 clone per Sept 2004 (40th aniversity of PDP-6 announcement), possibly with an Linux or NetBSD port using Lars' gcc for PDP-10 (his site once said something of porting Linux). This project is open source, right from the beginning. Everything goes online the day I write it. Download, try, use, crash (yes, non noticed crashes also go online :-)), send me your contributions. The code will be under the most open license: public domain. The project web site is up since today: http://neil.franklin.ch/Projects/PDP-10/ At the moment there is mainly my activities log file there: http://neil.franklin.ch/Projects/PDP-10/Logfile This file documents what I am checking through at the moment, what docs I have got (incl URLs), etc. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Mon, 01 Jan 01 10:39:41 GMT Organization: UltraNet Communications, Inc. Lines: 24 Message-ID: <92pqre$8ah$2@bob.news.rcn.net> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> X-Trace: UmFuZG9tSVazk+hgDvtl2NKZtDfbpf5dpFh2KiBqRCl26RS3PE/YOf6ns3DpBeoo X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Jan 2001 11:49:02 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-216-10 Xref: chonsp.franklin.ch alt.sys.pdp10:2325 In article <3A4F9C13.4E9C02C3@trailing-edge.com>, Tim Shoppa wrote: >Neil Franklin wrote: >> In the end I want to be able to run my mail/news readers and web site >> on such an PDP-10 clone per Sept 2004 (40th aniversity of PDP-6 >> announcement) > >That would be a fine goal, especially as many of the better >mail readers were originally developed on -10's. > >> possibly with an Linux or NetBSD port using Lars' gcc >> for PDP-10 (his site once said something of porting Linux). > >This I don't understand. I don't understand either. Is he doing a hardware design or just another software layer design? And if he's doing a hardware design, please or please pretty please do NOT preclude SMP. /BAH Subtract a hundred and four for e-mail. ###### Message-ID: <3A4D30BB.8E2B0B55@jetnet.ab.ca> Date: Fri, 29 Dec 2000 17:47:55 -0700 From: Ben Franchuk X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.18 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.53 X-Trace: 1 Jan 2001 02:36:36 -0700, 207.153.6.53 Organization: OA Internet Lines: 27 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!logbridge.uoregon.edu!newsfeed.direct.ca!look.ca!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.53 Xref: chonsp.franklin.ch alt.sys.pdp10:2323 Paul Repacholi wrote: > > Neil Franklin writes: > > > > I'd say you could fit and entire 30-bit KL into a single FPGA nowdays. > > > > The XKL/Toad-1 is hardwarily 2 Xilinx XC4010E-3 FPGAs. They were > > introduced about 1992-95. > > Should be able to. They go to 1 million gates now. IO pins is normally > the wall you hit with them. > > From scratch would be hairy, the U-code changed for 10 vs 20, > and ITS used it's own. Don't know what Stanford used. So it really > needs to be at the u-machine level, not just the ISP. I like the idea of bunch of low cost FPGA's rather than 1 BIG chip. Some how having to load both micro-code and FPGA logic from boot roms does not have a nice feel.Anti-fuse FPGA's (fuse programed) are better at random logic than the Ram based ones. The micro code may best be changed to prevent fewer problems with copywrites and stuff like that. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk ###### From: berd_kalamunda@techemail.com (Rolie Baldock) Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Sun, 31 Dec 2000 22:38:34 GMT Message-ID: <3a4fb421.4306449@news.m.iinet.net.au> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> X-Newsreader: Forte Free Agent 1.11/16.235 Lines: 137 NNTP-Posting-Host: 203.59.69.200 X-Trace: news.iinet.net.au 978302103 28114 emut7d@203.59.69.200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!skynet.be!newsfeed.iinet.net.au!news.iinet.net.au!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2327 Hello Neil, Great project, hope you make it. Will be eagerly looking at developments. I would really love to have a machine where the code and the symbol table were in read only memory. I just crashed a QuickBASIC program through some activity in an assembly language subroutine on the PC and the symbol table seems to have inadvertantly got damaged which makes debugging with CodeVIEW difficult. I would prefer DDT-10 anyway. On 31 Dec 2000 22:34:24 +0100, Neil Franklin wrote: >Paul Repacholi writes: > >> jmfbahciv@aol.com writes: >> >> > Well, if I could, I'd buy me an XKL. This is really a very > >One day in the future you may be able to download an clone. > > >> > good exorcise for the kiddies who want to put up a PDP-10 >> > system. Just consider me the first field test site. >> >> I just wish the hardware Logic Design files would fall off >> the back of a truck somewhere. > >They would still be under copyright and so off limits unless you like >to be the target of harassment by the legal system. > >Better just re-develop them. We today have the open source development >method to spread development cost among many amateur designers. Linux >was re-written from scratch by amateurs, not copied from AT&T Unix. And >this way we get just what we want. > > >> I'd say you could fit and entire 30-bit KL into a single FPGA nowdays. > >The XKL/Toad-1 is hardwarily 2 Xilinx XC4010E-3 FPGAs. They were >introduced about 1992-95. > >On the possibilities of FPGA PDP-10 clones see an thread from October: > >http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001001_PDP_10_in_an_FPGA_chip > > >> Ah, but could we resist fixing it if we did! > >That is just what open source is about! The source code is open to >everyone. Everyone fixes what they want added. The central developer >(called the maintainer) merges the stuff in. We all recieve the sum >of all this. Simply start with fixing an empty design file (one that >can do nothing = defective). Programming is just debugging an empty >program :-). > > >One reason to post this post here is to update information on what has >happened here in the last 3 months: > >I have decided to actually do an FPGA PDP-10 clone. Plans to first do >an 8 and/or 11 have been shelved (11 too big an deviation and not >really interesting despite historical Unix to run on it, 8 no big >usefull stepping stone so it just distracts as I have no 8 code to run). > > >Presently it looks like I will be using an Xilinx Virtex or Spartan-II >chip, programming using the JBits tool set. Reason for this choice is >that JBits seems to be the only tool that runs 100% on Linux. And JBits >only supports these chip families. Most likely is an XC2S200 or XCV200 >or XCV300 chip. First on an commercial prototyping board, real later in >the project I may go for an custom board. > >I have since about 1 month installed the tools to program FPGAs and am >at the moment learning to use them. Also I have aquired some PDP-10 >docs. So I am in the "burried with docs" phase of project specifying. > > >Target will be initially an KI style box (simpler instruction set, and >boot from console paper tape (= concealed RS232 to development system) >but with the intention of then going on to KL and then on to 30bit >addresses like the XKL. Initially I will be doing an LEDs+switches >front panel for debugging, but the design should also run without it >for users on a small budget (money and time) or with less soldering >skills. > >Processor design will be state machine based (no microcode) like the KI >(or in fact later PDP-8s). Initially 10MHz (roughly KL) are to be >expected using simplest possible microengine design (D G Conroys PDP-8/X >does 10MHz@12bits on cheap XCS10 chips, 12->36bits add 12ns per clock >cycle). It looks like 100MHz (ca Jupiter/KC speed) should be attainable >in the long run (by using pipelined design, Xilinx claims 200MHz). > > >The complex KL/XKL stuff is intended to be done with trap&emulate [1] >(a la IBM 360/44 or 360/95, IIRC the models). Even some of the more >complicated KI stuff may end up being trap&emulate, such as: floating >point (a la Intel i386/i486SX without i387/i487SX chip), pager (a la >MIPS CPUs), console (a la XKL doing KL PDP-11 console in microcode), >some IO devices (a la Intel i386SL SMI mode used for emulationg some >PC IO on low energy/space notebooks). > >[1] complex instructions are treated as UUOs, to an 3rd mode lower >than MUUOs, I am calling these EmulateUUOs. There simple (= non-EUUO) >subset of PDP-10 instructions implement the complex instructions as >chip-external "macro-microcode". > >In the end I want to be able to run my mail/news readers and web site >on such an PDP-10 clone per Sept 2004 (40th aniversity of PDP-6 >announcement), possibly with an Linux or NetBSD port using Lars' gcc >for PDP-10 (his site once said something of porting Linux). > > >This project is open source, right from the beginning. Everything goes >online the day I write it. Download, try, use, crash (yes, non noticed >crashes also go online :-)), send me your contributions. The code will >be under the most open license: public domain. > > >The project web site is up since today: > >http://neil.franklin.ch/Projects/PDP-10/ > >At the moment there is mainly my activities log file there: > >http://neil.franklin.ch/Projects/PDP-10/Logfile > >This file documents what I am checking through at the moment, what >docs I have got (incl URLs), etc. > > >-- >Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ >Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic --Rolie Baldock. email: ###### User-Agent: Microsoft-Outlook-Express-Macintosh-Edition/5.02.2022 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) From: David G Conroy Newsgroups: alt.sys.pdp10 Message-ID: References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3a4fb421.4306449@news.m.iinet.net.au> Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 9 Date: Sun, 31 Dec 2000 22:47:33 GMT NNTP-Posting-Host: 207.21.131.126 X-Complaints-To: abuse@verio.net X-Trace: sjc-read.news.verio.net 978302853 207.21.131.126 (Sun, 31 Dec 2000 22:47:33 GMT) NNTP-Posting-Date: Sun, 31 Dec 2000 22:47:33 GMT Organization: Verio Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!kanja.arnes.si!news-hub.siol.net!news-out.cwix.com!newsfeed.cwix.com!sjc-peer.news.verio.net!news.verio.net!sjc-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2321 The critical path in the pdp-8/x is much longer than the 12-bit add. It goes major/minor state through some logic which computes the carry into the add through 12 bits of ripple carry through the rotate muxs and into the L-AC. If there was a flipflop right at the carry inject point (so the logic which computes the carry input runs in the previous cycle), and the 12-bit ripple add was replaced by 3 6-bit adders in a carry-select configuration, the thing would run almost twice as fast. But I didn't care. ###### Message-ID: <3A4F9C13.4E9C02C3@trailing-edge.com> Date: Sun, 31 Dec 2000 20:50:27 -0400 From: Tim Shoppa Organization: Trailing Edge Technology X-Mailer: Mozilla 3.03Gold (X11; I; OpenVMS V7.2 AlphaServer 1200 5/533 4MB) MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 22 NNTP-Posting-Host: 63.73.218.130 X-Trace: reader0.news.uu.net 978313827 12379 63.73.218.130 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.wirehub.nl!surfnet.nl!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!wn4feed!worldnet.att.net!198.6.0.7!uunet!ash.uu.net!dfw.uu.net!ffx.uu.net!spool0.news.uu.net!reader0.news.uu.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2326 Neil Franklin wrote: > In the end I want to be able to run my mail/news readers and web site > on such an PDP-10 clone per Sept 2004 (40th aniversity of PDP-6 > announcement) That would be a fine goal, especially as many of the better mail readers were originally developed on -10's. > possibly with an Linux or NetBSD port using Lars' gcc > for PDP-10 (his site once said something of porting Linux). This I don't understand. Here we have TOPS-10 and TOPS-20, without a doubt two of the finest operating systems ever produced, available under the terms of the 36-bit hobbyist license (assuming that what you'll be using them for fall under its limitations). The programming tools available are rich, full-featured, and well-developed, and (at least with TOPS-20) the user interface is powerful and easy to use. Why in the world would you want to run a Unix-type OS, with its baggage of primitive tools, awkward interfaces, and overall lack of functionality? Tim. ###### From: Arthur Krewat Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Organization: Kilonet.net Lines: 25 Message-ID: <3A4FD667.CF96DF2D@bartek.dontspamme.net> References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (X11; I; SunOS 5.8 i86pc) X-Accept-Language: en Date: Mon, 01 Jan 2001 01:00:39 GMT NNTP-Posting-Host: 167.206.68.16 X-Trace: news02.optonline.net 978310839 167.206.68.16 (Sun, 31 Dec 2000 20:00:39 EST) NNTP-Posting-Date: Sun, 31 Dec 2000 20:00:39 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!nntp.flash.net!cyclone-sjo1.usenetserver.com!news-out.usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2331 Neil Franklin wrote: > > One reason to post this post here is to update information on what has > happened here in the last 3 months: > > I have decided to actually do an FPGA PDP-10 clone. Plans to first do > an 8 and/or 11 have been shelved (11 too big an deviation and not > really interesting despite historical Unix to run on it, 8 no big > usefull stepping stone so it just distracts as I have no 8 code to run). > > Presently it looks like I will be using an Xilinx Virtex or Spartan-II > chip, programming using the JBits tool set. Reason for this choice is > that JBits seems to be the only tool that runs 100% on Linux. And JBits > only supports these chip families. Most likely is an XC2S200 or XCV200 > or XCV300 chip. First on an commercial prototyping board, real later in > the project I may go for an custom board. I have access to some exceptional Xilinx talent as well as licenses for software (lmgrd). If you need any help, please feel free to email me. I can donate time and materials for web hosting, mailing lists, etc. tell me what you need from me :) art k. ###### User-Agent: Microsoft-Outlook-Express-Macintosh-Edition/5.02.2022 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) From: David G Conroy Newsgroups: alt.sys.pdp10 Message-ID: References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4FD667.CF96DF2D@bartek.dontspamme.net> Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 5 Date: Mon, 01 Jan 2001 01:27:12 GMT NNTP-Posting-Host: 207.21.131.91 X-Complaints-To: abuse@verio.net X-Trace: sjc-read.news.verio.net 978312432 207.21.131.91 (Mon, 01 Jan 2001 01:27:12 GMT) NNTP-Posting-Date: Mon, 01 Jan 2001 01:27:12 GMT Organization: Verio Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-peer.gip.net!news.gsl.net!gip.net!news-out.usenetserver.com!sjc-peer.news.verio.net!news.verio.net!sjc-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2322 I'm an expert on the 3K/4K architectures as well. Feel free to e-mail me as well. dgc ###### Sender: prep@k9.prep.synonet.com Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> From: Paul Repacholi Date: 01 Jan 2001 11:05:55 +0800 Message-ID: <8766k02cq4.fsf@k9.prep.synonet.com> Lines: 21 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 196.d02.pe.iqnet.net.au X-Trace: 1 Jan 2001 11:24:56 +0800, 196.d02.pe.iqnet.net.au Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!news.good.net!feedwest.news.agis.net!agis!feed-out.newsfeeds.com!newsfeeds.com!feed.newsfeeds.com!newsfeeds.com!newsfeed.iinet.net.au!news.waia.asn.au!usenet.per.paradox.net.au!127.0.0.1!nobody Xref: chonsp.franklin.ch alt.sys.pdp10:2328 Tim Shoppa writes: > This I don't understand. Here we have TOPS-10 and TOPS-20, > without a doubt two of the finest operating systems ever produced, > available under the terms of the 36-bit hobbyist license (assuming that > what you'll be using them for fall under its limitations). The > programming tools available are rich, full-featured, and well-developed, > and (at least with TOPS-20) the user interface is powerful and easy to > use. Why in the world would you want to run a Unix-type OS, with > its baggage of primitive tools, awkward interfaces, and overall lack of > functionality? If you wanted to do that, why wouldn't you run ITS? ( duck... ) BTW Tim, mail incoming... -- Paul Repacholi 1 Crescent Rd., +61 (08) 9257-1001 Kalamunda. West Australia 6076 Raw, Cooked or Well-done, it's all half baked. ###### Sender: prep@k9.prep.synonet.com Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> From: Paul Repacholi Date: 01 Jan 2001 11:14:03 +0800 Message-ID: <871yuo2cck.fsf@k9.prep.synonet.com> Lines: 23 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 196.d02.pe.iqnet.net.au X-Trace: 1 Jan 2001 11:24:58 +0800, 196.d02.pe.iqnet.net.au Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newshub2.rdc1.sfba.home.com!news.home.com!cyclone-sjo1.usenetserver.com!news-out.usenetserver.com!newsxfer.interpacket.net!feed-out.newsfeeds.com!newsfeeds.com!feed.newsfeeds.com!newsfeeds.com!newsfeed.iinet.net.au!news.waia.asn.au!usenet.per.paradox.net.au!127.0.0.1!nobody Xref: chonsp.franklin.ch alt.sys.pdp10:2329 Neil Franklin writes: > > I'd say you could fit and entire 30-bit KL into a single FPGA nowdays. > > The XKL/Toad-1 is hardwarily 2 Xilinx XC4010E-3 FPGAs. They were > introduced about 1992-95. Should be able to. They go to 1 million gates now. IO pins is normally the wall you hit with them. From scratch would be hairy, the U-code changed for 10 vs 20, and ITS used it's own. Don't know what Stanford used. So it really needs to be at the u-machine level, not just the ISP. BTW, does anyone have a copy of Vol II of the Tops HArdware reference, the IO section? I've never seen one. -- Paul Repacholi 1 Crescent Rd., +61 (08) 9257-1001 Kalamunda. West Australia 6076 Raw, Cooked or Well-done, it's all half baked. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 01 Jan 2001 16:32:06 +0100 Organization: My own Private Self Lines: 48 Message-ID: <6uae9bnv9l.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978363126 1340 10.0.3.2 (1 Jan 2001 15:32:06 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 1 Jan 2001 15:32:06 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2334 jmfbahciv@aol.com writes: > I don't understand either. Is he doing a hardware design or > just another software layer design? Something in between that does not have an -ware name. As far as an outside observer (not looking into the FPGA chip) would see it, it will look just like I made an custom designed chip. But actually FPGA chips split the hard-/software split into 3 levels: - hardware (is sub-split) - actual chip (mass manufactured like processors) - chip configuration (bits, programmed, but wires the chip, not executed) - software (normal software that gets executed) What I will be doing is at chip configuration level (at least for the initial KI, some of the complex KL extensions will be real software (written in PDP-10 macro)). At this level the underlying chip appears as an grid of 16*1bit RAMs, single flipflops, muxes in between them, a few 256*16bit RAMs allong the edges, and all interconnected by an grid of interconnect lines covered by an sea of switch transistors. These are all configured (bits into the RAMs and FFs, switches opened) by an "second layer" in the chip consising of just an big RAM. Strictly working with FPGAs is programming, i.e. generating an file full of bits. But this file is intended for loading into the "second layer", after which the hardware of the "first layer" is "shaped" to work as if it had been designed as a custon chip. > And if he's doing a > hardware design, please or please pretty please do NOT > preclude SMP. That should be possible, with an large enough FPGA chip. I think an XCV1000 should have enough room for 4 processor SMP. And anyway, unlike real fixed hardware an FPGA can have SMP added just as easy as an emulator can, so long you do not run out of FPGA space (thats like running out of memory in a program on an non-virtual memory machine). -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 01 Jan 2001 16:50:24 +0100 Organization: My own Private Self Lines: 73 Message-ID: <6u7l4fnuf3.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978364224 1447 10.0.3.2 (1 Jan 2001 15:50:24 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 1 Jan 2001 15:50:24 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2335 Tim Shoppa writes: > Neil Franklin wrote: > > In the end I want to be able to run my mail/news readers and web site > > on such an PDP-10 clone per Sept 2004 (40th aniversity of PDP-6 > > announcement) > > That would be a fine goal, especially as many of the better > mail readers were originally developed on -10's. I today use the RMAIL mailer and GNUS newsreader that are part of Emacs. That came to Linux via the Lisp Machines from PDP-10/ITS/TECO. So I already have an soft spot there. What is the support for newer mail protocols like PO3 and IMAP4 like in TOPS mail and news readers? > > possibly with an Linux or NetBSD port using Lars' gcc > > for PDP-10 (his site once said something of porting Linux). > > This I don't understand. Here we have TOPS-10 and TOPS-20, > without a doubt two of the finest operating systems ever produced, Looks like I will be looking into these. Note that I will have to use TOPS (I assume TOPS-10) for the KI, so it will have time until 30bit address KL is running (below that a Linux port is not possible) to convince me to change to it. P.S. My previous background OS-wise is: MS-DOS 3.3-6.0 (retch), Windows 3.0-3.11 (don't mention it), VMS 5.5-6.0 (I know its reputation here) and Linux 1.0.8-2.2.13 (what I use at home), Irix 5.3-6.5 (what I use at work), Solaris 2.5-2.6 (also work). Of these Linux is the best I have found so far. If I find something better, it has a good chance to grab me. What is TOPS-10 or 20 support for graphics like? Is there something like X that makes an graphical web browser possible? I know that X will display onto any Unix, PCs, Macs, and even VMS. Such graphics will be crucial for me to adapt an OS for everyday work. That is why I said "possibly" with Linux, it is also possible that it will be with one of the TOPSes. Generally: how much has TOPS-10 or 20 been kept uptodate with developments since DEC stopped making 10s? > available under the terms of the 36-bit hobbyist license (assuming that > what you'll be using them for fall under its limitations). I have not read the license. But I assume I will fit in. Hobby use. Playing around. Personal email, surfing and website. > programming tools available are rich, full-featured, and well-developed, > and (at least with TOPS-20) the user interface is powerful and easy to > use. Am I getting it right that TOPS-20 is KL and above? So I assume I will be looking into both TOPSes. > Why in the world would you want to run a Unix-type OS, with > its baggage of primitive tools, awkward interfaces, and overall lack of > functionality? With the OSes I knoe up until now, Linux is actually the one with the best functionality. If one of the TOPSes can even beat that, even better. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 01 Jan 2001 17:10:59 +0100 Organization: My own Private Self Lines: 54 Message-ID: <6u1yunntgs.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978365460 1551 10.0.3.2 (1 Jan 2001 16:11:00 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 1 Jan 2001 16:11:00 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2336 Paul Repacholi writes: > Neil Franklin writes: > > > > I'd say you could fit and entire 30-bit KL into a single FPGA nowdays. > > > > The XKL/Toad-1 is hardwarily 2 Xilinx XC4010E-3 FPGAs. They were > > introduced about 1992-95. > > Should be able to. They go to 1 million gates now. That is user designs with the complexity of 1 mio gates. The biggest chips today are implemented with 10 mio gates / 40 mio transistors. I am looking at fairly cheap 100'000 user gates chips for the beginning, particularly the XC2S200 at $50. > IO pins is normally > the wall you hit with them. Yes. That I have noticed. Actually one can get up to 1000 pins, but anything above about 250 pins is in BGA or even FBGA cases. So totally off the map for someone who may one day do an own board. 100-250 pins at least are TQFP cases. All them nice 100-600 pin PGAs seem to not be offered for the newer chips. > From scratch would be hairy, the U-code changed for 10 vs 20, > and ITS used it's own. Don't know what Stanford used. So it really > needs to be at the u-machine level, not just the ISP. The problem with any u-machine level design is that I can not fit the 2048 x 96 bit (KL10-D and above) u-code memory inside the FPGA and I do not have the pins to do it external without losing on pins for wide RAM (72bit) or IO devices. That is why I will be aiming for an KI like state machine (non-u-code) design and then implementing the complex (X)KL functions as a type of UUOs. > BTW, does anyone have a copy of Vol II of the Tops HArdware > reference, the IO section? I've never seen one. IO device (and "7" instructions) manuals are one of the places I also still have an big hole. But I have not really gone through all the web sites out there, that is still part of the "reading up" phase I am now in. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### From: Arthur Krewat Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Organization: Kilonet.net Lines: 24 Message-ID: <3A509D31.7CA23886@bartek.dontspamme.net> References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (X11; I; SunOS 5.8 i86pc) X-Accept-Language: en Date: Mon, 01 Jan 2001 15:10:36 GMT NNTP-Posting-Host: 167.206.68.16 X-Trace: news02.optonline.net 978361836 167.206.68.16 (Mon, 01 Jan 2001 10:10:36 EST) NNTP-Posting-Date: Mon, 01 Jan 2001 10:10:36 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newshub2.rdc1.sfba.home.com!news.home.com!cyclone-sjo1.usenetserver.com!news-out.usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2347 jmfbahciv@aol.com wrote: > > >That would be a fine goal, especially as many of the better > >mail readers were originally developed on -10's. > > > >> possibly with an Linux or NetBSD port using Lars' gcc > >> for PDP-10 (his site once said something of porting Linux). > > > >This I don't understand. > > > I don't understand either. Is he doing a hardware design or > just another software layer design? And if he's doing a > hardware design, please or please pretty please do NOT > preclude SMP. He means that once he has a running PDP-10, he wants to port Linux or NetBSD to it using the PDP-10 GCC that Lars is going to work on. Noble effort. As mentioned before, if you need any help, please ask! art k. ###### User-Agent: Microsoft-Outlook-Express-Macintosh-Edition/5.02.2022 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) From: David G Conroy Newsgroups: alt.sys.pdp10 Message-ID: References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 33 Date: Mon, 01 Jan 2001 18:46:39 GMT NNTP-Posting-Host: 207.21.131.71 X-Complaints-To: abuse@verio.net X-Trace: sjc-read.news.verio.net 978374799 207.21.131.71 (Mon, 01 Jan 2001 18:46:39 GMT) NNTP-Posting-Date: Mon, 01 Jan 2001 18:46:39 GMT Organization: Verio Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.cwix.com!sjc-peer.news.verio.net!news.verio.net!sjc-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2337 > The problem with any u-machine level design is that I can not fit the > 2048 x 96 bit (KL10-D and above) u-code memory inside the FPGA and I > do not have the pins to do it external without losing on pins for wide > RAM (72bit) or IO devices. > > That is why I will be aiming for an KI like state machine (non-u-code) > design and then implementing the complex (X)KL functions as a type of > UUOs. You should not assume that you need to have a small horizontal microstore just because the KL10 did. Times change, and you have raw circuit speed on your side, both in the form of logic, and in the form of large and cheap rams (say 32Kx8-12ns for about $2.50, quantity 1). In the KL10's time executing 30 million microwords a second, or decoding instructions by doing a 512-way dispatch into 32-word slots in a 16K control store, was a lot less practical than it is today. Doing SMP is more complicated that finding space for the processors. The processors, I/O devices, and memory have to be designed so that they implement the correct multiprocessing model (for example, exactly when do operations on one processor and/or I/O device become observable at other processors and/or I/O devices, and which operations are guaranteed to be atomic). I can describe the model for a lot of machines, but not for the '10 (although I'm sure someone who reads this can). Retrofitting this kind of stuff is really really ugly. SMP makes doing parts of the architecture in software a little tricky too (it's the same problem as doing SMP PALCODE on ALPHA) because you need to deal with the per-processor data. dgc ###### From: berd_kalamunda@techemail.com (Rolie Baldock) Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Mon, 01 Jan 2001 22:37:40 GMT Message-ID: <3a510463.3916427@news.m.iinet.net.au> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> X-Newsreader: Forte Free Agent 1.11/16.235 Lines: 74 NNTP-Posting-Host: 203.59.69.73 X-Trace: news.iinet.net.au 978388454 30426 emut7d@203.59.69.73 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!skynet.be!newsfeed.iinet.net.au!news.iinet.net.au!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2343 Hello Neil, Were I taking on your PDP-10 project I would not make it a 36 bit architecture but a 96 bit architecture with many more fast registers and 48 bit address field in the RH of the word. Yes I know it wold not be a PDP-10 but times change and the advantages would be ASTRONOMIC. The 96 bit word would be very efficient in the 8bit byte area and the 3bit tri-colour area of the screen. Phased routines running in registers would be greatly enhanced.....etc...etc. Once the logic for the E-Box is finalised it should not be too hard to upgrade the size of the word. Regards, On 01 Jan 2001 17:10:59 +0100, Neil Franklin wrote: >Paul Repacholi writes: > >> Neil Franklin writes: >> >> > > I'd say you could fit and entire 30-bit KL into a single FPGA nowdays. >> > >> > The XKL/Toad-1 is hardwarily 2 Xilinx XC4010E-3 FPGAs. They were >> > introduced about 1992-95. >> >> Should be able to. They go to 1 million gates now. > >That is user designs with the complexity of 1 mio gates. The biggest >chips today are implemented with 10 mio gates / 40 mio transistors. > >I am looking at fairly cheap 100'000 user gates chips for the >beginning, particularly the XC2S200 at $50. > > >> IO pins is normally >> the wall you hit with them. > >Yes. That I have noticed. Actually one can get up to 1000 pins, but >anything above about 250 pins is in BGA or even FBGA cases. So totally >off the map for someone who may one day do an own board. 100-250 pins >at least are TQFP cases. All them nice 100-600 pin PGAs seem to not be >offered for the newer chips. > > >> From scratch would be hairy, the U-code changed for 10 vs 20, >> and ITS used it's own. Don't know what Stanford used. So it really >> needs to be at the u-machine level, not just the ISP. > >The problem with any u-machine level design is that I can not fit the >2048 x 96 bit (KL10-D and above) u-code memory inside the FPGA and I >do not have the pins to do it external without losing on pins for wide >RAM (72bit) or IO devices. > >That is why I will be aiming for an KI like state machine (non-u-code) >design and then implementing the complex (X)KL functions as a type of >UUOs. > > >> BTW, does anyone have a copy of Vol II of the Tops HArdware >> reference, the IO section? I've never seen one. > >IO device (and "7" instructions) manuals are one of the places I also >still have an big hole. But I have not really gone through all the web >sites out there, that is still part of the "reading up" phase I am now >in. > > >-- >Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ >Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic --Rolie Baldock. email: ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 02 Jan 2001 01:04:05 +0100 Organization: My own Private Self Lines: 36 Message-ID: <6uitnykefe.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <3A509D31.7CA23886@bartek.dontspamme.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978393845 630 10.0.3.2 (2 Jan 2001 00:04:05 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Jan 2001 00:04:05 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2353 Arthur Krewat writes: > jmfbahciv@aol.com wrote: > > > >> possibly with an Linux or NetBSD port using Lars' gcc > > >> for PDP-10 (his site once said something of porting Linux). > > > > > >This I don't understand. > > > > I don't understand either. Is he doing a hardware design or > > just another software layer design? And if he's doing a > He means that once he has a running PDP-10, he wants to port > Linux or NetBSD to it using the PDP-10 GCC that Lars is > going to work on. -> possibly <- port Linux or NetBSD. It may be that after using TOPS-10 and TOPS-20 I decide I like them and instead try to port some stuff (XFree, Mozilla, Apache) to one of them. What software I will chose to get running on it is still completely open. The only things I regard as fixed is: - TOPS-10 for the KI, as both TOPS-20 and Linux or NetBSD will not fit into 256kword. - something for use as daily prodictive home system with target Sep 2004. > Noble effort. As mentioned before, if you need any help, please > ask! I sure will. Both PDP-10 and FPGA questions, here and in c.a.f. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 02 Jan 2001 01:37:46 +0100 Organization: My own Private Self Lines: 90 Message-ID: <6ug0j2kcv9.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978395867 1157 10.0.3.2 (2 Jan 2001 00:37:47 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Jan 2001 00:37:47 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2354 David G Conroy writes: > > The problem with any u-machine level design is that I can not fit the > > 2048 x 96 bit (KL10-D and above) u-code memory inside the FPGA and I > > do not have the pins to do it external without losing on pins for wide > > RAM (72bit) or IO devices. > > You should not assume that you need to have > a small horizontal microstore just because the KL10 did. Small would only be needed for u-code inside the FPGA, but there is not enough space there anyway. The chips I am aiming at (Virtex xcv150-300) have 12-16 4kbit blocks internally. That is not enough for any u-code. There exist enlarged memory versions, but the tools I have do not support them. > and you have raw circuit speed on your side, both in the form That is sure. The original PDP-10 would have licked their fingers for todays chip speeds. > of logic, and in the form of large and cheap rams (say 32Kx8-12ns for about > $2.50, quantity 1). In the KL10's time executing 30 million microwords > a second, or decoding instructions by doing a 512-way dispatch > into 32-word slots in a 16K control store, was a lot less practical than > it is today. Interesting technique. Throw address space at it. The Z80mu Z80 emulator for 8088 PCs used that method (256 16byte slots). For external, once the pins and speed are sacrificed, I can go to any size that modern SRAMs allow. That is currently 8Mbit (1Mx8bit) in async SRAMs and 16Mbit (512k*36bit) in ZBT SRAMs (expensive). At the moment I am planing using 5 1Mx8bit for 1Mword memory. The problem I have with external u-code is more the width of the u-instructions and getting them back into the FPGA. Depending on the chip package I have 140 (TQFP208) to 160 (TQFP240) user IO pins. From these I need to use about 60 for memory. Then quite a few for IO. > Doing SMP is more complicated that finding space for the > processors. Sure. But chip space is the only "hard" limit. The rest ist design work. Costs time, but is do-able. > The processors, I/O devices, and memory have to be designed > so that they implement the correct multiprocessing model (for example, > exactly when do operations on one processor and/or I/O device become > observable at other processors and/or I/O devices, Where the PDP-10 with its simple instructions help. In those I have so far looked at (KI) most only modify one memory word. And the others (block moves) have an defined interruptable behaviour. Some of the KL stuff looks complex, but that will be cut up to multiple simple instructions. One of the advantages of this technique. > and which > operations are guaranteed to be atomic). What did DEC define here? They had the same problem for Jupiter. Or is that all among the lost stuff? > sure someone who reads this can). Retrofitting this kind of stuff > is really really ugly. We will see when I get so far. Good job I am fairly good at biting the bullet and retrofitting changes through an entire project, even if that means a long amount of drudge work. > SMP makes doing parts of the > architecture in software a little tricky too (it's the same problem > as doing SMP PALCODE on ALPHA) because you need to deal with > the per-processor data. Thanks for the tip. Something to look out for. Suggests this code using an per processor internal memory. Or an per processor base pointer (a la KA per process base). -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 02 Jan 2001 01:47:44 +0100 Organization: My own Private Self Lines: 28 Message-ID: <6ud7e6kcen.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3a510463.3916427@news.m.iinet.net.au> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978396464 1157 10.0.3.2 (2 Jan 2001 00:47:44 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Jan 2001 00:47:44 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2355 berd_kalamunda@techemail.com (Rolie Baldock) writes: > Were I taking on your PDP-10 project I would not make it a 36 bit > architecture but a 96 bit architecture with many more fast registers > and 48 bit address field in the RH of the word. Yes I know it wold not > be a PDP-10 Which would sort of negate the projects purpose. I am in it for historical interest. > but times change and the advantages would be ASTRONOMIC. > The 96 bit word would be very efficient in the 8bit byte area and the > 3bit tri-colour area of the screen. Phased routines running in > registers would be greatly enhanced.....etc...etc. > Once the logic for the E-Box is finalised it should not be too hard to > upgrade the size of the word. If you are interested in such an processor design, go and have a look at the F-CPU project at http://www.f-cpu.org/. They are doing an 64 register auto-adapting n*32bit (initially n=2) width SIMD style design. Including aiming for mass produced ASIC. Jokingly called the "Merced killer". Looks like quite a big project. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> X-Disclaimer: Everything I write is false. Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 01 Jan 2001 16:34:55 -0800 Message-ID: Lines: 15 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 1 Jan 2001 16:38:11 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.mathworks.com!news.sgi.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch alt.sys.pdp10:2367 David G Conroy writes: > You should not assume that you need to have > a small horizontal microstore just because the KL10 did. Times change, > and you have raw circuit speed on your side, both in the form > of logic, and in the form of large and cheap rams (say 32Kx8-12ns for about > $2.50, quantity 1). In the KL10's time executing 30 million microwords > a second, or decoding instructions by doing a 512-way dispatch > into 32-word slots in a 16K control store, was a lot less practical than > it is today. I'm not sure I understand what you're suggesting. That is exactly how the KL10 was designed back in 1974 or so. So are you saying that since it is more practical to do it that way now, that it's reasonable to use that style of design now? Or are you saying that someone should just implement the KL10 logic exactly? ###### User-Agent: Microsoft-Outlook-Express-Macintosh-Edition/5.02.2022 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) From: David G Conroy Newsgroups: alt.sys.pdp10 Message-ID: References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 38 Date: Tue, 02 Jan 2001 01:45:54 GMT NNTP-Posting-Host: 207.21.131.84 X-Complaints-To: abuse@verio.net X-Trace: sjc-read.news.verio.net 978399954 207.21.131.84 (Tue, 02 Jan 2001 01:45:54 GMT) NNTP-Posting-Date: Tue, 02 Jan 2001 01:45:54 GMT Organization: Verio Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.media.kyoto-u.ac.jp!newsfeed.mesh.ad.jp!sjc-peer.news.verio.net!news.verio.net!sjc-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2356 >> You should not assume that you need to have >> a small horizontal microstore just because the KL10 did. Times change, >> and you have raw circuit speed on your side, both in the form >> of logic, and in the form of large and cheap rams (say 32Kx8-12ns for about >> $2.50, quantity 1). In the KL10's time executing 30 million microwords >> a second, or decoding instructions by doing a 512-way dispatch >> into 32-word slots in a 16K control store, was a lot less practical than >> it is today. > > I'm not sure I understand what you're suggesting. That is exactly how > the KL10 was designed back in 1974 or so. So are you saying that since > it is more practical to do it that way now, that it's reasonable to use > that style of design now? Or are you saying that someone should just > implement the KL10 logic exactly? I don't actually understand the low-level details of the KL, so I just took the "2Kx96" description of it's control store as the truth, and if it *is* the truth, it didn't seem compatible with direct dispatch on a 9-bit opcode field, although it's possible (with that much parallelism in space, 1 or 2 word per-instruction flows are not unreasonable). With a control store that small I would have guessed that a similar technique, where the opcode was used to index a map ram, which contained a dispatch pc into the control store, and (usually) some bits which would be used to control the data path, was used. But I'm happy to be corrected. I was actually saying that Neil should look very hard at the technology he is planning to use, and ask himself the question "what realization does this technology encourage", because it may not be the same as the ones used years ago by the original PDP-10 designers. They didn't have cheap 32Kx8 12ns SRAMS and 8Mx8 133MHz SDRAMS in their toolkit, and they didn't have to deal with FPGA interconnect delay, to name but a few of the changes in technology. ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> X-Disclaimer: Everything I write is false. Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 01 Jan 2001 18:02:36 -0800 Message-ID: Lines: 14 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 1 Jan 2001 18:05:53 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!surfnet.nl!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.mathworks.com!news.sgi.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch alt.sys.pdp10:2365 David G Conroy writes: > I don't actually understand the low-level details of the KL, > so I just took the "2Kx96" description of it's control store as the truth, > and if it *is* the truth, it didn't seem compatible with direct > dispatch on a 9-bit opcode field, although it's possible (with that much > parallelism in space, 1 or 2 word per-instruction flows are not > unreasonable). With a control store that small I would have guessed that > a similar technique, where the opcode was used to index a map ram, > which contained a dispatch pc into the control store, and (usually) some > bits which would be used to control the data path, was used. But > I'm happy to be corrected. Yes. The 2K*96 is called CRAM (Control RAM), and there is a 512*??? DRAM (Dispatch RAM). ###### From: Enrico Badella Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Tue, 02 Jan 2001 11:14:42 +0100 Organization: SoftStar Lines: 26 Message-ID: <3A51AA12.BF6C0D3D@softstar.it> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> NNTP-Posting-Host: ns.softstar.it Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: el,en,it Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!newsxfer.eecs.umich.edu!enews.sgi.com!newsfeed.nettuno.it!server-b.cs.interbusiness.it!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2358 Neil Franklin wrote: > > > hardware design, please or please pretty please do NOT > > preclude SMP. > > That should be possible, with an large enough FPGA chip. I think an > XCV1000 should have enough room for 4 processor SMP. And anyway, > unlike real fixed hardware an FPGA can have SMP added just as easy as > an emulator can, so long you do not run out of FPGA space (thats like I think that the point is to enable general SMP not only in the same FPGA some say maybe 16 CPUs on some form of external bus, PCI maybe? e. ======================================================================== Enrico Badella email: enrico.badella@softstar.it Soft*Star srl eb@vax.cnuce.cnr.it InterNetworking Specialists tel: +39-011-746092 Via Camburzano 9 fax: +39-011-746487 10143 Torino, Italy Wanted, for hobbyist use, any type of PDP and microVAX hardware,software, manuals,schematics,etc. and DEC-10 docs or manuals ========================================================================== ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 02 Jan 2001 14:31:45 +0100 Organization: My own Private Self Lines: 53 Message-ID: <6uzoha84hq.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <3A51AA12.BF6C0D3D@softstar.it> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978442305 933 10.0.3.2 (2 Jan 2001 13:31:45 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Jan 2001 13:31:45 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2369 Enrico Badella writes: > Neil Franklin wrote: > > > > > hardware design, please or please pretty please do NOT > > > preclude SMP. > > > > That should be possible, with an large enough FPGA chip. I think an > > XCV1000 should have enough room for 4 processor SMP. And anyway, > > unlike real fixed hardware an FPGA can have SMP added just as easy as > > an emulator can, so long you do not run out of FPGA space (thats like > > I think that the point is to enable general SMP not only in the same FPGA > some say maybe 16 CPUs on some form of external bus, I think the "do not preclude SMP" can be read that way. But as far as I know BAH from previous posts about SMP vs channels she really is just thinking of having multiple CPUs as being superiour to having specialised channel processors, not of multiple chips. And FPGA hardwarily one XCV1000 with 4 CPUs in it is a lot easier than 4 XCV300s (= same amount of space) with each 1 CPU in them. Because this gets rid of all the pin-count limited interconnection problems. Now for an 16 CPU system one may have to use 4 XCV1000 with each 4 CPUs in them. But even then I think I would first try to bug Xilinx to extend the JBits tools so that I could use the E series and then take an XCV3200E (3 times XCV1000E (=XCV1000 size in E series) space) and then do 12 CPUs. Note though that then we may have memory bottleneck problems. Pins really are a big problem, space in a single chip is far less so. > PCI maybe? If I had to go for an multi-chip system, then I would prefer to give each chip its own external RAM and then use some point to point interconnect, like that used in them SGI ccNUMA style boxes (4 CPUs SMP per node, up to 256 nodes ccNUMA interconnected [1]). Just that I would assume an max 4 chips a 4CPU/chip design. [1] Note: at work I sysadmin an 2 nodes * 2 processors SGI, I know how fast they are, even this smallest model. But all SMP discussion is about stuff _way_ into the future. First I need to make an single CPU and get thet up to its maximum speed. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 02 Jan 2001 15:00:53 +0100 Organization: My own Private Self Lines: 62 Message-ID: <6uwvce8356.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978444053 1095 10.0.3.2 (2 Jan 2001 14:00:53 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Jan 2001 14:00:53 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2370 David G Conroy writes: > >> You should not assume that you need to have > >> a small horizontal microstore just because the KL10 did. Times change, > > > > I'm not sure I understand what you're suggesting. If I undestand him correctly. He was suggesting an longer but narrower u-code RAM, i.e. 2k*96 -> 32k*(a lot lower then 96). > > So are you saying that since > > it is more practical to do it that way now, that it's reasonable to use > > that style of design now? More practical to do it with narrow u-code and clock through more u-code instructions per PDP-10 instruction. > unreasonable). With a control store that small I would have guessed that > a similar technique, where the opcode was used to index a map ram, > which contained a dispatch pc into the control store, and (usually) some > bits which would be used to control the data path, was used. But Which seems to be what Eric then documented in his reply (CRAM/DRAM). > I was actually saying that Neil should look very hard at > the technology he is planning to use, and ask himself the question "what > realization does this technology encourage", because it Which is actually exactly what I did. I discovered following limits: - I have logic (CLBs) to burn - CLBs are usuall 4 input, but pairs can 5 input and quadrupels 6 input also strings of CLBs can wide-and/or (this is Virtex, not XC4000) - pins are scarse, particularly as I am limited to TQFP - u-code RAM will not fit in chip -> external -> costs pins, not CLBs So that lead to the "hardware for simple stuff (only costs CLBs), trap&emulate for complex stuff (uses existing memory bus, saves pins)" design. Looking at your later post it suggests an "32 wide microcode using same bus as memory" design. At the moment I still prefer my original idea because less memory interface contention problems, but I will be keeping your one in mind in case mine turns out too complicated to handle. So thanks for the tip. > and they didn't have to deal > with FPGA interconnect delay, to name but a few of the changes in > technology. That one could turn out to change the design. I will have a look out for it. At the moment I will be trying to do state machine logic (most likely the "one hot" type that FPGAs like) and see how far I get. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### From: Enrico Badella Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip Date: Tue, 02 Jan 2001 15:38:49 +0100 Organization: SoftStar Lines: 29 Message-ID: <3A51E7F9.97058921@softstar.it> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <3A51AA12.BF6C0D3D@softstar.it> <6uzoha84hq.fsf@chonsp.franklin.ch> NNTP-Posting-Host: ns.softstar.it Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: el,en,it Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newsfeed.nettuno.it!server-b.cs.interbusiness.it!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2371 Neil Franklin wrote: > > If I had to go for an multi-chip system, then I would prefer to give > each chip its own external RAM and then use some point to point I was saying PCI just because it is more or less common. > But all SMP discussion is about stuff _way_ into the future. First I Yeah, but you got me way in the past when in University we tried to build an 8080 using 2901. Intriguing project but it never worked well; I've always had a love affair with 2901... Too bad I must bring the kids to the mountains and I cannot keep reading this thread! e. ======================================================================== Enrico Badella email: enrico.badella@softstar.it Soft*Star srl eb@vax.cnuce.cnr.it InterNetworking Specialists tel: +39-011-746092 Via Camburzano 9 fax: +39-011-746487 10143 Torino, Italy Wanted, for hobbyist use, any type of PDP and microVAX hardware,software, manuals,schematics,etc. and DEC-10 docs or manuals ========================================================================== ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Tue, 02 Jan 01 11:04:40 GMT Organization: UltraNet Communications, Inc. Lines: 64 Message-ID: <92sgmh$9dn$2@bob.news.rcn.net> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> X-Trace: UmFuZG9tSVZq9sVl6wD7OCncxhKNpwZx70V9mFE9b4uZ11PfhzvZiRdbEr3tBU8E X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 2 Jan 2001 12:14:09 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!209-122-236-81 Xref: chonsp.franklin.ch alt.sys.pdp10:2373 In article <6uae9bnv9l.fsf@chonsp.franklin.ch>, Neil Franklin wrote: >jmfbahciv@aol.com writes: > >> I don't understand either. Is he doing a hardware design or >> just another software layer design? > >Something in between that does not have an -ware name. > >As far as an outside observer (not looking into the FPGA chip) would >see it, it will look just like I made an custom designed chip. > >But actually FPGA chips split the hard-/software split into 3 levels: > >- hardware (is sub-split) > - actual chip (mass manufactured like processors) > - chip configuration (bits, programmed, but wires the chip, not executed) >- software (normal software that gets executed) > >What I will be doing is at chip configuration level (at least for the >initial KI, some of the complex KL extensions will be real software >(written in PDP-10 macro)). It sounds like the equivalent of the KL microcode that can be touched with my finger. > >At this level the underlying chip appears as an grid of 16*1bit RAMs, >single flipflops, muxes in between them, a few 256*16bit RAMs allong >the edges, and all interconnected by an grid of interconnect lines >covered by an sea of switch transistors. These are all configured >(bits into the RAMs and FFs, switches opened) by an "second layer" in >the chip consising of just an big RAM. > >Strictly working with FPGAs is programming, i.e. generating an file >full of bits. But this file is intended for loading into the "second >layer", after which the hardware of the "first layer" is "shaped" to >work as if it had been designed as a custon chip. If you're going to all that bother, making it look exactly like a KL isn't the way to go. The KL really sucked. > > >> And if he's doing a >> hardware design, please or please pretty please do NOT >> preclude SMP. > >That should be possible, with an large enough FPGA chip. I think an >XCV1000 should have enough room for 4 processor SMP. And anyway, >unlike real fixed hardware an FPGA can have SMP added just as easy as >an emulator can, so long you do not run out of FPGA space (thats like >running out of memory in a program on an non-virtual memory machine). The key to TOPS-10's implementation to SMP isn't just having a count of CPUs. It has everything to do with data paths from the CPU's to all of the devices. Our disks were limited to two ports. Comm gear was a PITA until we got Ethernet. A well-run SMP system did not have to context switch just because the job did an I/O request. /BAH Subtract a hundred and four for e-mail. ###### From: aek@spies.com (Al Kossow) Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 2 Jan 2001 09:25:54 -0800 Organization: Spies In The Wire Lines: 10 Message-ID: <92t2v2$lft$1@spies.com> References: <6uwvce8356.fsf@chonsp.franklin.ch> NNTP-Posting-Host: spies.com X-Trace: 2 Jan 2001 09:29:31 -0800, spies.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!HSNX.atgi.net!news.kjsl.com!news.spies.com!localhost!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2381 From article <6uwvce8356.fsf@chonsp.franklin.ch>, by Neil Franklin : > > - I have logic (CLBs) to burn If that is true, you may want to think about non-microcoded implementations ala KA/KI. The PDP-6 manual that is on line is an interesting read. They just don't make computers that work that way any more :-) Hopefully, I'll be able to get scannable copies of the KI docs soon. ###### From: Rich Alderson Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 02 Jan 2001 14:39:29 -0500 Organization: Systems Administration, XKL LLC, Redmond WA 98052 Lines: 11 Sender: alderson+news@panix3.panix.com Message-ID: References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <3A509D31.7CA23886@bartek.dontspamme.net> <6uitnykefe.fsf@chonsp.franklin.ch> NNTP-Posting-Host: panix3.panix.com X-Trace: news.panix.com 978464369 4582 166.84.0.228 (2 Jan 2001 19:39:29 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: 2 Jan 2001 19:39:29 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!newsxfer.eecs.umich.edu!panix!news.panix.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2376 Neil Franklin writes: > - TOPS-10 for the KI, as both TOPS-20 and Linux or NetBSD will not fit > into 256kword. Tops-20 v. 3A or earlier will fit in 256K, as will TENEX. Just have to find them. TENEX is probably easier at this point... -- Rich Alderson alderson+news@panix.com "You get what anybody gets. You get a lifetime." --Death, of the Endless ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 02 Jan 2001 22:58:45 +0100 Organization: My own Private Self Lines: 130 Message-ID: <6un1d98vl6.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978472725 4528 10.0.3.2 (2 Jan 2001 21:58:45 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Jan 2001 21:58:45 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2382 jmfbahciv@aol.com writes: > In article <6uae9bnv9l.fsf@chonsp.franklin.ch>, > Neil Franklin wrote: > >jmfbahciv@aol.com writes: > > > >> I don't understand either. Is he doing a hardware design or > >> just another software layer design? > > > >Something in between that does not have an -ware name. > > It sounds like the equivalent of the KL microcode that can be > touched with my finger. It is equivalent to KL in _only_ that one sense: that it is as easily modifiable. Apart from that it is totally different. After writing my last post I had a bit of idle time while travelling by rail to friends. While that I came up with an analogy that may help explain to non-EEs what FPGA programming is like. 1st step: remember the way the real KI was manufactured: - On one side there was the Flip-Chip modules, a small selection of mass produced hardware parts that were produced independant of whether they will end up in an 10, any other CPU, or even an peripheral controller or device. - On the other side there is the backplane, hardwired to be an KI and only an KI. Strictly speaking the KI-specific design work in the end resulted in 2 things: an backplane wiring list for the wire wrap machine and an assembly list for the assembly worker who will have to plug the right combination of Flip-Chip modules into the backplane. 2nd step: think of some following hypothetical hardware, generation 1: - An universal backplane where every socket has identical wiring to its neighbors -> no KI-specific wiring list. - Only one universal Flip-Chip module, that can be switched to be any type of module by a row of switches on it. It can also used any selection of the backplane wires of its socket, due to yet more switches on it. We will call this universal Flip-Chip an Configurable Logic Block (CLB). Now put one CLB into every socket -> no KI-specific assembly list. The entire result is still totally non-KI-specific. To make it into an KI you now have an "configuration worker" to set all the switches to the appropriate position. For this the designer has to supply an configuration list. An other configuration list would make it an 8, yet another list an peripheral, or anything else. (And yes, this is unpayably expensive in 1960s technology!) 3rd step: because of many configuration worker switching errors (just like the backplane wiring worker errors that lead to using wire wrap machines) we now make hypotherical hardware, generation 2: - Replace all the switches with switch transistors controlled by an small configuration memory on each CLB. - Have the backplane wired so that all these small memories are linked together and appear as one large one. To make this hardware into an KI you now just need to load all the configuration memories from an file. So now it just takes an other file to make an 8, peripheral, or anything else. (and yes, this is even more expensive in 1960s technology) 4th step: now implement this "generation 2" hardware with 2000s technology, all of it (backplane, CLBs, configuration memories) in one single chip! Now you have got an FPGA chip. To make this into an KI one just needs the right configuration file. And that is my design work: to produce the file for loading into the configuration memories that switches an FPGA to be an KI. These configuration files are as maleable as KL microcode, but from the way they are used by the chip (rewiring it) they are more like KI wiring and assembly lists. I hope this description makes FPGAs more comprehensable. For those readers who understand electronics, the details are here: http://www.xilinx.com/partinfo/ds003.pdf (450k, needs Acrobat reader). > If you're going to all that bother, making it look exactly like > a KL isn't the way to go. The KL really sucked. Which is why I have decided to wire an KI like hardware and then make it possible to run KL programs by having the processor UUO on KL instructions and then have the UUO run an Macro program that simulates the KL instructions. Actually some of the more complex and seldom used KI instructions may also end up being UUO + simulation. > >> And if he's doing a > >> hardware design, please or please pretty please do NOT > >> preclude SMP. > > > >That should be possible, with an large enough FPGA chip. I think an > >XCV1000 should have enough room for 4 processor SMP. And anyway, > >unlike real fixed hardware an FPGA can have SMP added just as easy as > >an emulator can, so long you do not run out of FPGA space (thats like > >running out of memory in a program on an non-virtual memory machine). > > The key to TOPS-10's implementation to SMP isn't just having > a count of CPUs. It has everything to do with data paths from > the CPU's to all of the devices. Our disks were limited to two > ports. Comm gear was a PITA until we got Ethernet. A well-run > SMP system did not have to context switch just because the > job did an I/O request. So I assume one CPU was waiting for the others IO call and then took up the job there? If not: how was this done? I would like to know, so that I can do this the right from the start. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 02 Jan 2001 23:00:24 +0100 Organization: My own Private Self Lines: 22 Message-ID: <6uk88d8vif.fsf@chonsp.franklin.ch> References: <6uwvce8356.fsf@chonsp.franklin.ch> <92t2v2$lft$1@spies.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978472827 4528 10.0.3.2 (2 Jan 2001 22:00:27 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Jan 2001 22:00:27 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2383 aek@spies.com (Al Kossow) writes: > From article <6uwvce8356.fsf@chonsp.franklin.ch>, by Neil Franklin : > > > > - I have logic (CLBs) to burn > > If that is true, you may want to think about non-microcoded implementations > ala KA/KI. Which is exactly my present intention. > The PDP-6 manual that is on line is an interesting read. Thanks for the reminder. I saw that one 1.5 years ago but did not download it because it was 20MByte. But now with the cable modem I can get it. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 02 Jan 2001 23:03:13 +0100 Organization: My own Private Self Lines: 16 Message-ID: <6ug0j18vdq.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.t aronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.tar onga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> < 6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92p qre$8ah$2@bob.news.rcn.net> <3A509D31.7CA23886@bartek.dontspamme.net> <6uitnykef e.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978472993 4528 10.0.3.2 (2 Jan 2001 22:03:13 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Jan 2001 22:03:13 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2384 Rich Alderson writes: > Neil Franklin writes: > > > - TOPS-10 for the KI, as both TOPS-20 and Linux or NetBSD will not fit > > into 256kword. > Tops-20 v. 3A or earlier will fit in 256K, as will TENEX. Just have to find > them. TENEX is probably easier at this point... Is that 256k on an KI or only from KL on upward? -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### From: Arthur Krewat Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Organization: Kilonet.net Lines: 41 Message-ID: <3A5267C9.EC3D4EF0@bartek.dontspamme.net> References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> <6un1d98vl6.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (X11; I; SunOS 5.8 i86pc) X-Accept-Language: en Date: Tue, 02 Jan 2001 23:45:38 GMT NNTP-Posting-Host: 167.206.68.16 X-Trace: news02.optonline.net 978479138 167.206.68.16 (Tue, 02 Jan 2001 18:45:38 EST) NNTP-Posting-Date: Tue, 02 Jan 2001 18:45:38 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!newsfeed.skycache.com!Cidera!cyclone-sjo1.usenetserver.com!news-out.usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2396 Neil Franklin wrote: > > > > To make this into an KI one just needs the right configuration file. > And that is my design work: to produce the file for loading into the > configuration memories that switches an FPGA to be an KI. > > These configuration files are as maleable as KL microcode, but from the > way they are used by the chip (rewiring it) they are more like KI wiring > and assembly lists. I hope this description makes FPGAs more comprehensable. Reading this thread from the beginning, I never imagined anyone would actually propose microcoding inside of an FPGA! You could take the KL microcode and convert it to VHDL :) > > If you're going to all that bother, making it look exactly like > > a KL isn't the way to go. The KL really sucked. > > Which is why I have decided to wire an KI like hardware and then make it > possible to run KL programs by having the processor UUO on KL > instructions and then have the UUO run an Macro program that simulates > the KL instructions. What sucked about the KL? Besides microcoding and other useless schemes that wouldn't fit into today's world of FPGA's. > Actually some of the more complex and seldom used KI instructions may > also end up being UUO + simulation. Hmm... this approach is a little weird. It will take more space from the FPGA, but I can't imagine EXTEND and the other KL/KS instructions being THAT hard to implement... adding software to the problem is not the "pure" way to go. I discussed this a few weeks ago, about adding DZ11 support to Tim Stark's emulator. The (my) answer was to emulate a DZ11 in the emulator, and not hack TOPS-10/20 to take care of it. I can't imagine emulating KL instructions under a KI hardware scheme would be "pure" :) art k. ###### From: berd_kalamunda@techemail.com (Rolie Baldock) Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Wed, 03 Jan 2001 00:07:35 GMT Message-ID: <3a526c10.10949738@news.m.iinet.net.au> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3a510463.3916427@news.m.iinet.net.au> <6ud7e6kcen.fsf@chonsp.franklin.ch> X-Newsreader: Forte Free Agent 1.11/16.235 Lines: 43 NNTP-Posting-Host: 203.59.67.206 X-Trace: news.iinet.net.au 978480252 32748 emut7d@203.59.67.206 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!merapi!enews.sgi.com!EU.net!blackbush.xlink.net!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!skynet.be!newsfeed.iinet.net.au!news.iinet.net.au!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2390 Neil, I have neither the time nor the SKILL to embark on such a project. My hope was that I could inspire somebody to build a 96 bit expanded PDP-10. Why the 96 bits! Well I imagine RAM now comes in 32bit chunks so 3 of them to get a word size a multiple of 3 bits was the underlying thought for efficient programming for colour monitors. Regards, On 02 Jan 2001 01:47:44 +0100, Neil Franklin wrote: >berd_kalamunda@techemail.com (Rolie Baldock) writes: > >> Were I taking on your PDP-10 project I would not make it a 36 bit >> architecture but a 96 bit architecture with many more fast registers >> and 48 bit address field in the RH of the word. Yes I know it wold not >> be a PDP-10 > >Which would sort of negate the projects purpose. I am in it for historical >interest. > > >> but times change and the advantages would be ASTRONOMIC. >> The 96 bit word would be very efficient in the 8bit byte area and the >> 3bit tri-colour area of the screen. Phased routines running in >> registers would be greatly enhanced.....etc...etc. >> Once the logic for the E-Box is finalised it should not be too hard to >> upgrade the size of the word. > >If you are interested in such an processor design, go and have a look >at the F-CPU project at http://www.f-cpu.org/. They are doing an 64 >register auto-adapting n*32bit (initially n=2) width SIMD style >design. Including aiming for mass produced ASIC. Jokingly called the >"Merced killer". Looks like quite a big project. > > >-- >Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ >Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic --Rolie Baldock. email: ###### From: rpw3@rigden.engr.sgi.com (Rob Warnock) Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 3 Jan 2001 12:31:57 GMT Organization: Silicon Graphics Inc., Mountain View, CA Lines: 26 Message-ID: <92v63t$kq660$1@fido.engr.sgi.com> References: <3A3A338C.8DE7FFA5@bartek.net> <6uwvce8356.fsf@chonsp.franklin.ch> NNTP-Posting-Host: rigden.engr.sgi.com X-Trace: fido.engr.sgi.com 978525117 21829824 163.154.34.115 (3 Jan 2001 12:31:57 GMT) X-Complaints-To: news@fido.engr.sgi.com NNTP-Posting-Date: 3 Jan 2001 12:31:57 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!telocity-west!TELOCITY!enews.sgi.com!fido.engr.sgi.com!rigden.engr.sgi.com!rpw3 Xref: chonsp.franklin.ch alt.sys.pdp10:2386 Neil Franklin wrote: +--------------- | At the moment I will be trying to do state machine logic (most | likely the "one hot" type that FPGAs like) and see how far I get. +--------------- Note that the KA-10 used a "asynchronous one-hot" design. That is, instead of there being a single synchronous system clock with the "one hot" being the one flop in the whole system that was set, there were lots of various-length delay lines with one-shot pulse amplifiers on their outputs, and the "one hot" was defined by which delay line "the" clock pulse was currently hiding inside. By converting the delay lines to chains of clocked flops (or a counted loop around a flop, for the longer delays), this style can be almost trivially converted to modern synchronous one-hot style. [Is that what the KI did?] -Rob ----- Rob Warnock, 31-2-510 rpw3@sgi.com SGI Network Engineering http://reality.sgi.com/rpw3/ 1600 Amphitheatre Pkwy. Phone: 650-933-1673 Mountain View, CA 94043 PP-ASEL-IA ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 03 Jan 2001 19:20:10 +0100 Organization: My own Private Self Lines: 96 Message-ID: <6uu27go5ut.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> <6un1d98vl6.fsf@chonsp.franklin.ch> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978546013 2709 10.0.3.2 (3 Jan 2001 18:20:13 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 3 Jan 2001 18:20:13 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2403 Arthur Krewat writes: > Neil Franklin wrote: > > > > > > Reading this thread from the beginning, I never imagined anyone would actually > propose microcoding inside of an FPGA! I did not expect it (and was surprised). But I understand that it is an other way to handle the problems stemming from KL being microcoded and aquiring some complex instructions because "they were easy to do". I should perhaps add, that David G Conroy has FPGA experience (he did an PDP-8/I clone in an XCS10 chip). And I assume that he did that in state machine logic, as the original was. I also know that he is working on PDP-1 and PDP-4/7/9/15 and has looked into PDP-10s, so I am taking his idea serious. > > > If you're going to all that bother, making it look exactly like > > > a KL isn't the way to go. The KL really sucked. > > > > Which is why I have decided to wire an KI like hardware and then make it > > possible to run KL programs by having the processor UUO on KL > > instructions and then have the UUO run an Macro program that simulates > > the KL instructions. > > What sucked about the KL? Besides microcoding and other useless schemes > that wouldn't fit into today's world of FPGA's. If I remember BAHs anti-KL posts correctly (I can't find them). She disliked the "IBMification" of the instruction set that became possible (and was done) with microcode. I certainly was nearly stunned when I did my first fast read the XKL docs and found the EDIT instruction. An entire second instruction set, triggered by one instruction. Now that is miles away from the elegant instruction set of the KI. Really IBMish, or VAXish :-). > > Actually some of the more complex and seldom used KI instructions may > > also end up being UUO + simulation. > > Hmm... this approach is a little weird. It will take more space from the > FPGA, but I can't imagine EXTEND and the other KL/KS instructions > being THAT hard to implement... I don't think that extend is a problem, just a second set of states in the state machine. But things like EDIT may be too complex to make an state machine for. > adding software to the problem is not > the "pure" way to go. But may be neccessary for some of the complex stuff. Note that if I can get it to work without this UUO hack I will try. > I discussed this a few weeks ago, about adding > DZ11 support to Tim Stark's emulator. The (my) answer was to emulate > a DZ11 in the emulator, and not hack TOPS-10/20 to take care of it. That is sure. I want to run 100% unchanged TOPS-10/20. I suppose that makes a bit more technology description necessary: What I am thinking of (and may not need anyway) is to do something like the trick that Intel used in the 386SL (not 386SX!) notebook processor. In this there exists in addition to the normal user and system modes (used by whatever PC OS) an third mode (Intel calls it SMI) that is even lower than system and only used for emulytion. When the processor is started is starts in SMI, then loads the emulation code, then switches to system mode and runs an unaltered OS. The SMI is only ever entered when nonimplemented instructions or IOs to non-existant hardware are met. I was thinking of loading the emulation code from the FPGA boot EEPROM, so the TOPS-10/20 running after from disk will newer even hear about it. > I can't imagine emulating KL instructions under a KI hardware scheme > would be "pure" :) But it may be an neccessary compromise for an non-microcode machine to implement some of the more complex KL instructions, or even some of the IO (say a complex console terminal (VT100 had an 8080 in it)), or even code that replaces the KLs PDP-11/40, like the microcode of the XKL does. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 03 Jan 2001 19:49:53 +0100 Organization: My own Private Self Lines: 32 Message-ID: <6ur92ko4ha.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3a510463.3916427@news.m.iinet.net.au> <6ud7e6kcen.fsf@chonsp.franklin.ch> <3a526c10.10949738@news.m.iinet.net.au> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978547793 2878 10.0.3.2 (3 Jan 2001 18:49:53 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 3 Jan 2001 18:49:53 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2404 berd_kalamunda@techemail.com (Rolie Baldock) writes: > I have neither the time nor the SKILL to embark on such a project. My > hope was that I could inspire somebody to build a 96 bit expanded > PDP-10. Well, anyone can extend my clone, when it is finished. Perhaps I should code various constants of 36 and 18 as variables. > Why the 96 bits! Well I imagine RAM now comes in 32bit chunks Depends. Async SRAM is 4 or 8 bit, Sync SRAM is 8/16/32, ZBT SRAM is 18/36 (yes, really!), DRAM is 1/4/8/16, SDRAM is usually 16 bit. > so 3 of them to get a word size a multiple of 3 bits was the > underlying thought for efficient programming for colour monitors. With a bunch of shift registers one can do 3*8bit video in any width of RAM. The PC I am writing this on has 64bit video RAM and the hardware can do 24bit video, if the driver were not broken. So I run it as 32bit video and throw 1/4 away! RAM is cheap these days. Actually I get into problems with video RAM bus bandwidth. PCs, argh! For the begin I will be using 5*8bit RAM for the 10, throwing 4bits away. A 72bit machine would use 9*8 or 5*16 with 8 thrown away. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Thu, 04 Jan 01 11:39:52 GMT Organization: UltraNet Communications, Inc. Lines: 35 Message-ID: <931rh3$2i$1@bob.news.rcn.net> References: <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> <6un1d98vl6.fsf@chonsp.franklin.ch> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> X-Trace: UmFuZG9tSVYSzeHwfMHB8rYc8wwcHp1G9YnBHNZG4wjcNYboaFVHwjKzKz2PzeW6 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 4 Jan 2001 12:49:39 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!fr.clara.net!heighliner.fr.clara.net!xfer10.netnews.com!netnews.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-245-24 Xref: chonsp.franklin.ch alt.sys.pdp10:2416 In article <3A5267C9.EC3D4EF0@bartek.dontspamme.net>, Arthur Krewat wrote: >Neil Franklin wrote: >> > If you're going to all that bother, making it look exactly like >> > a KL isn't the way to go. The KL really sucked. >> >> Which is why I have decided to wire an KI like hardware and then make it >> possible to run KL programs by having the processor UUO on KL >> instructions and then have the UUO run an Macro program that simulates >> the KL instructions. > >What sucked about the KL? Besides microcoding and other useless schemes >that wouldn't fit into today's world of FPGA's. The cache wasn't write-thru. Debugging the monitor was a PITA since the CTY wasn't really a CTY. Visual cues were gone other than the external memory lights (it's so much faster to take a look at the CPU's lights than type in locations to the front end terminal and have it display via ASCII. For really hairy symptoms, it was just another level of complexity to have to deal with a front end system. Trying to figure out if the problem was a 20F problem or a -10 problem or a 20F/PDP-10 problem was enough to make a pro quit. It was unsettling to leave bit pushing to some unknown mini-developer...especially the "unknown" part. The HSC development had the same problems. /BAH Subtract a hundred and four for e-mail. ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Thu, 04 Jan 01 11:52:57 GMT Organization: UltraNet Communications, Inc. Lines: 39 Message-ID: <931s9k$2i$4@bob.news.rcn.net> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3A53BEB7.802B5BEF@prescienttech.com> X-Trace: UmFuZG9tSVYloNgLGTQGn5ZPPPbwI5ByNJFrfwgjKAyXsNgwGtRY3zoeMTJgxcHG X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 4 Jan 2001 13:02:44 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!209.249.123.233.MISMATCH!xfer10.netnews.com!netnews.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-245-24 Xref: chonsp.franklin.ch alt.sys.pdp10:2417 In article <3A53BEB7.802B5BEF@prescienttech.com>, "Carl R. Friend" wrote: >David G Conroy wrote: >> >> Doing SMP is more complicated that finding space for the >> processors. The processors, I/O devices, and memory have to be >> designed so that they implement the correct multiprocessing model >> (for example, exactly when do operations on one processor and/or I/O >> device become observable at other processors and/or I/O devices, >> and which operations are guaranteed to be atomic). > > The biggest problem that faced the SMP designers was the KL's >cache memory. > > With a KI (and, yes, SMP worked on KIs), there was the inherent >atomicity of the RMW (Read/Modify/Write) cycle on the memory bus (core, >early-on, remember) as any other requests for that location (controller, >to be perfectly honest) were blocked at the outset until the original >RMW completed. The bit test-and-set instructions used this access >method making spinlocks an effective (and fool-proof) tactic. > > Since the KLs' caches were internal to the CPU box, there needed >to be some mechanism to ensure that all the caches were coherent. >This is where a multi-10-on-a-single-board would have an enormous >design advantage - the designer could use a single large (fast) cache >so getting multiple caches out of sync couldn't happen. Too, cache >coherency could be disturbed by external DMA devices (e.g. an RH-10/ >DF-10 doing a disk transfer). > > In any event, DRAM is now faster than the KL's cache, so one way >of looking at the problem is to "do away with the cache" and simply >run out of a single _very_ fast mainstore (like many supers of the >time did). > Thank you! :-) /BAH Subtract a hundred and four for e-mail. ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Thu, 04 Jan 01 11:49:52 GMT Organization: UltraNet Communications, Inc. Lines: 35 Message-ID: <931s3r$2i$3@bob.news.rcn.net> References: <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> <6un1d98vl6.fsf@chonsp.franklin.ch> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> <6uu27go5ut.fsf@chonsp.franklin.ch> <3A53ACB6.7EE480BE@bartek.dontspamme.net> X-Trace: UmFuZG9tSVaSnBZagRuxiY81kK1HrNDXd6PJgl+kqOTIlMGvhsRnRgcW4jGdz/n3 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 4 Jan 2001 12:59:39 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.tele.dk!128.230.129.106!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-245-24 Xref: chonsp.franklin.ch alt.sys.pdp10:2418 In article <3A53ACB6.7EE480BE@bartek.dontspamme.net>, Arthur Krewat wrote: >Neil Franklin wrote: >> >> > What sucked about the KL? Besides microcoding and other useless schemes >> > that wouldn't fit into today's world of FPGA's. >> >> If I remember BAHs anti-KL posts correctly (I can't find them). She >> disliked the "IBMification" of the instruction set that became >> possible (and was done) with microcode. > >I've never had any IBM experience. Only DEC. I never realized that this >was an IBMification. I just saw the new instructions (going from KA to KS) >and loved them. If I had known it was viewed that way by purists, I would >never have jumped on the bandwagon :) > >> I certainly was nearly stunned when I did my first fast read the XKL >> docs and found the EDIT instruction. An entire second instruction set, >> triggered by one instruction. Now that is miles away from the elegant >> instruction set of the KI. Really IBMish, or VAXish :-). > >Sounds like something that a newbie did because [s]he didn't want to >mess with the basic instruction set too much - a UUO without the UUO.. >It was handled by the microcode, not the monitor. Yeah, sounds VAXish. Nope. It's at the other extreme. It has to do with somebody very experienced with software development cycles and not having to modify *.MAC in order to debug and test the monitor. /BAH Subtract a hundred and four for e-mail. ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Thu, 04 Jan 01 11:47:32 GMT Organization: UltraNet Communications, Inc. Lines: 66 Message-ID: <931rvf$2i$2@bob.news.rcn.net> References: <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> <6un1d98vl6.fsf@chonsp.franklin.ch> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> <6uu27go5ut.fsf@chonsp.franklin.ch> X-Trace: UmFuZG9tSVZ5ddsCRWAk19FbJKeBuwooHY2lr8yvCOtuZn+1KB8LAgOnHpN15JOe X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 4 Jan 2001 12:57:19 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-245-24 Xref: chonsp.franklin.ch alt.sys.pdp10:2422 In article <6uu27go5ut.fsf@chonsp.franklin.ch>, Neil Franklin wrote: >Arthur Krewat writes: > >> Neil Franklin wrote: >> > >> > >> >> Reading this thread from the beginning, I never imagined anyone would actually >> propose microcoding inside of an FPGA! > >I did not expect it (and was surprised). But I understand that it is >an other way to handle the problems stemming from KL being microcoded >and aquiring some complex instructions because "they were easy to do". > >I should perhaps add, that David G Conroy has FPGA experience (he did an >PDP-8/I clone in an XCS10 chip). And I assume that he did that in state >machine logic, as the original was. I also know that he is working on >PDP-1 and PDP-4/7/9/15 and has looked into PDP-10s, so I am taking his >idea serious. > > >> > > If you're going to all that bother, making it look exactly like >> > > a KL isn't the way to go. The KL really sucked. >> > >> > Which is why I have decided to wire an KI like hardware and then make it >> > possible to run KL programs by having the processor UUO on KL >> > instructions and then have the UUO run an Macro program that simulates >> > the KL instructions. >> >> What sucked about the KL? Besides microcoding and other useless schemes >> that wouldn't fit into today's world of FPGA's. > >If I remember BAHs anti-KL posts correctly (I can't find them). She >disliked the "IBMification" of the instruction set that became >possible (and was done) with microcode. No. I never got to the level of microcode so I wouldn't have stated this. >> I discussed this a few weeks ago, about adding >> DZ11 support to Tim Stark's emulator. The (my) answer was to emulate >> a DZ11 in the emulator, and not hack TOPS-10/20 to take care of it. > >That is sure. I want to run 100% unchanged TOPS-10/20. I suppose that >makes a bit more technology description necessary: Also note that I am not one of these purists that insist TOPS10 has to run unmodified. I have no objection to a new CPU device driver (which is how I think of them) getting written to take advantage of CPU features. However, the transition of going from one CPU to another is a complicated development effort (at least it was when I watched JMF do it). One of the constraints that we had was to not break all the other software. To break all of the other software would require that everything be developed at the same time as the monitor. Nobody could coordinate that..besides the fact that it would take man-centuries to do the job. /BAH Subtract a hundred and four for e-mail. ###### Message-ID: <3A528FEA.5E47B606@jetnet.ab.ca> Date: Tue, 02 Jan 2001 19:35:22 -0700 From: Ben Franchuk X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.18 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> <6un1d98vl6.fsf@chonsp.franklin.ch> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> <6uu27go5ut.fsf@chonsp.franklin.ch> <931rvf$2i$2@bob.news.rcn.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.41 X-Trace: 4 Jan 2001 10:13:05 -0700, 207.153.6.41 Organization: OA Internet Lines: 27 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!merapi!news-ge.switch.ch!enews.sgi.com!newshub2.rdc1.sfba.home.com!news.home.com!newsfeed.direct.ca!look.ca!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.41 Xref: chonsp.franklin.ch alt.sys.pdp10:2415 jmfbahciv@aol.com wrote: > > In article <6uu27go5ut.fsf@chonsp.franklin.ch>, > Neil Franklin wrote: > >Arthur Krewat writes: > > > >> Neil Franklin wrote: > >> > > >> > > >> > >> Reading this thread from the beginning, I never imagined anyone would > actually > >> propose microcoding inside of an FPGA! > > > >I did not expect it (and was surprised). But I understand that it is > >an other way to handle the problems stemming from KL being microcoded > >and aquiring some complex instructions because "they were easy to do". Many modern FPGA's have small amounts of internal RAM. The FPGA I am using has 256 x 8 x 3 bits of ram.This can be used as a RAM or a ROM logic table. Just guessing here abut a large-midsized chip would be about $500 with a $125 socket.Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk ###### From: Arthur Krewat Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Organization: Kilonet.net Lines: 43 Message-ID: <3A53ACB6.7EE480BE@bartek.dontspamme.net> References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> <6un1d98vl6.fsf@chonsp.franklin.ch> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> <6uu27go5ut.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (X11; I; SunOS 5.8 i86pc) X-Accept-Language: en Date: Wed, 03 Jan 2001 22:55:39 GMT NNTP-Posting-Host: 167.206.68.16 X-Trace: news02.optonline.net 978562539 167.206.68.16 (Wed, 03 Jan 2001 17:55:39 EST) NNTP-Posting-Date: Wed, 03 Jan 2001 17:55:39 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-stuttgart.de!logbridge.uoregon.edu!newsfeed.direct.ca!look.ca!cyclone-sjo1.usenetserver.com!news-out.usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2451 Neil Franklin wrote: > > > What sucked about the KL? Besides microcoding and other useless schemes > > that wouldn't fit into today's world of FPGA's. > > If I remember BAHs anti-KL posts correctly (I can't find them). She > disliked the "IBMification" of the instruction set that became > possible (and was done) with microcode. I've never had any IBM experience. Only DEC. I never realized that this was an IBMification. I just saw the new instructions (going from KA to KS) and loved them. If I had known it was viewed that way by purists, I would never have jumped on the bandwagon :) > I certainly was nearly stunned when I did my first fast read the XKL > docs and found the EDIT instruction. An entire second instruction set, > triggered by one instruction. Now that is miles away from the elegant > instruction set of the KI. Really IBMish, or VAXish :-). Sounds like something that a newbie did because [s]he didn't want to mess with the basic instruction set too much - a UUO without the UUO.. It was handled by the microcode, not the monitor. Yeah, sounds VAXish. > I don't think that extend is a problem, just a second set of states in > the state machine. But things like EDIT may be too complex to make an > state machine for. Not sure about that. Build the basic model to take care of instructions that do not return within a few clock-cycles :) > > I can't imagine emulating KL instructions under a KI hardware scheme > > would be "pure" :) > > But it may be an neccessary compromise for an non-microcode machine to > implement some of the more complex KL instructions, or even some of > the IO (say a complex console terminal (VT100 had an 8080 in it)), or > even code that replaces the KLs PDP-11/40, like the microcode of the > XKL does. Make it a UART, and the terminal won't need to be emulated, that and some 1488 and 1489's... you got a PC for a front-end, right? :- ak ###### From: "Carl R. Friend" Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Wed, 03 Jan 2001 19:07:19 -0500 Organization: as little as possible! Lines: 39 Message-ID: <3A53BEB7.802B5BEF@prescienttech.com> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVatfe6/nhVGNWBQMh1Q9HzIijQJWQWJEatIQH+sDnjGzAbu1dHSwd5C X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 4 Jan 2001 00:07:21 GMT X-Mailer: Mozilla 4.5 [en] (X11; I; Linux 2.0.29 i586) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!merapi!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!newshub2.rdc1.sfba.home.com!news.home.com!sjc1.nntp.concentric.net!newsfeed.concentric.net!newsfeed.gol.com!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2435 David G Conroy wrote: > > Doing SMP is more complicated that finding space for the > processors. The processors, I/O devices, and memory have to be > designed so that they implement the correct multiprocessing model > (for example, exactly when do operations on one processor and/or I/O > device become observable at other processors and/or I/O devices, > and which operations are guaranteed to be atomic). The biggest problem that faced the SMP designers was the KL's cache memory. With a KI (and, yes, SMP worked on KIs), there was the inherent atomicity of the RMW (Read/Modify/Write) cycle on the memory bus (core, early-on, remember) as any other requests for that location (controller, to be perfectly honest) were blocked at the outset until the original RMW completed. The bit test-and-set instructions used this access method making spinlocks an effective (and fool-proof) tactic. Since the KLs' caches were internal to the CPU box, there needed to be some mechanism to ensure that all the caches were coherent. This is where a multi-10-on-a-single-board would have an enormous design advantage - the designer could use a single large (fast) cache so getting multiple caches out of sync couldn't happen. Too, cache coherency could be disturbed by external DMA devices (e.g. an RH-10/ DF-10 doing a disk transfer). In any event, DRAM is now faster than the KL's cache, so one way of looking at the problem is to "do away with the cache" and simply run out of a single _very_ fast mainstore (like many supers of the time did). -- +------------------------------------------------+---------------------+ | Carl Richard Friend (UNIX Sysadmin) | West Boylston | | Minicomputer Collector / Enthusiast | Massachusetts, USA | | mailto:crfriend@ma.ultranet.com +---------------------+ | http://www.ultranet.com/~crfriend/museum | ICBM: 42:22N 71:47W | +------------------------------------------------+---------------------+ ###### From: rivie@server.newlogan.teraglobal (Roger Ivie) Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3A53BEB7.802B5BEF@prescienttech.com> Reply-To: rivie@teraglobal.com Message-ID: User-Agent: slrn/0.9.6.2 (FreeBSD) NNTP-Posting-Host: 208.186.13.23 Date: 3 Jan 2001 18:47:08 -0600 X-Trace: 3 Jan 2001 18:47:08 -0600, 208.186.13.23 Lines: 23 X-Comments: This message was posted through Newsfeeds.com X-Comments2: IMPORTANT: Newsfeeds.com does not condone, nor support, spam or any illegal or copyrighted postings. X-Comments3: IMPORTANT: Under NO circumstances will postings containing illegal or copyrighted material through this service be tolerated!! X-Report: Please report illegal or inappropriate use to X-Abuse-Info: Please be sure to forward a copy of ALL headers, INCLUDING the body (DO NOT SEND ATTACHMENTS) Organization: Newsfeeds.com http://www.newsfeeds.com 80,000+ UNCENSORED Newsgroups. Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!telocity-west!TELOCITY!local-out2.newsfeeds.com!newsfeeds.com!corp.newsfeeds.com!newsfeeds.com!crp!anonymous!127.0.0.1!crp!rivie Xref: chonsp.franklin.ch alt.sys.pdp10:2430 In article <3A53BEB7.802B5BEF@prescienttech.com>, Carl R. Friend wrote: > In any event, DRAM is now faster than the KL's cache, so one way >of looking at the problem is to "do away with the cache" and simply >run out of a single _very_ fast mainstore (like many supers of the >time did). Forget DRAM; SRAM is fast and convenient. Take a look at Motorola's MCM63R836: 256Kx36 synchronous SRAM with a 3nS cycle time. It's intended for applications like the L2 cache of a G4, but at 36 bits wide it's nice and convenient for a -10. -- Roger Ivie TeraGlobal Communications Corporation 1770 North Research Park Way Suite 100 Logan, UT 84341 mailto:rivie@teraglobal.com phoneto:(435)787-0555 faxto:(435)787-0516 -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =----- ###### User-Agent: Microsoft-Outlook-Express-Macintosh-Edition/5.02.2022 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) From: David G Conroy Newsgroups: alt.sys.pdp10 Message-ID: References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3A53BEB7.802B5BEF@prescienttech.com> Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 12 Date: Thu, 04 Jan 2001 04:25:04 GMT NNTP-Posting-Host: 207.21.131.106 X-Complaints-To: abuse@verio.net X-Trace: sjc-read.news.verio.net 978582304 207.21.131.106 (Thu, 04 Jan 2001 04:25:04 GMT) NNTP-Posting-Date: Thu, 04 Jan 2001 04:25:04 GMT Organization: Verio Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!merapi!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.cwix.com!sjc-peer.news.verio.net!news.verio.net!sjc-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2413 > In any event, DRAM is now faster than the KL's cache, so one way > of looking at the problem is to "do away with the cache" and simply > run out of a single _very_ fast mainstore (like many supers of the > time did). Although you still need to be a little careful around things like buffered data paths in I/O adapters and interrupts; interrupt wires tend to be out-of-band, and the interrupt request can pass write data. dgc ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 06 Jan 2001 18:45:35 +0100 Organization: My own Private Self Lines: 66 Message-ID: <6uelyg8thc.fsf@chonsp.franklin.ch> References: <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> <6un1d98vl6.fsf@chonsp.franklin.ch> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> <6uu27go5ut.fsf@chonsp.franklin.ch> <931rvf$2i$2@bob.news.rcn.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978803135 2588 10.0.3.2 (6 Jan 2001 17:45:35 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 6 Jan 2001 17:45:35 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2458 Sorry late answer, my provider went offline for 2 days. jmfbahciv@aol.com writes: > In article <6uu27go5ut.fsf@chonsp.franklin.ch>, > Neil Franklin wrote: > >Arthur Krewat writes: > > > >> Neil Franklin wrote: > >> > > >> > Which is why I have decided to wire an KI like hardware and then make > it > >> > possible to run KL programs by having the processor UUO on KL > >> > instructions and then have the UUO run an Macro program that simulates > >> > the KL instructions. > >> > >> What sucked about the KL? Besides microcoding and other useless schemes > >> that wouldn't fit into today's world of FPGA's. > > > >If I remember BAHs anti-KL posts correctly (I can't find them). She > >disliked the "IBMification" of the instruction set that became > >possible (and was done) with microcode. > > No. I never got to the level of microcode so I wouldn't > have stated this. > I suppose I was a bit missunderstandable there. I was referring to some post of yours that the instruction set of the KL had aquired some bloated IBMish instructions, losing the simplicity of KI, and that you disliked KL for that. I assume EDIT to be one of them. The bit about such bloat coming from microcoding is of course my addition, because microcode makes such "subroutines in microcode" attractive to designers. > >> I discussed this a few weeks ago, about adding > >> DZ11 support to Tim Stark's emulator. The (my) answer was to emulate > >> a DZ11 in the emulator, and not hack TOPS-10/20 to take care of it. > > > >That is sure. I want to run 100% unchanged TOPS-10/20. I suppose that > >makes a bit more technology description necessary: > > > Also note that I am not one of these purists that insist > TOPS10 has to run unmodified. I have no objection to a > new CPU device driver (which is how I think of them) getting > written to take advantage of CPU features. But I certainly want to get through with exact old software. > However, the > transition of going from one CPU to another is a complicated > development effort (at least it was when I watched JMF do it). > One of the constraints that we had was to not break all the > other software. Which is why I want full compatibility. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 06 Jan 2001 18:52:54 +0100 Organization: My own Private Self Lines: 36 Message-ID: <6ubstk8t55.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.dontspamme.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <3A4F9C13.4E9C02C3@trailing-edge.com> <92pqre$8ah$2@bob.news.rcn.net> <6uae9bnv9l.fsf@chonsp.franklin.ch> <92sgmh$9dn$2@bob.news.rcn.net> <6un1d98vl6.fsf@chonsp.franklin.ch> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> <6uu27go5ut.fsf@chonsp.franklin.ch> <3A53ACB6.7EE480BE@bartek.dontspamme.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978803574 2588 10.0.3.2 (6 Jan 2001 17:52:54 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 6 Jan 2001 17:52:54 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2459 Arthur Krewat writes: > Neil Franklin wrote: > > > > I certainly was nearly stunned when I did my first fast read the XKL > > docs and found the EDIT instruction. An entire second instruction set, > > triggered by one instruction. Now that is miles away from the elegant > > instruction set of the KI. Really IBMish, or VAXish :-). > > Sounds like something that a newbie did because [s]he didn't want to > mess with the basic instruction set too much - a UUO without the UUO.. > It was handled by the microcode, not the monitor. Yeah, sounds VAXish. More something that is done by someone with a bit of ucode space left and an attempt to reduce instruction from memory fetches. Core was slow. > > > I can't imagine emulating KL instructions under a KI hardware scheme > > > would be "pure" :) > > > > But it may be an neccessary compromise for an non-microcode machine to > > implement some of the more complex KL instructions, or even some of > > the IO (say a complex console terminal (VT100 had an 8080 in it)), or > > even code that replaces the KLs PDP-11/40, like the microcode of the > > XKL does. > > Make it a UART, and the terminal won't need to be emulated, that and some > 1488 and 1489's... you got a PC for a front-end, right? :- Making an PDP-10 clone and then accessing it through an PC? Sort of lacks in "look&feel". I want an directly connected keyboard and monitor. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Message-ID: <3A56EE3B.AC8B6336@jetnet.ab.ca> Date: Sat, 06 Jan 2001 03:06:51 -0700 From: Ben Franchuk X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.18 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.59 X-Trace: 7 Jan 2001 11:16:21 -0700, 207.153.6.59 Organization: OA Internet Lines: 14 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.59 Xref: chonsp.franklin.ch alt.sys.pdp10:2470 Neil Franklin wrote: > I am looking at fairly cheap 100'000 user gates chips for the > beginning, particularly the XC2S200 at $50. That is 100'000 2 input gates I bet. With what little I have played with FPGA's a 4 input gate or bigger takes up 1 or more logic blocks. A 10,000 gate chip (400 logic blocks) would give you 100 12 input nand gates. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk ###### Message-ID: <3A573969.60B11FC9@jetnet.ab.ca> Date: Sat, 06 Jan 2001 08:27:37 -0700 From: Ben Franchuk X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.18 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3A56EE3B.AC8B6336@jetnet.ab.ca> <6uu27b6ml6.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.54 X-Trace: 7 Jan 2001 16:37:04 -0700, 207.153.6.54 Organization: OA Internet Lines: 34 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!newsfeed.direct.ca!look.ca!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.54 Xref: chonsp.franklin.ch alt.sys.pdp10:2483 Neil Franklin wrote: > > Ben Franchuk writes: > Hard technical data is: An XC2S200 has 56x84 (= 4704) logic blocks of > each: AH... details How about a price first ... > - 4-input LUT (= 16bit SRAM) > - section of carry / long AND/OR chain (1 AND + 4 Muxes + 1 XOR) > - direct input selector (1 Mux) > - LUT combiner (1 Mux), allows paring LUTs to 5-input and 6-input > - Flip-Flop for sequential logic > - diverse routing resources to connect to other logic blocks A nice state of the art chip. I have not looked at Xilinx since the only FPGA software I can afford is free software. > So they seem to be calculating about 60'000/4700 = 13 4-transistor > gate-equivalents of average usage per logic block. Seems to be naming > the upper limit of the realistic range. > As I once said in this thread: logic to burn and not enough RAM for > microcode. So that is why I am going for an KI, not an KL, initially. Would splitting it up into TWO chips be an advantage as the data path logic would be similar regardless of how control is generated? Ben. PS. Good luck on the project. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 09 Jan 2001 23:13:38 +0100 Organization: My own Private Self Lines: 55 Message-ID: <6ud7dwtlv1.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3A56EE3B.AC8B6336@jetnet.ab.ca> <6uu27b6ml6.fsf@chonsp.franklin.ch> <3A573969.60B11FC9@jetnet.ab.ca> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 979078418 1890 10.0.3.2 (9 Jan 2001 22:13:38 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 9 Jan 2001 22:13:38 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2534 Ben Franchuk writes: > Neil Franklin wrote: > > > > Ben Franchuk writes: > > > Hard technical data is: An XC2S200 has 56x84 (= 4704) logic blocks of > > each: > AH... details > How about a price first ... Price always last :-) For an raw XC2S200 without anything I do not have a price quote (never looked). But put on an prototype board with the minimal stuff to run put around it and a bit of wire wrap space: $120. http://www.burched.com.au/bedspartan2.html > > - 4-input LUT (= 16bit SRAM) > > - section of carry / long AND/OR chain (1 AND + 4 Muxes + 1 XOR) > > - direct input selector (1 Mux) > > - LUT combiner (1 Mux), allows paring LUTs to 5-input and 6-input > > - Flip-Flop for sequential logic > > - diverse routing resources to connect to other logic blocks > > A nice state of the art chip. I have not looked at Xilinx > since the only FPGA software I can afford is free software. Hold tight to your chair: The JBits toolset I am using is free (as in free beer, not free speach). Yes, Xilinx has had to follow Alteras lead of making MaxPlus free. And JBits is written in Java, so it runs on Linux. The later was the decisive point for me, but the former is nice too. > > As I once said in this thread: logic to burn and not enough RAM for > > microcode. So that is why I am going for an KI, not an KL, initially. > > Would splitting it up into TWO chips be an advantage as the data path > logic would be similar regardless of how control is generated? Not quite sure I understand the way you are splitting it: - 18 bits datapath per chip and then some control on each - all 36 bits datapath in one chip, control in the other At least the later is again the pins problem with 140 user IO pins. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Message-ID: <3A5896E2.8BB7B48F@jetnet.ab.ca> Date: Sun, 07 Jan 2001 09:18:42 -0700 From: Ben Franchuk X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.18 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3A56EE3B.AC8B6336@jetnet.ab.ca> <6uu27b6ml6.fsf@chonsp.franklin.ch> <3A573969.60B11FC9@jetnet.ab.ca> <6ud7dwtlv1.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.53 X-Trace: 9 Jan 2001 15:44:27 -0700, 207.153.6.53 Organization: OA Internet Lines: 32 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.53 Xref: chonsp.franklin.ch alt.sys.pdp10:2537 Neil Franklin wrote: > > http://www.burched.com.au/bedspartan2.html They make nice FPGA kits... looking a Altera kit here sitting by my puter. > Hold tight to your chair: The JBits toolset I am using is free (as in > free beer, not free speach). Yes, Xilinx has had to follow Alteras > lead of making MaxPlus free. Now for OPEN SOURCE tools.:) > And JBits is written in Java, so it runs on Linux. The later was the > decisive point for me, but the former is nice too. > As I once said in this thread: logic to burn and not enough RAM for > microcode. So that is why I am going for an KI, not an KL, initially. Also with that type of decoding you often share states that can help with logic re-use. > > Would splitting it up into TWO chips be an advantage as the data path > > logic would be similar regardless of how control is generated? Off hand I can see about 24 lines for control and a 18 bit address bus and a 36 bit data bus for the ALU chip. Until I get the 500 lbs? of paper schematics and hard copy doc's I will have to make ball park guesses in the logic needed. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk ###### From: inwap@best.com (Joe Smith) Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 17 Jan 2001 11:16:29 GMT Organization: Chez Inwap Lines: 20 Message-ID: <943uud$29sd$1@nntp1.ba.best.com> References: <87r92p7wmq.fsf@k9.prep.synonet.com> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> <6uu27go5ut.fsf@chonsp.franklin.ch> <931rvf$2i$2@bob.news.rcn.net> NNTP-Posting-Host: shell3.ba.best.com X-Trace: nntp1.ba.best.com 979730189 75661 206.184.139.134 (17 Jan 2001 11:16:29 GMT) X-Complaints-To: abuse@best.com NNTP-Posting-Date: 17 Jan 2001 11:16:29 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!merapi!feed2.news.luth.se!luth.se!newspump.monmouth.com!newspeer.monmouth.com!cpk-news-hub1.bbnplanet.com!news.gtei.net!feed2.news.rcn.net!rcn!news2.best.com!nntp1.ba.best.com!inwap Xref: chonsp.franklin.ch alt.sys.pdp10:2684 In article <931rvf$2i$2@bob.news.rcn.net>, wrote: >In article <6uu27go5ut.fsf@chonsp.franklin.ch>, > Neil Franklin wrote: >>If I remember BAHs anti-KL posts correctly (I can't find them). She >>disliked the "IBMification" of the instruction set that became >>possible (and was done) with microcode. > >No. I never got to the level of microcode so I wouldn't >have stated this. I thought that you were of the same mind as those of us who thought that it was an abomination for the KL to implement "convert binary to packed decimal" and "convert binary to EBCDIC" instructions in microcode. Those CV* EXTEND instructions are very IBMish. The name of the COBOL feature, "Business Instruction Set", was a definite reference to Big Blue. -Joe -- See http://www.inwap.com/ for PDP-10 and "ReBoot" pages. ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: Sat, 20 Jan 01 10:14:08 GMT Organization: UltraNet Communications, Inc. Lines: 39 Message-ID: <94bsks$12s$1@bob.news.rcn.net> References: <87r92p7wmq.fsf@k9.prep.synonet.com> <3A5267C9.EC3D4EF0@bartek.dontspamme.net> <6uu27go5ut.fsf@chonsp.franklin.ch> <931rvf$2i$2@bob.news.rcn.net> <943uud$29sd$1@nntp1.ba.best.com> X-Trace: UmFuZG9tSVbeo+NlfhsXRcktlUdtd/FYtXZ0f8nRpHs22Dh7qTmn6O2Nk8AI1Pv2 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 20 Jan 2001 11:26:20 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-245-150 Xref: chonsp.franklin.ch alt.sys.pdp10:2720 In article <943uud$29sd$1@nntp1.ba.best.com>, inwap@best.com (Joe Smith) wrote: >In article <931rvf$2i$2@bob.news.rcn.net>, wrote: >>In article <6uu27go5ut.fsf@chonsp.franklin.ch>, >> Neil Franklin wrote: >>>If I remember BAHs anti-KL posts correctly (I can't find them). She >>>disliked the "IBMification" of the instruction set that became >>>possible (and was done) with microcode. >> >>No. I never got to the level of microcode so I wouldn't >>have stated this. > >I thought that you were of the same mind as those of us who thought that >it was an abomination for the KL to implement "convert binary to packed >decimal" and "convert binary to EBCDIC" instructions in microcode. I never worked at that detail level, so I wouldn't have had any informed opinion of it. > >Those CV* EXTEND instructions are very IBMish. >The name of the COBOL feature, "Business Instruction Set", was a >definite reference to Big Blue. Perhaps that was done to compete with IBM main frame business. We had been losing sales because we couldn't handle large (and I mean large) data bases that were encountered in bids with companies whose business was accounting-type processing. Jim did an on-site meeting with an insurance company in Hartford, Connecticut one time. He came back awed because they had one file that took up (I don't remember the exact number here) something like a hundred RP06s. We didn't get that bid. There was a impetus to handle transaction processing. JMF and CDO wrote an architectural specification to get DEC started in that aspect of the computing business. /BAH Subtract a hundred and four for e-mail. ###### Sender: prep@k9 Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <6ug0j2kcv9.fsf@chonsp.franklin.ch> <3A6E5B55.CA26B26D@MA.UltraNet.Com> From: Paul Repacholi Date: 11 Feb 2001 00:42:28 +0800 Message-ID: <87bssatrpn.fsf@prep.synonet.com> Lines: 12 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 149.d01.pe.iqnet.net.au X-Trace: 10 Feb 2001 23:58:19 +0800, 149.d01.pe.iqnet.net.au Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!Amsterdam.Infonet!News.Amsterdam.UnisourceCS!skynet.be!hermes.visi.com!news-out.visi.com!newsfeed.wirehub.nl!news-out.nuthinbutnews.com!news-in-austin.nuthinbutnews.com!feed2.newsfeeds.com!newsfeeds.com!newsfeed.iinet.net.au!news.waia.asn.au!usenet.per.paradox.net.au!127.0.0.1!nobody Xref: chonsp.franklin.ch alt.sys.pdp10:2926 For the info of the FPGA interested... There is a HDL tool for Linux just apeared on source forge, from POlybus.com. Free, and open source. You may want to have a look. They also have a set of pointers of other design tools. -- Paul Repacholi 1 Crescent Rd., +61 (08) 9257-1001 Kalamunda. West Australia 6076 Raw, Cooked or Well-done, it's all half baked. ###### Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <6ug0j2kcv9.fsf@chonsp.franklin.ch> <3A6E5B55.CA26B26D@MA.UltraNet.Com> <87bssatrpn.fsf@prep.synonet.com> From: Ric Werme X-Newsreader: NN version 6.5.0 CURRENT #119 Lines: 16 Message-ID: <4Sih6.4629$bK4.2494236@typhoon.ne.mediaone.net> Date: Sat, 10 Feb 2001 22:00:32 GMT NNTP-Posting-Host: 24.91.12.32 X-Complaints-To: abuse@mediaone.net X-Trace: typhoon.ne.mediaone.net 981842432 24.91.12.32 (Sat, 10 Feb 2001 17:00:32 EST) NNTP-Posting-Date: Sat, 10 Feb 2001 17:00:32 EST Organization: Road Runner Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newsxfer.eecs.umich.edu!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!chnws02.mediaone.net!chnws05.ne.mediaone.net!24.128.8.202!typhoon.ne.mediaone.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2943 Paul Repacholi writes: >For the info of the FPGA interested... >There is a HDL tool for Linux just apeared on source forge, from >POlybus.com. Free, and open source. You may want to have a look. [Warning, discussion heading off track!] Oh gee, I may be having dinner with the principals of Polybus Monday PM. (Monthly dinner for some of the Alliant Computer engineering alumni.) I'm sure I could steer the conversation around to PDP-10s, though I guess I'm the only one with extensive experience. OTOH, half the OS group at Alliant did. Our kernel debugger used the DDT manual as a starting point. -- Ric Werme | werme@nospam.mediaone.net http://people.ne.mediaone.net/werme | ^^^^^^^ delete ###### From: "Heinz Wolter" Newsgroups: alt.sys.pdp10 References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <6ug0j2kcv9.fsf@chonsp.franklin.ch> <3A6E5B55.CA26B26D@MA.UltraNet.Com> <87bssatrpn.fsf@prep.synonet.com> Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Lines: 21 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Wed, 14 Feb 2001 17:15:36 GMT NNTP-Posting-Host: 64.230.141.65 X-Trace: news20.bellglobal.com 982170936 64.230.141.65 (Wed, 14 Feb 2001 12:15:36 EST) NNTP-Posting-Date: Wed, 14 Feb 2001 12:15:36 EST Organization: Sympatico Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newshub2.rdc1.sfba.home.com!news.home.com!news-out.usenetserver.com!news-out.usenetserver.com!news3.bellglobal.com!nf2.bellglobal.com!news20.bellglobal.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:3072 I could find any references to this tool on google search. Do you have a package name or url? reagards, Heinz "Paul Repacholi" wrote in message news:87bssatrpn.fsf@prep.synonet.com... > > For the info of the FPGA interested... > > There is a HDL tool for Linux just apeared on source forge, from > POlybus.com. Free, and open source. You may want to have a look. > They also have a set of pointers of other design tools. > > -- > Paul Repacholi 1 Crescent Rd., > +61 (08) 9257-1001 Kalamunda. > West Australia 6076 > Raw, Cooked or Well-done, it's all half baked.