Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: FPGA clone status, 3rd milestone reached Date: 26 Jun 2002 00:37:57 +0200 Organization: My own Private Self Lines: 203 Message-ID: <6uy9d3assa.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1025044679 1676 10.0.3.2 (25 Jun 2002 22:37:59 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 25 Jun 2002 22:37:59 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:11538 It is time to announce the 3rd milestone. Time so far has been 5.5 months for the first, 6.5 for the second, and now back to 5.5 for the third. Without big time losses (4 weekends, 2 of then 4 day ones) to other hobbies that could have been 1 month less (and as planned for). Targets for third milestone Make design more flexible and faster to change and implement third and fourth instruction groups leading to 4 of 8 groups of 64 being done, i.e. 1/2 of all instructions, 2/3 of user level ones. That turned out to be: - rework my programming style to make changes easier - make code independent of LUT position within an CLB - abstract from raw JBits API as it is too literal and slowing - get rid of F/G dependant need for dual code and resulting copy/edit bugs - allow using all colums of the FPGA, not waisting 1/3 of space - automatic allocation system for selecting next free LUT for use - systematic naming of LUTs and their inputs to make code more readable - generate an Assembly-like listfile of LUT places/content - start using an Makefile to coordinate all the (re-)compiling stuff - separate memory and fast memory and decoding/selecting between them - side effect this allowed to go from 32 to 48 words of memory space - extend instruction repertoire - designed and implemented the 101tootmm (HLL*, HRL*, HRR* HLR*) instructions - designed and implemented the 110ooamma (TL*, TR*, TD*, TS*) instructions - went back to using the old program file format, used in the 1st milestone - extended test program to use them using the extra 16 words of memory The announced multiple read port (speed) stuff has been pushed back to later times, to be optimisations after the basic design runs. Test program The mentioned extended program and data are thus: ------ 000000000000000000000000000000000000 - 00 ; Projects/PDP-10/pdp10.mem 111111111111111111111111111111111111 ; memory image for pdp10.java|.class 010101010101010101010101010101010101 ; author Neil Franklin 001100110011001100110011001100110011 ; last modification 2002.06.25 000111000111000111000111000111000111 000011110000111100001111000011110000 ; 00..07 data regs for C(MA) 000001111100000111110000011111000001 000000111111000000111111000000111111 000000000000000000000000000000000001 - 10 ; 10..13 index regs, for MA(IR.X) 000000000000000000000000000000000010 000000000000000000000000000000000100 000000000000000000000000000000001000 001110010101010100001010111110110000 ; 14..17 data space, for C(AC) 001001010101101101100010110111000111 ; to process and overwrite 100101011101110000000110110111100001 001111010101000001110110111000000110 100000000110000000000000000000000001 - 20 ; SETZ 14,1 Set Zero 100000101110100000010010110001100100 ; AND I 15,226144 And 100001010111000000000000000000000010 ; ANDCA M 16,2 And Compl Acc 100001111110000000000000000000000100 ; SETM B 14,4 Set Memory 100010000110101000000000000000000010 ; ANDCM 15,2(10) And Compl Mem 100010101111001001000000000000000101 ; SETA I 16,5(11) Set Accu 100100010111010000000000000000000110 ; ANDCB M 16,@7 And Compl Both 100100111110010000000000000000000010 ; EQV B 14,@2 Equivalent 101000000111000000000000000000000010 - 30 ; HLL 16,2 Half Left Left 101001100110100000000000000000000101 ; HRL Z 15,5 HLR Zero 101110000110000000000000000000000111 ; HRR O 14,7 HRR Ones 101111100111100000000000000000000001 ; HLR E 17,1 HRL Extent Top 101000001110000000001011010110100110 ; HLL I 14,132646 HLL Immediate 101000110110100000000000000000000011 ; HRL M 15,3 HRL Memory 101100011111101011000000000000000100 ; HRR S 17,4(13) HRR Self 101110110111000000000000000000000110 ; HLR O M 16,6 HRL Ones Memory 110000000110100000101110000101100011 -40 ; TR N 15,560543 Test Right Nowri 110010001111000000010010111001000110 ; TL Z 16,227106 Test Left Zero 110101000110000000000000000000000101 ; TD C 14,5 Test Direc Compl 110111001111100000000000000000001111 ; TS O 17,17 Test Swap Ones 110000010110000000000011101101000010 ; TR N E 14,035502 TRN Skip Equal 110000101111000000111101001100010000 ; TL N A 16,751420 TLN Skip Always 110001110110101001000000000000000100 ; TD N N 15,4(11) TDN Skip Not Eq 110101111111100000000000000000000111 ; TS C A 17,7 TSC Skip Not Eq 011000011111100000000100101001101000 - 50 ; CAI LE 17,45150 Comp AC Imm Skip 011001010111000000000000000000000100 ; CAM E 16,4 Comp AC Mem Skip 011011001110100000000000000000000011 ; SKIP L 15,3 Comp Mem Ze Skip 011101000110001010000000000000000110 ; AOS 14,6(12) Add One Mem Skip 011111111111100000000000000000000001 ; SOS G 17,1 Sub One Mem Skip 011100110000100000000000000000101010 ; AOJ N 1,52 Add One AC Jump 011110101110100000000000000000101001 ; SOJ GE 15,51 Sub One AC Jump 011010100110000000000000000000100000 - 57 ; JUMP A 14,40 Comp AC Ze Jump 0 1 2 3 ; bit no 012345678901234567890123456789012345 OOOOOOOOOAAAAIXXXXYYYYYYYYYYYYYYYYYY ; pdp10 instruction format 011tttmmm ; arith test instr sub-format 100ffffmm ; boolean logic instr sub-format 101tootmm ; half word instr sub-format 110ooamma ; bit testing instr sub-format ------ The program counter starts at the last word (057), as with real read-in. Speed of the present design Stayed exactly the same. It is intended to stay so until the first complete design is done. Only after will I be going for more speed. Functioning system has priority. Target change Originally I aimed for an KI-10 for the first implementation. I have changed this first target to be an KA-10. I originally chose KI-10 because: - it was the original synchronous state logic design (KA-10 is async state, KL-10 is sync microcoded logic), but my implementation is different to all anyway - for the best console layout, but I can also use an KI-10 style console on an KA-10 instruction/feature set machine I have changed because: - the KI-10s 4 register sets (needed for full binary compatibility, which I want for the first design) cuts too strongly into my availabe chip space - there seems to be no KI-10 specific OS around, TOPS-10 6.x is still KA-10 only, 7.0 was KI-10, 7.01 KL-10 (and only 7.03/7.04 survive), ITS was KA-10 and then direct KL-10, TOPS-20 is KL-10B minimum - the KA-10 base and offset memory managment is less stuff to through away when going for KL-10B/XKL-1 extended address paged memory management Archive of this milestone I have archived this third milestone as: http://neil.franklin.ch/Projects/PDP-10/Milestone-20020625/ The second milestone remains archived at: http://neil.franklin.ch/Projects/PDP-10/Milestone-20011229/ The first milestone remains archived at: http://neil.franklin.ch/Projects/PDP-10/Milestone-20010516/ Current working state is still at: http://neil.franklin.ch/Projects/PDP-10/ For the first 2 status reports see: http://neil.franklin.ch/Usenet/alt.sys.pdp10/20010516_FPGA_clone_status_1st_milestone_reached http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011230_FPGA_clone_status_2nd_milestone_reached Detailled ongoing logfile of progress is at: http://neil.franklin.ch/Projects/PDP-10/Logfile Targets for fourth Milestone - further improving programming style towards faster work - rework the awfull code in Mam section - larger 512 or 1024 word BRAM based memory for larger test programs together with the needed wait state handling - design and implement the 010xxxxxx fixed point and stack instructions this is a large group, as they are multiple subgroups - possibly: with all user instruction (excluding float and byte) done, first KLAD testes as far as they will run Job situation The problem with my job mentioned at the end of the 2nd state report is solved: I went and got myself a new job, new employer and different work. Started it on 1st Mai. Just the outlook to the change from 1st Feb on speed up this work wonderfully. VirtexTools Sister project I have been not particularly satisfied with the tools I am using, and the entire FPGA tool situation sucks. I need some more and better tools. So I am going to make them myself. See the beginnings of them in the above mentioned abstracting from JBits API. To enable this without delaying this work I have taken my new job at 40% (2 days per week), whereas old one was 80% (4 days). My new employer is even interested in using this sister project, as soon as it is usable for actual work. So I will then go up to 60% while working 1 day on it and the other 2 on my present work. Expect to see first results of this project in form of commented colour graphics of the FPGA contents. Ideal for documenting what goes on in these chips and helping others learn to work with them. This project can be found at: http://neil.franklin.ch/Projects/VirtexTools/ Its detailled ongoing logfile of progress is at: http://neil.franklin.ch/Projects/VirtexTools/Logfile -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domain ###### From: "Zane H. Healy" Newsgroups: alt.sys.pdp10 Subject: Re: FPGA clone status, 3rd milestone reached Date: 26 Jun 2002 01:32:14 GMT Organization: Aracnet Lines: 7 Message-ID: References: <6uy9d3assa.fsf@chonsp.franklin.ch> NNTP-Posting-Host: p-279.newsdawg.com User-Agent: tin/1.4.4-20000803 ("Vet for the Insane") (UNIX) (Linux/2.2.19 (i686)) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!proxad.net!proxad.net!216.148.52.16.MISMATCH!pln-e!spln!dex!extra.newsguy.com!newsp.newsguy.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:11544 Neil Franklin wrote: > It is time to announce the 3rd milestone. Awsome! I look forward to eventually being able to boot an OS on an FPGA clone system! Zane ###### Reply-To: "Henry Miller" From: "Henry Miller" Newsgroups: alt.sys.pdp10 References: <6uy9d3assa.fsf@chonsp.franklin.ch> Subject: Re: FPGA clone status, 3rd milestone reached Lines: 57 Organization: What? You mean someone organized this? X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: Date: Fri, 28 Jun 2002 15:58:32 GMT NNTP-Posting-Host: 12.81.77.85 X-Complaints-To: abuse@worldnet.att.net X-Trace: bgtnsc05-news.ops.worldnet.att.net 1025279912 12.81.77.85 (Fri, 28 Jun 2002 15:58:32 GMT) NNTP-Posting-Date: Fri, 28 Jun 2002 15:58:32 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!wn1feed!worldnet.att.net!bgtnsc05-news.ops.worldnet.att.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:11543 Neil, Great work, but one thing is not as cloudy as you think: "Neil Franklin" wrote in message news:6uy9d3assa.fsf@chonsp.franklin.ch... > It is time to announce the 3rd milestone. > > Time so far has been 5.5 months for the first, 6.5 for the second, and > now back to 5.5 for the third. Without big time losses (4 weekends, 2 > of then 4 day ones) to other hobbies that could have been 1 month less > (and as planned for). > [snip] > Target change > > Originally I aimed for an KI-10 for the first implementation. I have > changed this first target to be an KA-10. > > I originally chose KI-10 because: > - it was the original synchronous state logic design (KA-10 is async > state, KL-10 is sync microcoded logic), but my implementation is > different to all anyway > - for the best console layout, but I can also use an KI-10 style > console on an KA-10 instruction/feature set machine > > I have changed because: > - the KI-10s 4 register sets (needed for full binary compatibility, > which I want for the first design) cuts too strongly into my availabe > chip space > - there seems to be no KI-10 specific OS around, TOPS-10 6.x is still No, I know at least 6.03A ran on at least the KI, KL & KS. I don't recall if it ran on the KA. It probably did, as a goodbye OS. > KA-10 only, 7.0 was KI-10, 7.01 KL-10 (and only 7.03/7.04 survive), 7.0 was a LIR for KI & KL SMP. 7.01 ran on the later processors, namely the KI, KL & KS, and was the last monitor to support KI-only paging on the KL and KS. IIRC, 7.02 offered either KL or KI paging on the KL and KS; 7.03 would be KL paging only, which would mean that 7.02 was the last KI monitor. > ITS was KA-10 and then direct KL-10, TOPS-20 is KL-10B minimum > - the KA-10 base and offset memory managment is less stuff to through > away when going for KL-10B/XKL-1 extended address paged memory > management > > [SNIP] -HWM ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: FPGA clone status, 3rd milestone reached Date: 28 Jun 2002 22:49:41 +0200 Organization: My own Private Self Lines: 40 Message-ID: <6uvg83ruvu.fsf@chonsp.franklin.ch> References: <6uy9d3assa.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1025297381 525 10.0.3.2 (28 Jun 2002 20:49:41 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 28 Jun 2002 20:49:41 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:11550 "Henry Miller" writes: > Great work, but one thing is not as cloudy as you > think: One of ther person also mailled me the same info privately. So with two of you, I can consider this issue differently. > "Neil Franklin" wrote in message > > > > - there seems to be no KI-10 specific OS around, TOPS-10 6.x is still > > No, I know at least 6.03A ran on at least the KI, KL & KS. I don't > recall if it ran on the KA. It probably did, as a goodbye OS. So that makes 6.03A the most universal. And IIRC that is one of the surviving versions on Shoppas site. > > KA-10 only, 7.0 was KI-10, 7.01 KL-10 (and only 7.03/7.04 survive), > > 7.0 was a LIR for KI & KL SMP. 7.01 ran on the later processors, > namely the KI, KL & KS, and was the last monitor to support KI-only > paging on the KL and KS. IIRC, 7.02 offered either KL or KI paging > on the KL and KS; 7.03 would be KL paging only, which would mean > that 7.02 was the last KI monitor. Still will though aim for KA-10 (simplest and fastest to reach first, enough for TOPS-10) and then most likely go directly to an full KL-10 style addressing (large address space, most powerfull, will run TOPS-20) or direct to XKL-1 style (maximum version). That is of course preliminary planning. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domain