Index of /Usenet/comp.arch.fpga

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[   ]00000000_all_posts.tar.gz2003-12-23 21:41 26M 
[   ]20031217_From_FPGA_to_ASIC_these_days2003-12-22 16:43 6.3K 
[   ]20031210_Soldering_of_FPGAs2003-12-21 15:45 38K 
[   ]20031212_advantages_of_ethernet_MAC_ip_core2003-12-21 15:44 20K 
[   ]20031216_From_ASIC_to_FPGA_these_days2003-12-19 21:49 5.4K 
[   ]20031125_Slightly_unmatched_UART_frequencies2003-12-05 21:46 96K 
[   ]20031125_5V_I_O_with_1_8V_Core2003-12-02 02:03 54K 
[   ]20031123_Laptop_without_serial_parallel_port2003-11-26 23:45 15K 
[   ]20031120_Xilinx_legacy_situation2003-11-25 00:57 44K 
[   ]20031121_Xilinx_WebPack_and_Linux_WINE2003-11-23 20:37 3.0K 
[   ]20031119_Small_PLD_choices2003-11-21 21:43 25K 
[   ]20031110_Layout_examples2003-11-14 21:11 47K 
[   ]20030908_Xilinx_S3_I_O_robustness_question2003-11-13 01:33 208K 
[   ]20031109_Home_grown_CPU_core_legal2003-11-13 01:25 94K 
[   ]20031028_What_s_a_good_book_on_FPGA_CPU_design2003-10-29 00:50 4.0K 
[   ]20031008_Visualizing_VHDL2003-10-26 22:58 27K 
[   ]20031015_USB_transceiver_for_FPGA2003-10-26 22:49 38K 
[   ]20031022_The_Luddite_Needs_Reference_Books2003-10-26 22:40 9.7K 
[   ]20030926_Reducing_Clock_Speed2003-10-26 22:29 37K 
[   ]20030908_Programming_Xilinx_CPLD_under_linux2003-10-26 22:26 6.9K 
[   ]20030917_platform_flash_as_storage2003-10-26 22:24 11K 
[   ]20030919_ORCA_fpga2003-10-26 22:17 18K 
[   ]20031018_ISE_6_1_and_Redhat_92003-10-26 22:10 32K 
[   ]20031003_Interesting_article_about_FPGAs2003-10-26 22:05 52K 
[   ]20031007_Installing_Xilinx_6_1_under_Linux2003-10-26 21:48 13K 
[   ]20031009_Floorplanning_Routing_FPGA_Editor2003-10-26 21:42 18K 
[   ]20031014_Electronic_Dice_3_die_In_VHDL2003-10-26 21:38 75K 
[   ]20031021_74_logic_to_CPLD_how_easy_for_a_Newbie2003-10-26 21:15 38K 
[   ]20030917_Xilinx2003-10-02 21:38 57K 
[   ]20030924_Regulator_for_Spartan_22003-10-01 19:41 24K 
[   ]20030922_FPGA_implementation_in_V_HDL2003-10-01 19:38 23K 
[   ]20030922_Regarding_XC62162003-09-25 21:13 22K 
[   ]20030919_LVDS_in_Xilinx_Spartan_32003-09-20 17:47 9.4K 
[   ]20030910_Crystal_Input_to_FPGA2003-09-13 20:45 34K 
[   ]20030907_CMOS_camera_w_USB2_crazy2003-09-13 20:44 63K 
[   ]20030905_Sending_and_receiving_Ethernet_traffic2003-09-11 21:58 16K 
[   ]20030909_cpld_s_in_a_DIL_package_available2003-09-10 00:33 1.0K 
[   ]20030823_Thinking_out_loud_about_metastability2003-09-07 14:54 224K 
[   ]20030903_How_to_extend_a_pulse_width_without_clock2003-09-06 14:41 9.3K 
[   ]20030904_More_about_metastability2003-09-04 20:50 6.0K 
[   ]20030826_How_to_listen_to_music_through_an_FPGA_pin2003-09-01 15:23 16K 
[   ]20030812_Datasheet_for_National_PAL20L102003-08-29 00:28 9.3K 
[   ]20030825_Lithium_cell_on_Virtex2_Pro2003-08-28 22:13 11K 
[   ]20030825_FPGA_minimum_operating_frequencies2003-08-26 21:07 8.7K 
[   ]20030819_Async_logic_in_FPGAs2003-08-23 16:31 20K 
[   ]20030811_Virtex_Virtual_VCC2003-08-13 00:22 7.7K 
[   ]20030809_DDR_ram_interface_xapp2002003-08-11 19:04 11K 
[   ]20030804_Virtual_Grounds2003-08-06 23:37 9.7K 
[   ]20030803_Unused_Pins_on_big_Virtex_II2003-08-03 18:19 5.9K 
[   ]20030725_Reseting_the_whole_thing2003-07-25 21:23 23K 
[   ]20030724_Active_Probe2003-07-25 21:19 11K 
[   ]20030711_Graduation_Day_My_first_4_layer_PCB2003-07-22 00:37 92K 
[   ]20030712_edge_card_connectors_and_high_speed_design2003-07-16 17:45 8.9K 
[   ]20030714_Virtex_Bitstream_verification2003-07-13 21:07 2.3K 
[   ]20030629_SPARTAN_3_vs_VIRTEX_II2003-07-09 15:56 54K 
[   ]20030707_Spartan_XL_Tool_Support2003-07-08 00:15 4.3K 
[   ]20030625_Xilinx_Webpack_bugs_bugs_bugs2003-06-30 18:25 176K 
[   ]20030626_Free_PAL_synth_tools2003-06-27 21:53 15K 
[   ]20030625_GAL16V8_reverse_compilation2003-06-26 22:07 5.8K 
[   ]20030626_content_of_a_LUT2003-06-26 21:50 4.1K 
[   ]20030623_Q_regarding_I2C_protocols2003-06-25 01:30 52K 
[   ]20030623_JBits_and_Virtex_II_Pro2003-06-24 01:51 2.3K 
[   ]20030622_Ethernet_only_network2003-06-23 21:38 6.0K 
[   ]20030613_Problem_with_tristate_inout_pins_of_PS_2_Host2003-06-17 15:51 11K 
[   ]20030616_BGA_Xray_inspection_costs2003-06-17 15:41 8.7K 
[   ]20030613_PDP11_40_Compatible_CPU_on_an_FPGA2003-06-13 20:56 3.2K 
[   ]20030610_What_s_in_a_bitstream2003-06-11 20:49 16K 
[   ]20030610_Cheap_development_tools2003-06-11 20:45 7.6K 
[   ]20030518_Mini_solder_masks2003-05-18 23:51 3.0K 
[   ]20030508_accurate_power_measurements2003-05-10 14:51 11K 
[   ]20030501_Schmitt_Trigger_an_a_Virtex2003-05-05 19:33 12K 
[   ]20030414_ISE_WebPack_under_Linux_use_of_command_line_tools2003-04-20 22:57 11K 
[   ]20030415_Selling_CPU_cores2003-04-16 21:10 12K 
[   ]20030414_request for simple UART2003-04-16 01:44 32K 
[   ]20030410_Ethernet_MAC2003-04-12 21:53 5.5K 
[   ]20030317_Cheapest_Spartan_II_IIE_configuration_flash_EEPROM2003-03-20 22:16 13K 
[   ]20030314_Xilinx_WebPACK_on_WINE_getting_close2003-03-16 01:19 11K 
[   ]20030313_Xilinx_Looking_for_Parallel_Cable_III2003-03-14 21:56 21K 
[   ]20021210_State_of_the_PCB_world2003-03-11 23:23 52K 
[   ]20030225_Licencing_for_downloadable_FPGA_tools2003-02-27 23:12 36K 
[   ]20030218_PCB_Design_for_a_Xilinx_Spartan_II_FPGA2003-02-21 21:28 27K 
[   ]20030210_JBits2003-02-14 23:17 18K 
[   ]20030206_debounce_circuit2003-02-08 00:26 7.3K 
[   ]20030128_PCI_protocol_assigning_an_address_to_my_device2003-02-05 23:46 23K 
[   ]20030203_Difference_between_CPLD_FPGA_ASICS2003-02-05 18:59 11K 
[   ]20030128_Clock_Feedback_for_DDR_SDRAM2003-02-04 18:46 10K 
[   ]20030129_GNU_C_for_custom_processor2003-02-02 21:45 17K 
[   ]20030116_Support_for_older_Virtex2003-01-19 00:09 13K 
[   ]20030110_Spartan_2_reset_sync_or_async2003-01-13 21:02 8.4K 
[   ]20030108_USB_OPENCORE_IP_usage2003-01-08 19:44 8.5K 
[   ]20021231_Unused_FPGA_I_O_Pins2003-01-06 14:46 11K 
[   ]20021220_Hi_xilinx2002-12-23 21:33 21K 
[   ]20021218_Async_RAM_on_an_FPGA_board2002-12-23 21:31 47K 
[   ]20021219_virtex_output_pin_voltage2002-12-09 23:20 4.1K 
[   ]20021031_FPGA_convert_to_ASIC2002-11-11 23:00 17K 
[   ]20021108_Xilinx_LUT_based_FPGAs2002-11-09 23:15 5.4K 
[   ]20021021_Newbie_Questions_Jan_Gray_XSOC2002-10-23 19:42 50K 
[   ]20021018_Floorplanner_RPM_How_to_use_it2002-10-23 19:22 93K 
[   ]20021020_6502_core_available2002-10-23 19:18 27K 
[   ]20021018_Size_of_configuration_bitstream_for_xcv502002-10-21 22:05 16K 
[   ]20020925_PCB_Design_for_Altera_FPGA2002-10-19 16:02 23K 
[   ]20021012_Open_Source_and_other_issues2002-10-19 16:00 96K 
[   ]20021008_Why_can_Xilinx_sw_be_as_good_as_Altera_s_sw2002-10-18 22:58 379K 
[   ]20021010_Sync_Reset_without_clocks2002-10-15 20:09 25K 
[   ]20021015_GCK_as_normal_IO2002-10-15 19:57 4.7K 
[   ]20021009_Why_can_t_Altera_sw_be_as_good_as_Xilinx_s_sw2002-10-13 21:03 49K 
[   ]20021001_USB2_in_FPGA2002-10-09 23:04 44K 
[   ]20021003_Low_power_design2002-10-07 19:52 51K 
[   ]20021001_Rounting_of_non_global_IO_pad_to_a_GCLKIOB_site2002-10-02 21:00 16K 
[   ]20020927_Block_Ram_maximum_speed2002-09-28 21:03 9.8K 
[   ]20020921_Can_a_fpga_replace_external_inverters_in_a_crystal_osc2002-09-28 00:14 23K 
[   ]20020921_Spartan_II_JTAG_reconfiguration_bug_workaround2002-09-25 21:32 25K 
[   ]20020921_external_switch_to_CPLD_input2002-09-24 00:18 8.8K 
[   ]20020920_Overheat_with_XCV_600E2002-09-23 20:19 14K 
[   ]20020920_Silicon_lifetime2002-09-21 21:56 5.0K 
[   ]20020918_using_CPLD_s_inverter_in_oscillator_circuit2002-09-19 22:39 11K 
[   ]20020916_Readback_size_for_virtex22002-09-17 22:30 4.9K 
[   ]20020910_FPGA_comes_with_a_DAC2002-09-14 20:55 13K 
[   ]20020906_Metastability_numbers2002-09-11 20:40 54K 
[   ]20020909_minimalist_FPGA_system2002-09-11 00:31 25K 
[   ]20020906_Virtex_II_bit_file_and_strange_configuration_command2002-09-10 14:57 8.9K 
[   ]20020830_XNF_vs_EDIF2002-08-30 21:46 5.4K 
[   ]20020813_RBT_versus_BIT_file2002-08-14 00:56 4.5K 
[   ]20020805_Soundchip2002-08-07 01:32 18K 
[   ]20020805_Qn_Low_Level_Design2002-08-07 01:30 4.0K 
[   ]20020802_Silicon_Area_for_Xilinx_FPGAs2002-08-03 20:23 11K 
[   ]20020715_Spartan_clock_mirroring2002-07-16 14:34 4.6K 
[   ]20020713_serial_configuration_in_parallel_Xilinx_Spartan_II2002-07-14 12:32 5.1K 
[   ]20020713_What_proportion_of_an_FPGA_s_configuration_data_is_used_for_routing2002-07-14 02:29 6.0K 
[   ]20020704_Maximum_frequency_in_Virtex_and_Virtex_E_Devices2002-07-05 22:09 13K 
[   ]20020702_Bitstream_Verification_JBITS2002-07-05 22:02 12K 
[   ]20020618_5V_tolerance2002-07-01 02:03 81K 
[   ]20020626_Virtex_E_Readback2002-06-28 23:07 4.4K 
[   ]20020624_too_hot_fpga_device2002-06-28 23:04 16K 
[   ]20020616_new_computer2002-06-24 23:13 59K 
[   ]20020624_book_recommenation2002-06-24 22:57 1.9K 
[   ]20020610_Power_supply_caps_on_PCB2002-06-22 17:58 59K 
[   ]20020617_Internal_oscillator_in_CPLD2002-06-19 19:44 17K 
[   ]20020607_Doing_Trig_Functions_in_FPGA_EPLD2002-06-09 20:59 15K 
[   ]20020603_divide_by_52002-06-09 20:54 39K 
[   ]20020603_FPGA_destruction_possible2002-06-07 22:57 29K 
[   ]20020523_Xilinx_proprietary_format2002-05-30 00:21 7.0K 
[   ]20020522_Routing_in_a_6200_like_sea_of_gates2002-05-22 23:01 8.5K 
[   ]20020513_Architecture_for_high_level_reconfigurable_computing2002-05-22 22:36 120K 
[   ]20020516_Bidirectional_DONE2002-05-20 22:38 9.1K 
[   ]20020513_50_mA_sink2002-05-20 22:29 4.5K 
[   ]20020505_Xilinx_IOBUF2002-05-06 21:48 18K 
[   ]20020430_Virtex_Evolution2002-05-02 22:36 9.9K 
[   ]20020413_new_to_fpga_s_need_insight2002-04-16 00:41 39K 
[   ]20020412_DDR_SDRAM_Controller2002-04-13 14:10 9.2K 
[   ]20020404_hand_placement2002-04-12 23:36 155K 
[   ]20020410_ChipScope_ILA_cable_requirements2002-04-12 23:25 6.0K 
[   ]20020312_powerpc_in_virtex2pro2002-04-08 23:18 104K 
[   ]20020327_Partial_Reconfiguration2002-03-28 23:52 13K 
[   ]20020315_High_speed_clock_routing2002-03-27 23:40 196K 
[   ]20020319_1_5V_power_supply2002-03-20 22:39 6.4K 
[   ]20020318_questions_from_a_newby2002-03-18 21:42 8.8K 
[   ]20020306_Using_a_battery_instead_of_Config_device2002-03-07 21:30 5.9K 
[   ]20020301_Xilinx_Virtex_Family_die_photos2002-03-05 23:41 4.9K 
[   ]20020228_stuck_in_state_in_Spartan_II2002-03-02 23:28 41K 
[   ]20020225_Comparison_between_two_FPGA_what_is_decisive_factor2002-03-02 23:11 12K 
[   ]20020301_Clock_multiplier_ADPLL_in_PLD2002-03-02 23:09 13K 
[   ]20020227_SDRAM_FPGA2002-02-28 21:07 3.8K 
[   ]20020206_Pseudorandom_Bitstream2002-02-20 21:34 76K 
[   ]20020210_Xilinx_EDIF_to_BIT_transation2002-02-13 00:18 17K 
[   ]20020204_Virtex_II_and_SDRAM_Controller_at_133MHz2002-02-07 22:33 13K 
[   ]20020206_designing_a_protocol_analyzer_for_proprietary_serial_bus2002-02-07 22:30 4.8K 
[   ]20020205_FPGA_SDRAM_Groundbounce_Latchup_Possible2002-02-07 22:25 20K 
[   ]20020129_Soft_errors_climb_in_0_13u_SRAM2002-02-03 20:23 10K 
[   ]20020130_Java_or_bytecode_processors2002-02-03 20:04 14K 
[   ]20020113_Homebrew_computers_using_FPGA2002-02-03 20:00 31K 
[   ]20020128_glitchless_clock_enable_disable_in_spartanII2002-02-03 19:53 57K 
[   ]20020128_configuring_an_FPGA_from_an_Hard_drive_with_a_80c512002-02-03 19:14 28K 
[   ]20020124_Dynamic_Reconfiguration_of_single_Xilinx_FPGA2002-01-25 22:56 30K 
[   ]20020122_Virtex_II_Programming_Highs_and_Lows2002-01-23 21:51 18K 
[   ]20020118_DDR_Interface2002-01-21 21:11 11K 
[   ]20020117_Virtex2_ICAP2002-01-18 22:48 4.8K 
[   ]20020111_Xilinx_PAR_and_Editor_speed_up2002-01-14 20:47 12K 
[   ]20020108_latch_vs_register2002-01-13 22:25 22K 
[   ]20020109_Spartan_IIE_pinout_compatibililty_with_Virtex_E2002-01-10 21:27 8.2K 
[   ]20020103_Spartan_IIE_interfacing_issues2002-01-06 00:36 8.9K 
[   ]20011221_CE_on_XILINX_FFs_and_Metastability2001-12-22 23:57 13K 
[   ]20011218_Barrel_shifter_puts_three_2_1_muxes_slice_in_Xilinx2001-12-22 23:54 49K 
[   ]20011221_16_5_multiplier_uses_new_multiply_algorithm2001-12-22 23:40 10K 
[   ]20011219_Low_area_barrel_shift_puts_3_to_1_mux_in_a_Xilinx_LUT2001-12-19 23:11 38K 
[   ]20011219_Efficient_new_multiplier_for_Spartan2_Virtex_c2001-12-19 23:03 8.4K 
[   ]20011218_Divide_by_3_with_remainder_efficient_and_fast_for_Altera_or_Xilinx2001-12-19 23:02 42K 
[   ]20011216_Multiplying_by_squaring_using_Block_RAM2001-12-17 22:09 7.3K 
[   ]20011206_where_is_designed_FPGA_for_apple_II_computer2001-12-13 13:42 30K 
[   ]20011130_What_do_you_like_dislike_about_place_and_route_tools2001-12-13 13:41 53K 
[   ]20011208_ISA_syncronization2001-12-13 13:40 19K 
[   ]20011128_SpartanIIE2001-12-10 21:23 25K 
[   ]20011203_Crossing_a_clock_domain2001-12-06 21:42 24K 
[   ]20011128_Is_there_a_full_open_source_synthesis_path_for_any_FPGA2001-12-04 22:53 197K 
[   ]20011109_Decoupling_capacitors_on_Virtex_II2001-11-26 20:56 75K 
[   ]20011120_Ann_Low_cost_Spartan2_FPGA_board2001-11-19 21:07 2.1K 
[   ]20011117_Q_XILINX_binary_bit_file_header2001-11-18 19:01 6.8K 
[   ]20011109_Carry_chain_in_Virtex_II2001-11-15 21:52 10K 
[   ]20011107_Xilinx_machine_readable_package_info2001-11-10 20:05 20K 
[   ]20011103_How_dense_are_FPGA_CPLD_s2001-11-10 20:01 28K 
[   ]20011107_FPGA_suppliers_for_hobbyists2001-11-08 00:40 7.9K 
[   ]20011107_Modifying_BlockRAM_contents_in_a_bitstream2001-11-07 21:14 3.4K 
[   ]20011104_JBITS_and_modular_FPGA_configuration2001-11-04 23:20 8.7K 
[   ]20011102_Open_configuration_bitstreams2001-11-03 18:26 9.6K 
[   ]20011030_Autostart_Problem_SPROM_FPGA2001-10-31 20:19 4.9K 
[   ]20011016_LUT_Glitches2001-10-28 15:13 35K 
[   ]20011025_Probing_BGA_Designs2001-10-27 21:22 6.4K 
[   ]20010930_future_Xilinx_products_wish_list2001-10-26 23:19 75K 
[   ]20011014_PLLs_DLLs2001-10-17 23:33 39K 
[   ]20011008_FPGA_reset2001-10-15 21:41 30K 
[   ]20011001_CTL_Register_in_Virtex_E_Configuration2001-10-03 21:45 2.6K 
[   ]20010920_Clockin_on_rising_AND_falling_edge2001-09-24 21:03 18K 
[   ]20010920_Data_cache_for_fpga_cpu_using_Xilinx_BlockRam2001-09-12 21:19 11K 
[   ]20010831_ISA_PC_104_BUS_DECODE_ASYNC_or_SYNC2001-09-05 22:55 19K 
[   ]20010903_Virtex_Architecture_Interconnect2001-09-05 15:31 3.3K 
[   ]20010830_Ethernet_CRC2001-09-05 15:29 26K 
[   ]20010904_Open_collector_outputs2001-09-04 21:59 5.9K 
[   ]20010903_Linux_download_bitstream_w_source2001-09-04 21:57 5.8K 
[   ]20010901_Re_Jbits_more_info_required2001-09-01 21:01 6.9K 
[   ]20010830_Re_XCV800_Jbits2001-09-01 00:18 4.1K 
[   ]20010828_download_bitstream_to_FPGA2001-08-31 23:49 24K 
[   ]20010816_hardware_damage_to_a_Virtex_or_Spartan_II2001-08-25 16:37 43K 
[   ]20010814_Building_a_clock_out_of_a_PLD2001-08-17 00:01 37K 
[   ]20010815_Xilinx_pin_lists_in_text_format2001-08-16 00:04 6.4K 
[   ]20010814_A_parallel_port_low_voltage_signal_interface_for_new_FPGAs2001-08-14 23:24 1.4K 
[   ]20010802_Spartan_II_and_asynchronous_memory_interface2001-08-08 23:48 82K 
[   ]20010723_Homemade_Xilinx_parallel_cable_problem2001-08-04 21:15 23K 
[   ]20010802_Clock_skew_with_Xilinx_DLLs2001-08-03 23:39 17K 
[   ]20010726_PQFP_sockets2001-07-28 02:41 11K 
[   ]20010721_Soldering_Ceramic_BGA_s2001-07-25 17:43 12K 
[   ]20010716_Xilinx_bit_file_format2001-07-17 21:41 7.9K 
[   ]20010708_Shift_and_Add_Multiplier_With_Signed_Numbers2001-07-17 21:31 27K 
[   ]20010712_Design_entry2001-07-17 21:24 44K 
[   ]20010630_xr16vx_a_GPL_16_bit_xr16_microcontroller_in_JHDL2001-07-13 23:39 18K 
[   ]20010604_Xilinx_Configuration_Bitstream2001-07-13 23:27 35K 
[   ]20010626_Stupid_Xilinx_Patent2001-07-13 22:59 46K 
[   ]20010706_Problems_with_Virtex_Block_Ram_Propagation_Delay2001-07-13 22:31 8.4K 
[   ]20010611_Gray_Code_Guard_bits2001-06-12 23:03 10K 
[   ]20010611_Doing_Ethernet_in_a_Virtex2001-06-12 23:00 6.7K 
[   ]20010526_Xilinx_XC4010E_Problem2001-06-06 19:32 31K 
[   ]20010526_The_FAQ_is_Live_and_so_is_the_Archive2001-05-29 23:33 7.5K 
[   ]20010526_Internal_tri_states2001-05-29 23:28 20K 
[   ]20010510_Finally_an_FPGA_tool_chain_for_Linux_Altera_Quartus_II2001-05-23 20:11 85K 
[   ]20010428_BlockRAM_outputs_and_the_Placer2001-04-30 01:03 13K 
[   ]20010417_Download_Cable_Mystery_Solved2001-04-18 17:30 7.6K 
[   ]20010319_TBUFs_in_Virtex_and_later_chips_going_out_of_fashion_what_instead2001-03-23 23:34 63K 
[   ]20010222_Virtex_USB_solution2001-03-19 22:30 20K 
[   ]20010311_sample_code_for_JTAG_configuration_of_Virtex_Spartan_II2001-03-14 00:59 2.1K 
[   ]20010306_More_detailed_Spartan_II_CLB_drawings2001-03-11 23:10 9.4K 
[   ]20010303_Bad_Xilinx_bitstream_big_bang2001-03-07 21:56 42K 
[   ]20010227_Interfacing_Xilinx_4003_to_an_IDE_Hard_Disk_interface2001-03-06 22:02 27K 
[   ]20010224_Soldering_and_Unsoldering_PQFP_by_hand2001-03-04 00:26 14K 
[   ]20010218_Samll_quantities_ordering2001-02-28 23:07 12K 
[   ]20010227_Partial_Reconfig_using_JBits2001-02-28 23:07 10K 
[   ]20010225_VDHL_Book_recomendation_please_Xilinx_designer2001-02-27 20:44 3.1K 
[   ]20010226_Linux_Xilinx_Programmer2001-02-27 20:31 7.6K 
[   ]20010221_Clocks2001-02-21 23:16 5.5K 
[   ]20010216_Vertex_Place_Route_Time2001-02-17 23:38 11K 
[   ]20010215_FAQ_submission2001-02-17 16:55 2.9K 
[   ]20010206_can_A_B_computed_in_one_level_of_logic2001-02-10 16:04 4.5K 
[   ]20010130_Spartan_2_DLL2001-02-06 22:20 65K 
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