From: unexpectedvalue@yahoo.com (avalanche effect) Newsgroups: comp.arch.fpga Subject: From FPGA to ASIC these days Date: 17 Dec 2003 09:53:05 -0800 Organization: http://groups.google.com Lines: 21 Message-ID: <1dcb9a53.0312170953.1b9e2e6c@posting.google.com> References: <1dcb9a53.0312161905.6c373e24@posting.google.com> NNTP-Posting-Host: 205.179.159.102 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1071683585 8813 127.0.0.1 (17 Dec 2003 17:53:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 17 Dec 2003 17:53:05 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!proxad.net!news-out.visi.com!petbe.visi.com!newsfeed2.dallas1.level3.net!news.level3.com!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:36598 Just changing the Subject: to what is should have been ... > Googling web & usenet didn't provide answer or pointers - so here it > goes: > > We have a fully tested design on fat Xilinx FPGA. Must go to ASIC, > 0.18 or better. Relatively simple design, 3 clock domains, 300K gates. > The only interface is USB, so very low pin count. If the foundry > doesn't have USB phy in standard lib, we'll interface external phy. > > The question is - how long does it take - how many months ? We will > farm that out, but I need some realistic idea about time between > giving cash and working FPGA code to this outsourcing entity until we > get first chips in sample quantities. > > I fully understand that each project is different, but feel > uncomfortable with sales' quotes - I'd like to hear real experiences. > > And, BTW, are fabs busy these days or are they in mood for deals ? ###### From: johnjakson@yahoo.com (john jakson) Newsgroups: comp.arch.fpga Subject: Re: From FPGA to ASIC these days Date: 18 Dec 2003 05:19:33 -0800 Organization: http://groups.google.com Lines: 31 Message-ID: References: <1dcb9a53.0312161905.6c373e24@posting.google.com> <1dcb9a53.0312170953.1b9e2e6c@posting.google.com> NNTP-Posting-Host: 211.75.91.19 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1071753574 21383 127.0.0.1 (18 Dec 2003 13:19:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 18 Dec 2003 13:19:34 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!in.100proofnews.com!in.100proofnews.com!news-out.visi.com!petbe.visi.com!newsfeed2.dallas1.level3.net!news.level3.com!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:36616 unexpectedvalue@yahoo.com (avalanche effect) wrote in message news:<1dcb9a53.0312170953.1b9e2e6c@posting.google.com>... > Just changing the Subject: to what is should have been ... > > > > > Googling web & usenet didn't provide answer or pointers - so here it > > goes: > > > > We have a fully tested design on fat Xilinx FPGA. Must go to ASIC, > > 0.18 or better. Relatively simple design, 3 clock domains, 300K gates. > > The only interface is USB, so very low pin count. If the foundry > > doesn't have USB phy in standard lib, we'll interface external phy. > > > > The question is - how long does it take - how many months ? We will > > farm that out, but I need some realistic idea about time between > > giving cash and working FPGA code to this outsourcing entity until we > > get first chips in sample quantities. > > > > I fully understand that each project is different, but feel > > uncomfortable with sales' quotes - I'd like to hear real experiences. > > > > And, BTW, are fabs busy these days or are they in mood for deals ? Check out Lightspeed and Flextronics. Lightspeed has a good story on their website clearly chasing after Xilinx architectures but I have no personal experience of either (yet). Apart from block rams, the IP is the big gotcha here. Lightspeed only customizes 2 layers of metal so it should be quick. johnjaksonATusaDOTcom ###### From: vbetz@altera.com (Vaughn Betz) Newsgroups: comp.arch.fpga Subject: Re: From FPGA to ASIC these days Date: 21 Dec 2003 21:36:55 -0800 Organization: http://groups.google.com Lines: 31 Message-ID: <48761f7f.0312212136.2652384f@posting.google.com> References: <1dcb9a53.0312161905.6c373e24@posting.google.com> <1dcb9a53.0312170953.1b9e2e6c@posting.google.com> NNTP-Posting-Host: 64.229.131.100 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1072071415 7150 127.0.0.1 (22 Dec 2003 05:36:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Dec 2003 05:36:55 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!proxad.net!fr.ip.ndsoftware.net!fu-berlin.de!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:36713 > > Googling web & usenet didn't provide answer or pointers - so here it > > goes: > > > > We have a fully tested design on fat Xilinx FPGA. Must go to ASIC, > > 0.18 or better. Relatively simple design, 3 clock domains, 300K gates. > > The only interface is USB, so very low pin count. If the foundry > > doesn't have USB phy in standard lib, we'll interface external phy. > > > > The question is - how long does it take - how many months ? We will > > farm that out, but I need some realistic idea about time between > > giving cash and working FPGA code to this outsourcing entity until we > > get first chips in sample quantities. > > > > I fully understand that each project is different, but feel > > uncomfortable with sales' quotes - I'd like to hear real experiences. > > > > And, BTW, are fabs busy these days or are they in mood for deals ? One option for a low-risk ASIC conversion is to convert the design to Stratix, then use Altera's HardCopy conversion to an ASIC. It does mean you have to do an FPGA conversion, but that's easy to test immediately because you can try the FPGA right away. Then the ASIC conversion (HardCopy) is relatively easy, since you use the same synthesis & placement tools as you did for the FPGA, and all the tricky IP blocks like RAMs are the same in the HardCopy array as they are in the FPGA. So it's a two-step conversion process, but it lowers your risk. Vaughn Altera