From: bpride@monad.net (Bruce P.) Newsgroups: comp.arch.fpga Subject: Home grown CPU core legal? Date: 9 Nov 2003 11:30:24 -0800 Organization: http://groups.google.com Lines: 24 Message-ID: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: 207.3.146.37 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1068406224 27769 127.0.0.1 (9 Nov 2003 19:30:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 9 Nov 2003 19:30:24 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35308 I've always been interested in designing my own 8-bit CPU core in an FPGA for educational purposes. After visiting www.opencores.org, it seems the easiest/most popular way to go about this is to make the CPU core be compatible with an existing ISA (Instruction Set Architecture) from an available device (e.g. 8051, PIC, etc.). That way I could use readily available development tools to write code, debug, create a hex file, etc. If by some chance I ever used my home grown, ISA compatible, core in a commercialized product, would there be legal issues? Chances are I would never use my own and would probably use a Nios or Microblaze instead, but if I just needed a simple little core, it could prove useful. I know very little about the IP core business, but I've seen off the shelf compatible CPU cores for sale, so I'm guessing these IP companies must pay companies like Microchip when they sell a PIC compatible core? Just curious if anyone has any insight into how all this works. Thanks. -Bruce ###### From: news@sulimma.de (Kolja Sulimma) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: 10 Nov 2003 07:55:36 -0800 Organization: http://groups.google.com Lines: 32 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: 82.82.136.239 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1068479736 10935 127.0.0.1 (10 Nov 2003 15:55:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 10 Nov 2003 15:55:36 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35331 > If by some chance I ever used my home grown, ISA compatible, core in a > commercialized product, would there be legal issues? Chances are I > would never use my own and would probably use a Nios or Microblaze > instead, but if I just needed a simple little core, it could prove > useful. AFAIK (and IANAL) the only effective legal way against a processor clone are patents. This means that very old designs like the 8051, 6502, PIC, etc. should be no problem. The patents only affect ways to design or implement the processor, not the ISA. So if you knew the patents you could design the CPU in a way that does not violate the patent. Unfortuanatle as an amateur you can never be sure what kind of wierd patents suddenly surface out of nowhere. The ISA can not be protected effectively. This does not mean that a pissed processor vendor will not send a hord of lawyers after you to scare you or to cover you in loads of expensive paperwork. Therefore you should stay away from CPUs from companies that live from processor licensing fees. (Like ARM or MIPS) If you really want to play it safe you should implement a SPARC ISA. That's an open standard. Or do a reimplementation of picoblaze or microblaze or xr16. I believe that Xilinx won't mind another Microblaze implementation that helps selling there Chips. (Göran, can you comment on that?) And Jan Gray explicitely stated that he does not object to reimplementations of his xr16 design. Kolja Sulimma ###### From: Goran Bilski Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Mon, 10 Nov 2003 17:17:13 +0100 Organization: Xilinx, Inc. Lines: 150 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: cscopool-20.xilinx.com Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------050408080207040802060803" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.4) Gecko/20030624 Netscape/7.1 (ax) X-Accept-Language: en,sv In-Reply-To: Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!takemy.news.telefonica.de!telefonica.de!newsfeed.media.kyoto-u.ac.jp!ctu-gate!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35333 This is a multi-part message in MIME format. --------------050408080207040802060803 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Hi, I can't see why Xilinx would be against a clean room implementation of MicroBlaze. It would actually be quite interesting. We actually want to promote the use of MicroBlaze. We are not getting our money from MicroBlaze sells but rather on the FPGAs that MicroBlaze uses. If someone did a clean room, open source implementation of MicroBlaze it would probably letting us sell more FPGAs. As Kolja said, you can't really effectively patent an ISA, only an implementation. BUT an implementation can have certain features which you can patent and thus make it hard to design around that patent. ARM has the shadow registers at interrupts and MIPS has the unaligned word access handling,... Even if you did a clean room implementation of ARM and avoid all patents, ARM will sue you to the end. So unless you have big financial backing that will pay your lawyers, you will not win. Göran Kolja Sulimma wrote: >>If by some chance I ever used my home grown, ISA compatible, core in a >>commercialized product, would there be legal issues? Chances are I >>would never use my own and would probably use a Nios or Microblaze >>instead, but if I just needed a simple little core, it could prove >>useful. >> >> > >AFAIK (and IANAL) the only effective legal way against a processor >clone are patents. This means that very old designs like the 8051, >6502, PIC, etc. should be no problem. >The patents only affect ways to design or implement the processor, not >the ISA. So if you knew the patents you could design the CPU in a way >that does not violate the patent. Unfortuanatle as an amateur you can >never be sure what kind of wierd patents suddenly surface out of >nowhere. > >The ISA can not be protected effectively. This does not mean that a >pissed processor vendor will not send a hord of lawyers after you to >scare you or to cover you in loads of expensive paperwork. Therefore >you should stay away from CPUs from companies that live from processor >licensing fees. (Like ARM or MIPS) > >If you really want to play it safe you should implement a SPARC ISA. >That's an open standard. > >Or do a reimplementation of picoblaze or microblaze or xr16. I believe >that Xilinx won't mind another Microblaze implementation that helps >selling there Chips. (Göran, can you comment on that?) > >And Jan Gray explicitely stated that he does not object to >reimplementations of his xr16 design. > >Kolja Sulimma > > --------------050408080207040802060803 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Hi,

I can't see why Xilinx would be against a clean room implementation of MicroBlaze.
It would actually be quite interesting.
We actually want to promote the use of MicroBlaze.
We are not getting our money from MicroBlaze sells but rather on the FPGAs that MicroBlaze uses.
If someone did a clean room, open source implementation of MicroBlaze it would probably letting us sell more FPGAs.

As Kolja said, you can't really effectively patent an ISA, only an implementation.
BUT an implementation can have certain features which you can patent and thus make it hard to design around that patent.
ARM has the shadow registers at interrupts and MIPS has the unaligned word access handling,...

Even if you did a clean room implementation of ARM and avoid all patents, ARM will sue you to the end.
So unless you have big financial backing that will pay your lawyers, you will not win.

Göran

Kolja Sulimma wrote:
If by some chance I ever used my home grown, ISA compatible, core in a
commercialized product, would there be legal issues?   Chances are I
would never use my own and would probably use a Nios or Microblaze
instead, but if I just needed a simple little core, it could prove
useful.
    

AFAIK (and IANAL) the only effective legal way against a processor
clone are patents. This means that very old designs like the 8051,
6502, PIC, etc. should be no problem.
The patents only affect ways to design or implement the processor, not
the ISA. So if you knew the patents you could design the CPU in a way
that does not violate the patent. Unfortuanatle as an amateur you can
never be sure what kind of wierd patents suddenly surface out of
nowhere.

The ISA can not be protected effectively. This does not mean that a
pissed processor vendor will not send a hord of lawyers after you to
scare you or to cover you in loads of expensive paperwork. Therefore
you should stay away from CPUs from companies that live from processor
licensing fees. (Like ARM or MIPS)

If you really want to play it safe you should implement a SPARC ISA.
That's an open standard.

Or do a reimplementation of picoblaze or microblaze or xr16. I believe
that Xilinx won't mind another Microblaze implementation that helps
selling there Chips. (Göran, can you comment on that?)

And Jan Gray explicitely stated that he does not object to
reimplementations of his xr16 design.

Kolja Sulimma
--------------050408080207040802060803-- ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Mon, 10 Nov 2003 16:42:16 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 28 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1068482536 81497 128.32.112.203 (10 Nov 2003 16:42:16 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Mon, 10 Nov 2003 16:42:16 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!newsfeed.stanford.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35334 In article , Kolja Sulimma wrote: >The ISA can not be protected effectively. This does not mean that a >pissed processor vendor will not send a hord of lawyers after you to >scare you or to cover you in loads of expensive paperwork. Therefore >you should stay away from CPUs from companies that live from processor >licensing fees. (Like ARM or MIPS) I'm not so sure about this, look at some of the unique ISA features (eg, the initial conditional execution in ARM, the IA64 deferred exceptions (good idea) and rotating register file (bad idea)). I think these items can and are patented. >If you really want to play it safe you should implement a SPARC ISA. >That's an open standard. Just don't call it SPARC. You have to say "Sparc Compatabile IEEE whatever" until you pay sparc money. But that's no big deal. >Or do a reimplementation of picoblaze or microblaze or xr16. I believe >that Xilinx won't mind another Microblaze implementation that helps >selling there Chips. (Göran, can you comment on that?) Microblaze is probably a nice one, since it should map well to large families of FPGAs. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: "Symon" Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Mon, 10 Nov 2003 08:49:22 -0800 Lines: 25 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: 67-121-165-33.ded.pacbell.net (67.121.165.33) X-Trace: news.uni-berlin.de 1068483288 50985656 67.121.165.33 (16 [212844]) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!npeer.de.kpn-eurorings.net!fu-berlin.de!uni-berlin.de!67-121-165-33.ded.pacbell.NET!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35337 Hi Goran, So, playing devli's advocate, Xilinx wouldn't mind if the clean room Microblaze was targeted at their competitors' devices? Or do you think that no one would do this because Microblaze only efficiently fits the Xilinx devices? Or the competitors have their own solutions for their parts? I wonder.... cheers, Syms. "Goran Bilski" wrote in message news:boodq5$bgr2@cliff.xsj.xilinx.com... Hi, I can't see why Xilinx would be against a clean room implementation of MicroBlaze. It would actually be quite interesting. We actually want to promote the use of MicroBlaze. We are not getting our money from MicroBlaze sells but rather on the FPGAs that MicroBlaze uses. If someone did a clean room, open source implementation of MicroBlaze it would probably letting us sell more FPGAs. ###### From: Goran Bilski Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Mon, 10 Nov 2003 18:30:28 +0100 Organization: Xilinx, Inc. Lines: 48 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: cscopool-20.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.4) Gecko/20030624 Netscape/7.1 (ax) X-Accept-Language: en,sv In-Reply-To: Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!in.100proofnews.com!in.100proofnews.com!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35341 Hi Symon, I don't think Xilinx would be happy but I don't think we would do anything against it. I also think that MicroBlaze will be better implemented in our FPGA than in our competitors. If someone did a clean, pure RTL implementation of MicroBlaze, I think that someone will very quickly try it on our competitors FPGA. I have a pure RTL version of MicroBlaze and it doesn't look good when targeting other devices than Xilinx's devices. But someone started from scratch, the design would probably not be so biased against Xilinx. Göran Symon wrote: >Hi Goran, > So, playing devli's advocate, Xilinx wouldn't mind if the clean room >Microblaze was targeted at their competitors' devices? Or do you think that >no one would do this because Microblaze only efficiently fits the Xilinx >devices? Or the competitors have their own solutions for their parts? > I wonder.... > cheers, Syms. > > >"Goran Bilski" wrote in message >news:boodq5$bgr2@cliff.xsj.xilinx.com... >Hi, > >I can't see why Xilinx would be against a clean room implementation of >MicroBlaze. >It would actually be quite interesting. >We actually want to promote the use of MicroBlaze. >We are not getting our money from MicroBlaze sells but rather on the FPGAs >that MicroBlaze uses. >If someone did a clean room, open source implementation of MicroBlaze it >would probably letting us sell more FPGAs. > > > > > > ###### From: bpride@monad.net (Bruce P.) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: 10 Nov 2003 10:08:48 -0800 Organization: http://groups.google.com Lines: 12 Message-ID: <762349e4.0311101008.37154b09@posting.google.com> References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: 208.50.113.34 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1068487729 20561 127.0.0.1 (10 Nov 2003 18:08:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 10 Nov 2003 18:08:49 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!postnews2.google.com!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35344 > If you really want to play it safe you should implement a SPARC ISA. > That's an open standard. > > Or do a reimplementation of picoblaze or microblaze or xr16. I believe > that Xilinx won't mind another Microblaze implementation that helps > selling there Chips. (Göran, can you comment on that?) > Thanks, the Picoblaze looks like a simple one to look at first. Plenty of documentation and free tools as well. BP ###### From: jakespambox@yahoo.com (Jake Janovetz) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: 10 Nov 2003 11:33:06 -0800 Organization: http://groups.google.com Lines: 10 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: 12.221.77.174 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1068492787 26908 127.0.0.1 (10 Nov 2003 19:33:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 10 Nov 2003 19:33:07 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35349 news@sulimma.de (Kolja Sulimma) wrote in message news:... > Or do a reimplementation of picoblaze or microblaze or xr16. I believe > that Xilinx won't mind another Microblaze implementation that helps > selling there Chips. (Göran, can you comment on that?) Once a version of microblaze becomes widely available on the Cyclone series (or other Altera chip) and starts selling Altera chips, I'm sure Xilinx would mind. :) Jake ###### From: "Ralph Mason" Newsgroups: comp.arch.fpga References: <762349e4.0311091130.6464de51@posting.google.com> Subject: Re: Home grown CPU core legal? Lines: 14 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Date: Tue, 11 Nov 2003 08:50:02 +1300 NNTP-Posting-Host: 219.89.129.61 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 1068493797 219.89.129.61 (Tue, 11 Nov 2003 08:49:57 NZDT) NNTP-Posting-Date: Tue, 11 Nov 2003 08:49:57 NZDT Organization: Xtra Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!enews.sgi.com!news.xtra.co.nz!53ab2750!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35350 "Goran Bilski" wrote in message news:booi3e$bg72@cliff.xsj.xilinx.com... > Hi Symon, > But someone started from scratch, the design would probably not be so > biased against Xilinx. > Perhaps you should do one that is biased *towards* Xilinx parts ;-) Ralph ###### From: Goran Bilski Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Mon, 10 Nov 2003 21:18:28 +0100 Organization: Xilinx, Inc. Lines: 90 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: cscopool-20.xilinx.com Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------090508090504070508040605" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.4) Gecko/20030624 Netscape/7.1 (ax) X-Accept-Language: en,sv In-Reply-To: Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!enews.sgi.com!news-out.superfeed.net!propagator2-maxim!news-in-maxim.spamkiller.net!news.usc.edu!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35351 This is a multi-part message in MIME format. --------------090508090504070508040605 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Well, MicroBlaze is biased against Xilinx FPGA. The whole ISA is done towards our devices. That's why I mean it will probably not be efficient in other FPGA vendors architecture. But I think it would be very suited for an ASIC implementation. Göran Ralph Mason wrote: >"Goran Bilski" wrote in message >news:booi3e$bg72@cliff.xsj.xilinx.com... > > >>Hi Symon, >> >> > > > >>But someone started from scratch, the design would probably not be so >>biased against Xilinx. >> >> >> > >Perhaps you should do one that is biased *towards* Xilinx parts ;-) > >Ralph > > > > --------------090508090504070508040605 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Well, MicroBlaze is biased against Xilinx FPGA.
The whole ISA is done towards our devices.

That's why I mean it will probably not be efficient in other FPGA vendors architecture.
But I think it would be very suited for an ASIC implementation.

Göran

Ralph Mason wrote:
"Goran Bilski" <goran@xilinx.com> wrote in message
news:booi3e$bg72@cliff.xsj.xilinx.com...
  
Hi Symon,
    

  
But someone started from scratch, the design would probably not be so
biased against Xilinx.

    

Perhaps you should do one that is biased *towards* Xilinx parts ;-)

Ralph
--------------090508090504070508040605-- ###### Message-ID: <3FAFFAE7.2939@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? References: <762349e4.0311091130.6464de51@posting.google.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 19 Date: Tue, 11 Nov 2003 09:53:59 +1300 NNTP-Posting-Host: 210.246.4.22 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1068497653 210.246.4.22 (Tue, 11 Nov 2003 09:54:13 NZDT) NNTP-Posting-Date: Tue, 11 Nov 2003 09:54:13 NZDT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!enews.sgi.com!news.xtra.co.nz!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35353 Symon wrote: > > Hi Goran, > So, playing devli's advocate, Xilinx wouldn't mind if the clean room > Microblaze was targeted at their competitors' devices? Or do you think that > no one would do this because Microblaze only efficiently fits the Xilinx > devices? Or the competitors have their own solutions for their parts? > I wonder.... Xilinx's protection does not come from attack on the clean room clone, but rather from the protection of the Microblaze name, and tool flows. So, anyone would be free to create an opcode compatible core, if they wished, but not to use the brand, nor the Xilinx tool flows. Older uC cores are easier to copy (any patents lapsed), and their tools are widely available. Things like 80C51, 6502, Z8, and even 8085.... ( someone must have done a 8048 core ? :) -jg ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Mon, 10 Nov 2003 13:16:26 -0800 Organization: Xilinx, Inc. Lines: 20 Message-ID: <3FB0002A.909E765A@xilinx.com> References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: 149.199.53.89 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Mailer: Mozilla 4.79 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!newsfeed.berkeley.edu!ucberkeley!ihnp4.ucsd.edu!usc.edu!news.usc.edu!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35356 Jake, Microblaze(tm) requires specific Xilinx features, and can not be implemented efficiently in (by) other architectures. The specific features required are covered by patents. Austin Jake Janovetz wrote: > news@sulimma.de (Kolja Sulimma) wrote in message news:... > > Or do a reimplementation of picoblaze or microblaze or xr16. I believe > > that Xilinx won't mind another Microblaze implementation that helps > > selling there Chips. (Göran, can you comment on that?) > > Once a version of microblaze becomes widely available on the Cyclone > series (or other Altera chip) and starts selling Altera chips, I'm > sure Xilinx would mind. :) > > Jake ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Mon, 10 Nov 2003 21:18:39 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 11 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FAFFAE7.2939@designtools.co.nz> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1068499119 87236 128.32.112.203 (10 Nov 2003 21:18:39 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Mon, 10 Nov 2003 21:18:39 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35355 In article <3FAFFAE7.2939@designtools.co.nz>, Jim Granville wrote: > Xilinx's protection does not come from attack on the clean room clone, >but rather from the protection of the Microblaze name, and tool flows. > So, anyone would be free to create an opcode compatible core, >if they wished, but not to use the brand, nor the Xilinx tool flows. Isn't the compiler flow gcc? -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: Goran Bilski Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Mon, 10 Nov 2003 22:30:26 +0100 Organization: Xilinx, Inc. Lines: 90 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FAFFAE7.2939@designtools.co.nz> NNTP-Posting-Host: cscopool-20.xilinx.com Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------010507050305030102070901" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.4) Gecko/20030624 Netscape/7.1 (ax) X-Accept-Language: en,sv In-Reply-To: <3FAFFAE7.2939@designtools.co.nz> Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!in.100proofnews.com!in.100proofnews.com!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35358 This is a multi-part message in MIME format. --------------010507050305030102070901 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit The name MicroBlaze is a trademark of MicroBlaze. So a cleanroom can't be called MicroBlaze. For the tools part, yes, the EDK tools is our tools which we don't give away for free (they costs $495 and that's including all the IP) The actual compiler tools is GNU tools and they are open-sourced. Göran Jim Granville wrote: >Symon wrote: > > >>Hi Goran, >> So, playing devli's advocate, Xilinx wouldn't mind if the clean room >>Microblaze was targeted at their competitors' devices? Or do you think that >>no one would do this because Microblaze only efficiently fits the Xilinx >>devices? Or the competitors have their own solutions for their parts? >> I wonder.... >> >> > > Xilinx's protection does not come from attack on the clean room clone, >but rather from the protection of the Microblaze name, and tool flows. > So, anyone would be free to create an opcode compatible core, >if they wished, but not to use the brand, nor the Xilinx tool flows. > > Older uC cores are easier to copy (any patents lapsed), and their tools >are widely available. Things like 80C51, 6502, Z8, and even 8085.... > ( someone must have done a 8048 core ? :) > >-jg > > --------------010507050305030102070901 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit The name MicroBlaze is a trademark of MicroBlaze.
So a cleanroom can't be called MicroBlaze.
For the tools part, yes, the EDK tools is our tools which we don't give away for free (they costs $495 and that's including all the IP)
The actual compiler tools is GNU tools and they are open-sourced.

Göran

Jim Granville wrote:
Symon wrote:
  
Hi Goran,
    So, playing devli's advocate, Xilinx wouldn't mind if the clean room
Microblaze was targeted at their competitors' devices? Or do you think that
no one would do this because Microblaze only efficiently fits the Xilinx
devices? Or the competitors have their own solutions for their parts?
    I wonder....
    

 Xilinx's protection does not come from attack on the clean room clone,
but rather from the protection of the Microblaze name, and tool flows.
 So, anyone would be free to create an opcode compatible core, 
if they wished, but not to use the brand, nor the Xilinx tool flows.

 Older uC cores are easier to copy (any patents lapsed), and their tools 
are widely available. Things like 80C51, 6502, Z8, and even 8085....
 ( someone must have done a 8048 core ? :)

-jg
--------------010507050305030102070901-- ###### From: acher@in.tum.de (Georg Acher) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: 10 Nov 2003 21:33:35 GMT Organization: LRR, TU Muenchen Lines: 15 Distribution: world Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FB0002A.909E765A@xilinx.com> NNTP-Posting-Host: atbode61.informatik.tu-muenchen.de X-Trace: wsc10.lrz-muenchen.de 1068500015 686 131.159.32.54 (10 Nov 2003 21:33:35 GMT) X-Complaints-To: news@lrz-muenchen.de NNTP-Posting-Date: 10 Nov 2003 21:33:35 GMT X-Newsreader: xrn 9.02 Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!news.belwue.de!informatik.tu-muenchen.de!lrz.de!atbode61.lrr.in.tum.de!acher Xref: redlance.franklin.ch comp.arch.fpga:35357 In article <3FB0002A.909E765A@xilinx.com>, Austin Lesea writes: |> Microblaze(tm) requires specific Xilinx features, and can not be implemented efficiently in (by) other |> architectures. The specific features required are covered by patents. I like the perversion of the word "patent". "patere", lat.: "standing open". SCNR(tm) -- Georg Acher, acher@in.tum.de http://wwwbode.in.tum.de/~acher "Oh no, not again !" The bowl of petunias ###### From: John Williams Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Tue, 11 Nov 2003 08:16:35 +1000 Organization: ITEE, University of Queensland Lines: 21 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FB0002A.909E765A@xilinx.com> Reply-To: jwilliams@itee.uq.edu.au NNTP-Posting-Host: g435-9029.itee.uq.edu.au Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: bunyip.cc.uq.edu.au 1068502562 31806 130.102.66.250 (10 Nov 2003 22:16:02 GMT) X-Complaints-To: news@uq.edu.au NNTP-Posting-Date: 10 Nov 2003 22:16:02 GMT User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4) Gecko/20030529 X-Accept-Language: en-us, en In-Reply-To: Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!news1.optus.net.au!optus!news.mel.connect.com.au!news.syd.connect.com.au!news.bri.connect.com.au!bunyip.cc.uq.edu.au!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35361 Georg Acher wrote: > In article <3FB0002A.909E765A@xilinx.com>, > Austin Lesea writes: > > |> Microblaze(tm) requires specific Xilinx features, and can not be implemented efficiently in (by) other > |> architectures. The specific features required are covered by patents. > > I like the perversion of the word "patent". > > "patere", lat.: "standing open". Which is precisely what they do - the details are published (ie open), but there is protection for the inventor to profit exclusively from that invention for a limited period of time. A reasonable idea in principle - it's the rampant abuse that is the problem. Regards, John ###### From: John Williams Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Tue, 11 Nov 2003 08:19:14 +1000 Organization: ITEE, University of Queensland Lines: 23 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FAFFAE7.2939@designtools.co.nz> Reply-To: jwilliams@itee.uq.edu.au NNTP-Posting-Host: g435-9029.itee.uq.edu.au Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: bunyip.cc.uq.edu.au 1068502721 31806 130.102.66.250 (10 Nov 2003 22:18:41 GMT) X-Complaints-To: news@uq.edu.au NNTP-Posting-Date: 10 Nov 2003 22:18:41 GMT User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4) Gecko/20030529 X-Accept-Language: en-us, en In-Reply-To: Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!news.mel.connect.com.au!news.syd.connect.com.au!news.bri.connect.com.au!bunyip.cc.uq.edu.au!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35362 Nicholas C. Weaver wrote: > In article <3FAFFAE7.2939@designtools.co.nz>, > Jim Granville wrote: > > >>Xilinx's protection does not come from attack on the clean room clone, >>but rather from the protection of the Microblaze name, and tool flows. >>So, anyone would be free to create an opcode compatible core, >>if they wished, but not to use the brand, nor the Xilinx tool flows. > > > Isn't the compiler flow gcc? It is indeed. I host a copy of the tools on my website, and one may build entire microblaze linux kernels without paying a cent to Xilinx. Of course, you won't have a processor to run it on unless you do! Same as any gcc-targeted processor really. Regards, John ###### From: bpride@monad.net (Bruce P.) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: 10 Nov 2003 14:31:05 -0800 Organization: http://groups.google.com Lines: 14 Message-ID: <762349e4.0311101431.24595dcb@posting.google.com> References: <762349e4.0311091130.6464de51@posting.google.com> NNTP-Posting-Host: 208.50.113.34 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1068503465 7086 127.0.0.1 (10 Nov 2003 22:31:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 10 Nov 2003 22:31:05 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35364 > > Once a version of microblaze becomes widely available on the Cyclone > series (or other Altera chip) and starts selling Altera chips, I'm > sure Xilinx would mind. :) > Did I mention that my new board design has a Cyclone on it? Hmmm, "The Cyclo-Blaze"...has sort of a nice ring to it. ;>) I guess if it's smaller than the Altera Nios and a lot simpler, it could be of some use. Anyway, it should be a good learning experience. Thanks again. BP ###### From: H. Peter Anvin Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Organization: Transmeta Corporation, Santa Clara CA Lines: 34 Sender: hpa@cesium.transmeta.com Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: bpride@monad.net (Bruce P.) Disclaimer: Not speaking for Transmeta in any way, shape, or form. Copyright: Copyright 2003 H. Peter Anvin - All Rights Reserved Cache-Post-Path: palladium.transmeta.com!unknown@cesium.transmeta.com X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Date: 11 Nov 2003 11:28:59 -0800 NNTP-Posting-Host: 63.209.4.196 X-Complaints-To: news@globix.net X-Trace: news.sjc.globix.net 1068578913 63.209.4.196 (Tue, 11 Nov 2003 11:28:33 PST) NNTP-Posting-Date: Tue, 11 Nov 2003 11:28:33 PST Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!small1.nntp.aus1.giganews.com!border1.nntp.aus1.giganews.com!nntp.giganews.com!cyclone-sf.pbi.net!209.10.34.151!newsfeed.sjc.globix.net!news.sjc.globix.net!cesium.transmeta.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35421 Followup to: <762349e4.0311101431.24595dcb@posting.google.com> By author: bpride@monad.net (Bruce P.) In newsgroup: comp.arch.fpga > > Did I mention that my new board design has a Cyclone on it? Hmmm, "The > Cyclo-Blaze"...has sort of a nice ring to it. ;>) > > I guess if it's smaller than the Altera Nios and a lot simpler, it > could be of some use. Anyway, it should be a good learning > experience. Thanks again. > I think a small core that's vendor-independent would be nice. There are enough many things in common between most current FPGA architectures (4- or 5-input LUTs, carry chains, dualport block RAMs in the 4kbit size range) that doing something sane that's technology-independent shouldn't be that hard. It may not be as sophisticated as MicroBlaze or NIOS, but wouldn't come with automatic vendor lock-in. I have actually been hacking a bit on a very simple 16-bit architecture that I'm hoping will fit the bill. No promises if or when I'll get around to finishing it, though... at this point I'd say the RTL is about 30% done. -hpa -- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64 ###### From: "Glen Herrmannsfeldt" Newsgroups: comp.arch.fpga References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> Subject: Re: Home grown CPU core legal? Lines: 25 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4927.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4927.1200 Message-ID: <6Uasb.123195$mZ5.829826@attbi_s54> NNTP-Posting-Host: 12.228.234.203 X-Complaints-To: abuse@comcast.net X-Trace: attbi_s54 1068579458 12.228.234.203 (Tue, 11 Nov 2003 19:37:38 GMT) NNTP-Posting-Date: Tue, 11 Nov 2003 19:37:38 GMT Organization: Comcast Online Date: Tue, 11 Nov 2003 19:37:38 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!newsfeed.frii.net!newsfeed.frii.net!140.99.99.194.MISMATCH!newsfeed1.easynews.com!easynews.com!easynews!crtntx1-snh1.gtei.net!news.gtei.net!chcgil2-snh1.gtei.net!news.bbnplanet.com!wn12feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!attbi_s54.POSTED!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35423 "H. Peter Anvin" wrote in message news:bord9r$sn5$1@cesium.transmeta.com... (snip) > I think a small core that's vendor-independent would be nice. There > are enough many things in common between most current FPGA > architectures (4- or 5-input LUTs, carry chains, dualport block RAMs > in the 4kbit size range) that doing something sane that's > technology-independent shouldn't be that hard. It may not be as > sophisticated as MicroBlaze or NIOS, but wouldn't come with automatic > vendor lock-in. > > I have actually been hacking a bit on a very simple 16-bit > architecture that I'm hoping will fit the bill. No promises if or > when I'll get around to finishing it, though... at this point I'd say > the RTL is about 30% done. The PDP-11 has a nice simple 16 bit architecture, not including the optional instructions. (FIS and EIS for example.) -- glen ###### From: H. Peter Anvin Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Organization: Transmeta Corporation, Santa Clara CA Lines: 97 Sender: hpa@cesium.transmeta.com Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: "Glen Herrmannsfeldt" Disclaimer: Not speaking for Transmeta in any way, shape, or form. Copyright: Copyright 2003 H. Peter Anvin - All Rights Reserved Cache-Post-Path: palladium.transmeta.com!unknown@cesium.transmeta.com X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Date: 11 Nov 2003 11:59:27 -0800 NNTP-Posting-Host: 63.209.4.196 X-Complaints-To: news@globix.net X-Trace: news.sjc.globix.net 1068580742 63.209.4.196 (Tue, 11 Nov 2003 11:59:02 PST) NNTP-Posting-Date: Tue, 11 Nov 2003 11:59:02 PST Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!enews.sgi.com!news-out.superfeed.net!propagator2-maxim!news-in-maxim.spamkiller.net!newsfeed.sjc.globix.net!news.sjc.globix.net!cesium.transmeta.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35425 Followup to: <6Uasb.123195$mZ5.829826@attbi_s54> By author: "Glen Herrmannsfeldt" In newsgroup: comp.arch.fpga > > The PDP-11 has a nice simple 16 bit architecture, not including the optional > instructions. (FIS and EIS for example.) > The PDP-11 is still very much a CISC archtecture... I think it would require a lot more logic than necessary. This below is my design notes for my hacked-up architecture, currently called "NanoRISC." I have no way to know how this is turning out. My current goal is to make sure it implements in < 1000 LEs on Cyclone, without using blockRAM for the register file. Fundamentally it's a personal research hack project. -hpa NanoRISC goals - Minimal hardware consumption - Technology independent - Free licensing -> 16-bit addressing, data width, instruction word -> Single issue in-order RISC -> Short pipeline (probably 3 stages) -> Deterministic timing (1 cycle/insn, taken branch 2 cycles?) -> Separate ports for I and D to take advantage of dual-port RAM 0000 NNNN NNNN NNNN - IMM (supplies upper 12 bits of q or Is field) 0001 0000 SSSS DDDD - JMP Rd,Rs (PC <- Rd, Rd <- Rs) 0001 CCCC TTTT TTTT - BR cc,PC+t (cc != 0) 001I PPPP SSSS DDDD - ALU Rd,Rs/Is (P = operation, I = immediate) 01WB QQQQ BBBB RRRR - LD/ST Rr,[Rb+q] (W=ST/LD# B=16/8#) 1TTT TTTT TTTT TTTT - CALL PC+t (PC <- PC+2, r15 <- PC, PC <- PC+t) ALU opcodes 0000 UNARY 1000 ROR 1001 ROL 1010 RCR 1011 RCL 1100 SHR 1101 SHL 1110 SAR 1111 SXL Shift left insert 1 [...more...] 0001 MOV 0010 CMP 0011 TST 0100 ANDN 0101 OR 0110 XOR 0111 AND 1000 ADD 1001 ADC 1010 SUB 1011 SBC 1100 SUBR 1101 SBCR 1110 WRSR 1111 RDSR Condition codes 3 N = negative 2 Z = zero 1 V = overflow 0 C = carry #e - Z #b - ~C #a - C & ~Z #l - V #g - ~V & ~Z #s - N + negations always - negation of code 0000 -- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64 ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Tue, 11 Nov 2003 15:33:17 -0500 Organization: Arius, Inc Lines: 36 Message-ID: <3FB1478D.8C19CC98@yahoo.com> References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbbcOv4fag1O2jaDvRzXRk36OHwwR4POIxK0PM1XVUIcBB/xGzgW50z X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 11 Nov 2003 20:33:18 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!feed1.news.rcn.net!rcn!feed3.news.rcn.net!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35427 "H. Peter Anvin" wrote: > > Followup to: <6Uasb.123195$mZ5.829826@attbi_s54> > By author: "Glen Herrmannsfeldt" > In newsgroup: comp.arch.fpga > > > > The PDP-11 has a nice simple 16 bit architecture, not including the optional > > instructions. (FIS and EIS for example.) > > > > The PDP-11 is still very much a CISC archtecture... I think it would > require a lot more logic than necessary. > > This below is my design notes for my hacked-up architecture, currently > called "NanoRISC." > > I have no way to know how this is turning out. My current goal is to > make sure it implements in < 1000 LEs on Cyclone, without using > blockRAM for the register file. Fundamentally it's a personal > research hack project. Aren't there already several open source FPGA CPUs avaiable? Anyone have a few links handy? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Erez Birenzwig" Newsgroups: comp.arch.fpga References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB1478D.8C19CC98@yahoo.com> Subject: Re: Home grown CPU core legal? Lines: 26 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Message-ID: Date: Wed, 12 Nov 2003 09:58:14 +1300 NNTP-Posting-Host: 219.88.101.154 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 1068584411 219.88.101.154 (Wed, 12 Nov 2003 10:00:11 NZDT) NNTP-Posting-Date: Wed, 12 Nov 2003 10:00:11 NZDT Organization: Xtra Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!newsfeed.vmunix.org!news1.optus.net.au!optus!news.mel.connect.com.au!news.xtra.co.nz!53ab2750!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35429 You should try www.opencores.org Erez. "rickman" wrote in message news:3FB1478D.8C19CC98@yahoo.com... > "H. Peter Anvin" wrote: > > > Aren't there already several open source FPGA CPUs avaiable? Anyone > have a few links handy? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Tue, 11 Nov 2003 13:22:29 -0800 Organization: Xilinx,Inc Lines: 44 Message-ID: <3FB15315.5D9F933E@xilinx.com> References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB1478D.8C19CC98@yahoo.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: rickman Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!proxad.net!newsfeed.media.kyoto-u.ac.jp!ctu-gate!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35434 Your self-imposed limit of "1000 LEs without using BlockRAM for the register file" will put you at a distinct disadvantage against MicroBlaze which can use LUT-RAMs and SRL16s, something Altera does not have. :-( or :-) dpending on your affiliation. Peter Alfke, Xilinx rickman wrote: > > "H. Peter Anvin" wrote: > > > > Followup to: <6Uasb.123195$mZ5.829826@attbi_s54> > > By author: "Glen Herrmannsfeldt" > > In newsgroup: comp.arch.fpga > > > > > > The PDP-11 has a nice simple 16 bit architecture, not including the optional > > > instructions. (FIS and EIS for example.) > > > > > > > The PDP-11 is still very much a CISC archtecture... I think it would > > require a lot more logic than necessary. > > > > This below is my design notes for my hacked-up architecture, currently > > called "NanoRISC." > > > > I have no way to know how this is turning out. My current goal is to > > make sure it implements in < 1000 LEs on Cyclone, without using > > blockRAM for the register file. Fundamentally it's a personal > > research hack project. > > Aren't there already several open source FPGA CPUs avaiable? Anyone > have a few links handy? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3FB1539C.160F@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 36 Date: Wed, 12 Nov 2003 10:24:44 +1300 NNTP-Posting-Host: 210.246.2.115 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1068585908 210.246.2.115 (Wed, 12 Nov 2003 10:25:08 NZDT) NNTP-Posting-Date: Wed, 12 Nov 2003 10:25:08 NZDT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.media.kyoto-u.ac.jp!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35436 H. Peter Anvin wrote: > > Followup to: <6Uasb.123195$mZ5.829826@attbi_s54> > By author: "Glen Herrmannsfeldt" > In newsgroup: comp.arch.fpga > > > > The PDP-11 has a nice simple 16 bit architecture, not including the optional > > instructions. (FIS and EIS for example.) > > > > The PDP-11 is still very much a CISC archtecture... I think it would > require a lot more logic than necessary. > > This below is my design notes for my hacked-up architecture, currently > called "NanoRISC." > > I have no way to know how this is turning out. My current goal is to > make sure it implements in < 1000 LEs on Cyclone, without using > blockRAM for the register file. Fundamentally it's a personal > research hack project. > > -hpa > > NanoRISC goals > - Minimal hardware consumption > - Technology independent > - Free licensing > > -> 16-bit addressing, data width, instruction word In doing a 'clean slate' FPGA small core, there is merit in choosing an opcode width that matches the FPGA Block RAM / Multiplier widths. ( eg I've seen 9 bit opcodes used ) Did you look at that ? -jg ###### From: H. Peter Anvin Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Organization: Transmeta Corporation, Santa Clara CA Lines: 30 Sender: hpa@cesium.transmeta.com Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FB1478D.8C19CC98@yahoo.com> <3FB15315.5D9F933E@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: Peter Alfke Disclaimer: Not speaking for Transmeta in any way, shape, or form. Copyright: Copyright 2003 H. Peter Anvin - All Rights Reserved Cache-Post-Path: palladium.transmeta.com!unknown@cesium.transmeta.com X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Date: 11 Nov 2003 13:29:47 -0800 NNTP-Posting-Host: 63.209.4.196 X-Complaints-To: news@globix.net X-Trace: news.sjc.globix.net 1068586161 63.209.4.196 (Tue, 11 Nov 2003 13:29:21 PST) NNTP-Posting-Date: Tue, 11 Nov 2003 13:29:21 PST Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!small1.nntp.aus1.giganews.com!border1.nntp.aus1.giganews.com!nntp.giganews.com!cyclone-sf.pbi.net!209.10.34.151!newsfeed.sjc.globix.net!news.sjc.globix.net!cesium.transmeta.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35437 Followup to: <3FB15315.5D9F933E@xilinx.com> By author: Peter Alfke In newsgroup: comp.arch.fpga > > Your self-imposed limit of "1000 LEs without using BlockRAM for the > register file" will put you at a distinct disadvantage against > MicroBlaze which can use LUT-RAMs and SRL16s, something Altera does not have. > :-( or :-) dpending on your affiliation. > Peter Alfke, Xilinx > Since my affiliation is "neither" (I just happen to own a Cyclone board since that was the biggest FPGA I could get with free tools) I guess it's more of a :-| than either of those :^) Unless Xilinx' tools are complete crap, which I'd find unlikely, I would expect that the tools would infer the use of LUT-RAMs for the register file if synthesized for a Xilinx part. It's all part of "no vendor lockin." Also, this is mostly a project I'm doing for fun. If it happens to be useful at some point in the future, so much the better, if not, I've still achieved my goal of grokking FPGA synthesis better. -hpa -- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64 ###### From: Petter Gustad Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: 11 Nov 2003 22:30:28 +0100 Organization: 502 You are not allowed to talk Lines: 16 Sender: petter@zener.home.gustad.com Message-ID: <87d6byy4nf.fsf@zener.home.gustad.com> References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB1478D.8C19CC98@yahoo.com> NNTP-Posting-Host: adsl58-175.firstmile.no (217.199.58.175) Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.uni-berlin.de 1068588014 52827031 217.199.58.175 (16 [203234]) X-Home-Page: http://gustad.com Original-Sender: newsmailcomp6@gustad.com User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeeder.edisontel.com!fu-berlin.de!uni-berlin.de!adsl58-175.firstmile.NO!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35444 "Erez Birenzwig" writes: > You should try www.opencores.org Or http://www.fpgacpu.org/links.html Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? ###### From: H. Peter Anvin Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Organization: Transmeta Corporation, Santa Clara CA Lines: 22 Sender: hpa@cesium.transmeta.com Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB1539C.160F@designtools.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: jim.granville@designtools.co.nz Disclaimer: Not speaking for Transmeta in any way, shape, or form. Copyright: Copyright 2003 H. Peter Anvin - All Rights Reserved Cache-Post-Path: palladium.transmeta.com!unknown@cesium.transmeta.com X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Date: 11 Nov 2003 13:31:51 -0800 NNTP-Posting-Host: 63.209.4.196 X-Complaints-To: news@globix.net X-Trace: news.sjc.globix.net 1068586286 63.209.4.196 (Tue, 11 Nov 2003 13:31:26 PST) NNTP-Posting-Date: Tue, 11 Nov 2003 13:31:26 PST Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.arcor-online.net!small1.nntp.aus1.giganews.com!border1.nntp.aus1.giganews.com!nntp.giganews.com!cyclone-sf.pbi.net!209.10.34.151!newsfeed.sjc.globix.net!news.sjc.globix.net!cesium.transmeta.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35438 Followup to: <3FB1539C.160F@designtools.co.nz> By author: jim.granville@designtools.co.nz In newsgroup: comp.arch.fpga > > In doing a 'clean slate' FPGA small core, there is merit in choosing > an opcode width that matches the FPGA Block RAM / Multiplier widths. > ( eg I've seen 9 bit opcodes used ) > Did you look at that ? > Some vendors have 9/18-bit blockRAMs, some don't. I'm trying to be as generic as possible. It also makes it easier to port tools like gas/binutils/gcc. -hpa -- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64 ###### Message-ID: <3FB15A89.7DF@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? References: <762349e4.0311091130.6464de51@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB1539C.160F@designtools.co.nz> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 42 Date: Wed, 12 Nov 2003 10:54:17 +1300 NNTP-Posting-Host: 210.246.2.115 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1068587672 210.246.2.115 (Wed, 12 Nov 2003 10:54:32 NZDT) NNTP-Posting-Date: Wed, 12 Nov 2003 10:54:32 NZDT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!enews.sgi.com!news.xtra.co.nz!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35441 H. Peter Anvin wrote: > > Followup to: <3FB1539C.160F@designtools.co.nz> > By author: jim.granville@designtools.co.nz > In newsgroup: comp.arch.fpga > > > > In doing a 'clean slate' FPGA small core, there is merit in choosing > > an opcode width that matches the FPGA Block RAM / Multiplier widths. > > ( eg I've seen 9 bit opcodes used ) > > Did you look at that ? > > > > Some vendors have 9/18-bit blockRAMs, some don't. I'm trying to be as > generic as possible. It also makes it easier to port tools like > gas/binutils/gcc. & Off chip memory is also easier.... As FPGAs get ever cheaper, and Block RAM gets larger, and factoring in relative speeds, there is scope to define a CPU that takes a coarse approach to cache, like : - reserves a BlockRAM (or 2) for CODE for SW interrupt loops, and Cache-locked code This gives very fast responses, and lowers RFI and total Power (minimum off-chip BUS/eternal memory activity) - uses another Block RAM for code cache, where it is allowed to pause while it loads from slower memory. Dual Port RAM would allow a FIFO style load. External memory could be WORD, BYTE or even serial ( FPGA_Stamp :) - Other Block RAMS are standard DATA rams, including fast context register switching for interrupts / param passing. Design ends up with a single CPU, but two distinct areas of FAST and SLOW code and data. Does anyone know of work using this HW focus on FPGA cores ? - jg ###### Message-ID: <3FB15BB3.5B87@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 11 Date: Wed, 12 Nov 2003 10:59:15 +1300 NNTP-Posting-Host: 210.246.2.115 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1068587969 210.246.2.115 (Wed, 12 Nov 2003 10:59:29 NZDT) NNTP-Posting-Date: Wed, 12 Nov 2003 10:59:29 NZDT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshosting.com!news-xfer1.atl.newshosting.com!news-out.superfeed.net!propagator2-maxim!news-in-maxim.spamkiller.net!news02.tsnz.net!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35442 H. Peter Anvin wrote: > > I have no way to know how this is turning out. My current goal is to > make sure it implements in < 1000 LEs on Cyclone, without using > blockRAM for the register file. Isn't some form of BlockRAM a defacto standard on all 'consider for new design' FPGAs - so not using that would restrict your options ? -jg ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Tue, 11 Nov 2003 17:46:18 -0500 Organization: Arius, Inc Lines: 29 Message-ID: <3FB166BA.3B81712E@yahoo.com> References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB15BB3.5B87@designtools.co.nz> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZ0UATWpfOm8kbdvvqCHo00wYjPtifTEx+N5py+tBhOEYFV3PycqAzj X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 11 Nov 2003 22:46:23 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!solnet.ch!solnet.ch!newsfeed.tiscali.ch!feed.news.nacamar.de!rcn!feed3.news.rcn.net!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35445 Jim Granville wrote: > > H. Peter Anvin wrote: > > > > I have no way to know how this is turning out. My current goal is to > > make sure it implements in < 1000 LEs on Cyclone, without using > > blockRAM for the register file. > > Isn't some form of BlockRAM a defacto standard on all > 'consider for new design' FPGAs - so not using that would > restrict your options ? > > -jg So are hardware multipliers these days. I believe all the latest chips have them as well as multi-standard IOs. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Tue, 11 Nov 2003 15:12:43 -0800 Organization: Xilinx,Inc Lines: 9 Message-ID: <3FB16CEB.C46327DE@xilinx.com> References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB15BB3.5B87@designtools.co.nz> <3FB166BA.3B81712E@yahoo.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: rickman Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!newsfeed.berkeley.edu!ucberkeley!ihnp4.ucsd.edu!usc.edu!news.usc.edu!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35447 I am convinced that a generic version would inevitably be inferior in performance and/or price, compared to the dedicated one. I know that Ken and Göran used many Xilinx-specific features when they designed PicoBlaze and MicroBlaze. And I assume that the Altera guys were operating in a comparable way when they designed Nios. The generic ones will be the "worst of both worlds", unless you really believe in clairvoyant synthesis. Peter Alfke, Xilinx ###### From: bpride@monad.net (Bruce P.) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: 11 Nov 2003 18:28:22 -0800 Organization: http://groups.google.com Lines: 13 Message-ID: <762349e4.0311111828.6ad1e351@posting.google.com> References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB15BB3.5B87@designtools.co.nz> <3FB166BA.3B81712E@yahoo.com> <3FB16CEB.C46327DE@xilinx.com> NNTP-Posting-Host: 12.148.161.151 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1068604102 23981 127.0.0.1 (12 Nov 2003 02:28:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 12 Nov 2003 02:28:22 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35450 > I am convinced that a generic version would inevitably be inferior in > performance and/or price, compared to the dedicated one. But, there's nothing like rolling your own for fun/educational purposes and then having something useful at the end of it all. I think it would also be easier to add new features and enhancements to your own design since the code was developed in your own way of thinking and coding style. In the end, maybe it will just be "yet another RISC core" on opencores.org, but at least it's yours and you'll have a good understanding of it's capabilities...even if all it can do is blink an LED! BP ###### From: H. Peter Anvin Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Organization: Transmeta Corporation, Santa Clara CA Lines: 28 Sender: hpa@cesium.transmeta.com Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB15BB3.5B87@designtools.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: jim.granville@designtools.co.nz Disclaimer: Not speaking for Transmeta in any way, shape, or form. Copyright: Copyright 2003 H. Peter Anvin - All Rights Reserved Cache-Post-Path: palladium.transmeta.com!unknown@cesium.transmeta.com X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Date: 11 Nov 2003 21:33:17 -0800 NNTP-Posting-Host: 63.209.4.196 X-Complaints-To: news@globix.net X-Trace: news.sjc.globix.net 1068615172 63.209.4.196 (Tue, 11 Nov 2003 21:32:52 PST) NNTP-Posting-Date: Tue, 11 Nov 2003 21:32:52 PST Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!pln-w!extra.newsguy.com!lotsanews.com!cyclone-sf.pbi.net!209.10.34.151!newsfeed.sjc.globix.net!news.sjc.globix.net!cesium.transmeta.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35453 Followup to: <3FB15BB3.5B87@designtools.co.nz> By author: jim.granville@designtools.co.nz In newsgroup: comp.arch.fpga > > H. Peter Anvin wrote: > > > > I have no way to know how this is turning out. My current goal is to > > make sure it implements in < 1000 LEs on Cyclone, without using > > blockRAM for the register file. > > Isn't some form of BlockRAM a defacto standard on all > 'consider for new design' FPGAs - so not using that would > restrict your options ? > Some form thereof, yes, but I tend to run out of blockram a lot faster than running out of LUTs. Note that it's not that I'm saying you couldn't use it, I'm saying I want to be at < 1000 LE without using blockram. About 300-400 of that would be replacable with a blockram. -hpa -- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64 ###### From: H. Peter Anvin Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Organization: Transmeta Corporation, Santa Clara CA Lines: 24 Sender: hpa@cesium.transmeta.com Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FB15BB3.5B87@designtools.co.nz> <3FB166BA.3B81712E@yahoo.com> <3FB16CEB.C46327DE@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: Peter Alfke Disclaimer: Not speaking for Transmeta in any way, shape, or form. Copyright: Copyright 2003 H. Peter Anvin - All Rights Reserved Cache-Post-Path: palladium.transmeta.com!unknown@cesium.transmeta.com X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Date: 11 Nov 2003 21:34:11 -0800 NNTP-Posting-Host: 63.209.4.196 X-Complaints-To: news@globix.net X-Trace: news.sjc.globix.net 1068615225 63.209.4.196 (Tue, 11 Nov 2003 21:33:45 PST) NNTP-Posting-Date: Tue, 11 Nov 2003 21:33:45 PST Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!pln-w!extra.newsguy.com!lotsanews.com!cyclone-sf.pbi.net!209.10.34.151!newsfeed.sjc.globix.net!news.sjc.globix.net!cesium.transmeta.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35454 Followup to: <3FB16CEB.C46327DE@xilinx.com> By author: Peter Alfke In newsgroup: comp.arch.fpga > > I am convinced that a generic version would inevitably be inferior in > performance and/or price, compared to the dedicated one. I know that Ken > and Göran used many Xilinx-specific features when they designed > PicoBlaze and MicroBlaze. And I assume that the Altera guys were > operating in a comparable way when they designed Nios. > The generic ones will be the "worst of both worlds", unless you really > believe in clairvoyant synthesis. > Of course. But it would have the advantage that it could run on either. -hpa -- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64 From: H. Peter Anvin Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Organization: Transmeta Corporation, Santa Clara CA Lines: 24 Sender: hpa@cesium.transmeta.com Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FB15BB3.5B87@designtools.co.nz> <3FB166BA.3B81712E@yahoo.com> <3FB16CEB.C46327DE@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: Peter Alfke Disclaimer: Not speaking for Transmeta in any way, shape, or form. Copyright: Copyright 2003 H. Peter Anvin - All Rights Reserved Cache-Post-Path: palladium.transmeta.com!unknown@cesium.transmeta.com X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Date: 11 Nov 2003 21:34:11 -0800 NNTP-Posting-Host: 63.209.4.196 X-Complaints-To: news@globix.net X-Trace: news.sjc.globix.net 1068615225 63.209.4.196 (Tue, 11 Nov 2003 21:33:45 PST) NNTP-Posting-Date: Tue, 11 Nov 2003 21:33:45 PST Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!pln-w!extra.newsguy.com!lotsanews.com!cyclone-sf.pbi.net!209.10.34.151!newsfeed.sjc.globix.net!news.sjc.globix.net!cesium.transmeta.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35454 Followup to: <3FB16CEB.C46327DE@xilinx.com> By author: Peter Alfke In newsgroup: comp.arch.fpga > > I am convinced that a generic version would inevitably be inferior in > performance and/or price, compared to the dedicated one. I know that Ken > and Göran used many Xilinx-specific features when they designed > PicoBlaze and MicroBlaze. And I assume that the Altera guys were > operating in a comparable way when they designed Nios. > The generic ones will be the "worst of both worlds", unless you really > believe in clairvoyant synthesis. > Of course. But it would have the advantage that it could run on either. -hpa -- at work, in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64 ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Wed, 12 Nov 2003 10:02:03 -0500 Organization: Arius, Inc Lines: 34 Message-ID: <3FB24B6B.18895DA8@yahoo.com> References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB15BB3.5B87@designtools.co.nz> <3FB166BA.3B81712E@yahoo.com> <3FB16CEB.C46327DE@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: UmFuZG9tSVYY+cONQgUfVnBbXfXUofv+kwXi6IXir2hmWMLKl6rsJd8Kyck7OQtN X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 12 Nov 2003 15:02:13 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.cwix.com!feed1.news.rcn.net!rcn!feed3.news.rcn.net!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35469 Peter Alfke wrote: > > I am convinced that a generic version would inevitably be inferior in > performance and/or price, compared to the dedicated one. I know that Ken > and Göran used many Xilinx-specific features when they designed > PicoBlaze and MicroBlaze. And I assume that the Altera guys were > operating in a comparable way when they designed Nios. > The generic ones will be the "worst of both worlds", unless you really > believe in clairvoyant synthesis. > > Peter Alfke, Xilinx "Clairvoyant Synthesis", now that sounds like a good product! Is there a startup somewhere working on that? I can see product announcements touting the new FPGA CS that eliminates the need for product planners, designers and even testing as it would already know that the design was ready for production! No specs to write, no coding to compile and even simulation could be skipped. Just think of the design you want and out pops a bit file. Boy, what will they think of next? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Wed, 12 Nov 2003 10:06:11 -0500 Organization: Arius, Inc Lines: 41 Message-ID: <3FB24C63.2A1D807D@yahoo.com> References: <762349e4.0311091130.6464de51@posting.google.com> <762349e4.0311101431.24595dcb@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB15BB3.5B87@designtools.co.nz> <3FB166BA.3B81712E@yahoo.com> <3FB16CEB.C46327DE@xilinx.com> <762349e4.0311111828.6ad1e351@posting.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbriKuMsdHZoTSW1We0YRXvsD9Bz4C6TOR9m2odykglLFeVh107kooe X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 12 Nov 2003 15:06:22 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed1.news.rcn.net!rcn!feed3.news.rcn.net!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35470 "Bruce P." wrote: > > > I am convinced that a generic version would inevitably be inferior in > > performance and/or price, compared to the dedicated one. > > But, there's nothing like rolling your own for fun/educational > purposes and then having something useful at the end of it all. I > think it would also be easier to add new features and enhancements to > your own design since the code was developed in your own way of > thinking and coding style. In the end, maybe it will just be "yet > another RISC core" on opencores.org, but at least it's yours and > you'll have a good understanding of it's capabilities...even if all it > can do is blink an LED! > > BP When I was in school we worked on a paper design of a microcoded processor as a teaching tool. We had homework on it and had to design new features on our exams. I even had a question about it on my Masters comprehensive exam. I approached my professor about designing a simulation of it to run on the Univac mainframe for the undergrad students to learn from. But I guess I was ahead of my time as he did not see the value in that. Or maybe he had the foresight to see the complications it might create :) I guess this is a pretty common thing at Universities now. All they have to do is get you a FPGA design package with a simulator. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: jerry@quickcores.com (Jerry D. Harthcock) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: 12 Nov 2003 07:26:59 -0800 Organization: http://groups.google.com Lines: 53 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FAFFAE7.2939@designtools.co.nz> NNTP-Posting-Host: 206.176.155.179 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1068650819 10653 127.0.0.1 (12 Nov 2003 15:26:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 12 Nov 2003 15:26:59 +0000 (UTC) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!takemy.news.telefonica.de!telefonica.de!news.tele.dk!news.tele.dk!small.news.tele.dk!news.maxwell.syr.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35473 Hello Jim, For the most part, I agree with your legal analysis regarding cloning cores. The primary issues have to do with whether or not an architecture is protected by patent and if not, how you market or use the resulting clone so as not to infringe existing copyrights, trademarks, trade dress or confidentiality/license agreements. But in my view, this is not the main issue with cloning an existing architecture. The main issue has to do with how you are going to debug it once you get it into an FPGA wherein it is completely embedded with no address or data lines coming out. Accordingly, I'd like to take this opportunity to simply state that I've posted developmental versions of both my 8051 and 6805 microcontroller cores for free downloading at www.quickcores.com. The 8051 is in original Verilog RTL format and includes on-chip JTAG real-time monitoring and debug logic, including 144-channel trace buffer. I've successfully synthesized them using Synplify and Quartus II web edition. If anyone would like to start a thread about how the JTAG real-time monitor works, I'd be happy to engage. Regards, Jerry D. Harthcock QuickCores p.s., I also have the 9-bit RISC which I'd be happy to post if anyone is interested. Jim Granville wrote in message news:<3FAFFAE7.2939@designtools.co.nz>... > Symon wrote: > > > > Hi Goran, > > So, playing devli's advocate, Xilinx wouldn't mind if the clean room > > Microblaze was targeted at their competitors' devices? Or do you think that > > no one would do this because Microblaze only efficiently fits the Xilinx > > devices? Or the competitors have their own solutions for their parts? > > I wonder.... > > Xilinx's protection does not come from attack on the clean room clone, > but rather from the protection of the Microblaze name, and tool flows. > So, anyone would be free to create an opcode compatible core, > if they wished, but not to use the brand, nor the Xilinx tool flows. > > Older uC cores are easier to copy (any patents lapsed), and their tools > are widely available. Things like 80C51, 6502, Z8, and even 8085.... > ( someone must have done a 8048 core ? :) > > -jg ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Wed, 12 Nov 2003 18:26:43 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 23 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FB1539C.160F@designtools.co.nz> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1068661603 37312 128.32.112.203 (12 Nov 2003 18:26:43 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Wed, 12 Nov 2003 18:26:43 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!elnk-pas-nf1!newsfeed.earthlink.net!newsfeed.sjc.globix.net!cyclone-sf.pbi.net!216.218.192.242!news.he.net!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35484 In article , H. Peter Anvin wrote: >Some vendors have 9/18-bit blockRAMs, some don't. I'm trying to be as >generic as possible. It also makes it easier to port tools like >gas/binutils/gcc. Both Brand A and Brand X have midsize (8-16 bit wide + parity, with >128 addresses in that range) memories, and any other viable FPGA will as well. Thus it is safe to have parameterized cache and register file with instantiates the correct size memories, as part of your design, and still remain vendor neutral. You WANT to use these devices for both register file and memory. The thing that Brand A is missing are the SRL16/LUT as RAM features which give very small memories (16-64x1b), while Brand X all the BlockRAMs (midsized memories) are the same size while Brand A's memories come in different sizes. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Wed, 12 Nov 2003 18:29:03 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 23 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <3FB15BB3.5B87@designtools.co.nz> <3FB166BA.3B81712E@yahoo.com> <3FB16CEB.C46327DE@xilinx.com> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1068661743 37312 128.32.112.203 (12 Nov 2003 18:29:03 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Wed, 12 Nov 2003 18:29:03 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35485 In article <3FB16CEB.C46327DE@xilinx.com>, Peter Alfke wrote: >I am convinced that a generic version would inevitably be inferior in >performance and/or price, compared to the dedicated one. I know that Ken >and Göran used many Xilinx-specific features when they designed >PicoBlaze and MicroBlaze. And I assume that the Altera guys were >operating in a comparable way when they designed Nios. >The generic ones will be the "worst of both worlds", unless you really >believe in clairvoyant synthesis. I think generic will be inferior, but not THAT inferior, given the register files and caches can and should be done in the "everyone has" BlockRAMs. But in order to make it generic, these structures will probably need target-specific parameters and options (dual ported or not, size range) which are instantiated. Also, the other big disadvantage in the generic version is going to be a lack of placement. Placement is good for 10-30% performanec increases. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: "Symon" Newsgroups: comp.arch.fpga Subject: Re: Home grown CPU core legal? Date: Wed, 12 Nov 2003 11:51:16 -0800 Lines: 53 Message-ID: References: <762349e4.0311091130.6464de51@posting.google.com> <6Uasb.123195$mZ5.829826@attbi_s54> <3FB15BB3.5B87@designtools.co.nz> NNTP-Posting-Host: 67-121-165-33.ded.pacbell.net (67.121.165.33) X-Trace: news.uni-berlin.de 1068666997 53704127 67.121.165.33 (16 [212844]) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!fu-berlin.de!uni-berlin.de!67-121-165-33.ded.pacbell.NET!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:35489 Hi Peter, Yeah, the home built processor is great fun. I did a Xilinx VirtexII one when the parts first appeared and learnt a lot about the carry chain, those FMUX thingies, and the mighty 'mult_and'! It also teaches you a lot about the dual port block rams and multipliers. I called it nanoblaze, kind of halfway between Micro and Pico, because it used about 250 LUTs, 16 bits, 16 GP regs in a LUT RAM file, stack and program in a block ram, multiply instruction with the hard multiplier. If you target a particular architecture you can get suprisingly good performance, I got ~90MIPS in a VirtexII-slowestgrade, non-pipelined, i.e. 1 clock per most instructions including conditional relative jumps. Even single cycle interrupts! Once again, as you can tell(!!), I found it great fun, and an excellent way to learn about the fabric of the FPGA. Also, can teach you a lot about floorplanning and performance optimisation. I also used it to learn PERL to write the assembler, which was probably the best thing to come out of the whole project! BUT... I'd almost certainly NOT use it in a commercial product, too much documentation involved and soon every FPGA will have a hard processor anyway. Good luck, Syms. "H. Peter Anvin" wrote in message news:bosgmt$n0i$1@cesium.transmeta.com... > Followup to: <3FB15BB3.5B87@designtools.co.nz> > By author: jim.granville@designtools.co.nz > In newsgroup: comp.arch.fpga > > > > H. Peter Anvin wrote: > > > > > > I have no way to know how this is turning out. My current goal is to > > > make sure it implements in < 1000 LEs on Cyclone, without using > > > blockRAM for the register file. > > > > Isn't some form of BlockRAM a defacto standard on all > > 'consider for new design' FPGAs - so not using that would > > restrict your options ? > > > > Some form thereof, yes, but I tend to run out of blockram a lot faster > than running out of LUTs. Note that it's not that I'm saying you > couldn't use it, I'm saying I want to be at < 1000 LE without using > blockram. About 300-400 of that would be replacable with a blockram. > > -hpa > > > -- > at work, in private! > If you send me mail in HTML format I will assume it's spam. > "Unix gives you enough rope to shoot yourself in the foot." > Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64