From: "jakab tanko" Newsgroups: comp.arch.fpga Subject: USB transceiver for FPGA Date: Mon, 15 Sep 2003 09:49:33 -0400 Organization: Storm Internet Services Lines: 11 Sender: ics@gw-interactive-cir-sys.storm.ca Message-ID: NNTP-Posting-Host: gw-interactive-cir-sys.storm.ca X-Trace: news.storm.ca 1063633872 19471 209.87.237.58 (15 Sep 2003 13:51:12 GMT) X-Complaints-To: abuse@storm.ca NNTP-Posting-Date: 15 Sep 2003 13:51:12 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4927.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4927.1200 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.space.net!feed.news.nacamar.de!news.maxwell.syr.edu!east1.newsfeed.sprint-canada.net!news.storm.ca!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:32971 Hi, I am looking for an USB transceiver chip that can be interfaced to an FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. Any suggestions? Thanks, --- jakab ###### Reply-To: "Nial Stewart" From: "Nial Stewart" Newsgroups: comp.arch.fpga References: Subject: Re: USB transceiver for FPGA Date: Mon, 15 Sep 2003 15:25:56 +0100 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Lines: 35 Message-ID: <3f65cb6d$0$10961$fa0fcedb@lovejoy.zen.co.uk> Organization: Zen Internet NNTP-Posting-Host: 217.155.72.198 X-Trace: 1063635821 lovejoy.zen.co.uk 10961 217.155.72.198 X-Complaints-To: abuse@zen.co.uk Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!zen.net.uk!lovejoy.zen.co.uk.POSTED!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:32973 jakab tanko wrote in message news:bk4g4g$j0f$1@news.storm.ca... > Hi, > > I am looking for an USB transceiver chip that can be interfaced to an > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > Any suggestions? The FTDI 245BM sounds like what you want (although it's only 1.1). See.. http://www.ftdichip.com/ ..for details. I've a board based on this I built for my own use (see under downloads on my web site). I've a couple sitting here that someone said they wanted but money hasn't been forthcoming. Yours for £30 each if you want one/both for prototyping. See my downloads page for details of an example project showing how to drive it, it's relatively easy. Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.uk ###### NNTP-Posting-Date: Mon, 15 Sep 2003 14:26:29 -0500 From: "Colin Jackson" Newsgroups: comp.arch.fpga References: Subject: Re: USB transceiver for FPGA Date: Mon, 15 Sep 2003 15:26:24 -0400 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: <1sOdnZlEhZ77j_uiU-KYuA@comcast.com> Lines: 22 NNTP-Posting-Host: 66.176.51.78 X-Trace: sv3-DPja5vYSB4eSGVLaSgYlKUtu++j6vJqRMl9M/5JEFkKAMGyIkiclyoTlzejC6P5Skv8pltpEqc0O6Wk!n3pJHncBhYxZvzWu1r28Xm0wqoaojbnGWHvXmtFB//ZcmRC9LkvFCCver5ma X-Complaints-To: abuse@comcast.net X-DMCA-Complaints-To: dmca@comcast.net X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.1 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!proxad.net!proxad.net!216.166.71.118.MISMATCH!small1.nntp.aus1.giganews.com!border1.nntp.aus1.giganews.com!intern1.nntp.aus1.giganews.com!nntp.giganews.com!nntp.comcast.com!news.comcast.com.POSTED!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:32980 I'm working on a project with USB to a XILINX FPGA. The interface chip I'm going with is Phillips ISP-1501 http://www.semiconductors.philips.com/cgi-bin/pldb/pip/isp1501 Good Luck, Colin "jakab tanko" wrote in message news:bk4g4g$j0f$1@news.storm.ca... > Hi, > > I am looking for an USB transceiver chip that can be interfaced to an > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > Any suggestions? > > Thanks, > --- > jakab > > ###### From: "jakab tanko" Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Mon, 15 Sep 2003 17:04:18 -0400 Organization: Storm Internet Services Lines: 34 Sender: ics@gw-interactive-cir-sys.storm.ca Message-ID: References: <1sOdnZlEhZ77j_uiU-KYuA@comcast.com> NNTP-Posting-Host: gw-interactive-cir-sys.storm.ca X-Trace: news.storm.ca 1063659956 26082 209.87.237.58 (15 Sep 2003 21:05:56 GMT) X-Complaints-To: abuse@storm.ca NNTP-Posting-Date: 15 Sep 2003 21:05:56 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4927.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4927.1200 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!east1.newsfeed.sprint-canada.net!news.storm.ca!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:32983 I have looked at that one some time ago but there was a message on the Philips website that the chip is going obsolete and that scared me away... I tried to confirm with the Philips rep. here in Ottawa,Canada but all I got to talk to was an answering machine!. Did you manage to get an eval board for it? --- jakab "Colin Jackson" wrote in message news:1sOdnZlEhZ77j_uiU-KYuA@comcast.com... > I'm working on a project with USB to a XILINX FPGA. > The interface chip I'm going with is Phillips ISP-1501 > http://www.semiconductors.philips.com/cgi-bin/pldb/pip/isp1501 > > Good Luck, > Colin > > "jakab tanko" wrote in message > news:bk4g4g$j0f$1@news.storm.ca... > > Hi, > > > > I am looking for an USB transceiver chip that can be interfaced to an > > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > > Any suggestions? > > > > Thanks, > > --- > > jakab > > > > > > ###### From: "jakab tanko" Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Mon, 15 Sep 2003 17:07:22 -0400 Organization: Storm Internet Services Lines: 44 Sender: ics@gw-interactive-cir-sys.storm.ca Message-ID: References: <3f65cb6d$0$10961$fa0fcedb@lovejoy.zen.co.uk> NNTP-Posting-Host: gw-interactive-cir-sys.storm.ca X-Trace: news.storm.ca 1063660141 26088 209.87.237.58 (15 Sep 2003 21:09:01 GMT) X-Complaints-To: abuse@storm.ca NNTP-Posting-Date: 15 Sep 2003 21:09:01 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4927.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4927.1200 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!east1.newsfeed.sprint-canada.net!news.storm.ca!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:32984 Thanks for the suggestion, it looks like they also have USB 2.0 chip, the board you have looks interesting too. I will search a bit more before deciding. --- jakab "Nial Stewart" wrote in message news:3f65cb6d$0$10961$fa0fcedb@lovejoy.zen.co.uk... > jakab tanko wrote in message > news:bk4g4g$j0f$1@news.storm.ca... > > Hi, > > > > I am looking for an USB transceiver chip that can be interfaced to an > > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > > Any suggestions? > > The FTDI 245BM sounds like what you want (although it's only 1.1). > > See.. > > http://www.ftdichip.com/ > > ..for details. > > I've a board based on this I built for my own use (see under > downloads on my web site). I've a couple sitting here that > someone said they wanted but money hasn't been forthcoming. > > Yours for £30 each if you want one/both for prototyping. > > See my downloads page for details of an example project showing > how to drive it, it's relatively easy. > > > Nial Stewart > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.uk > > > ###### From: khimbittle@cliftonREMOVEsystems.com (Khim Bittle) Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Mon, 15 Sep 2003 23:43:07 GMT Organization: Clifton Systems Inc. Lines: 55 Message-ID: <3f664d82.5566451@news.compuserve.com> References: <3f65cb6d$0$10961$fa0fcedb@lovejoy.zen.co.uk> Reply-To: khimbittle@cliftonREMOVEsystems.com NNTP-Posting-Host: mid-tgn-nen-vty83.as.wcom.net X-Trace: ngspool-d02.news.aol.com 1063669221 19415 216.192.69.83 (15 Sep 2003 23:40:21 GMT) X-Complaints-To: newsmaster@compuserve.com NNTP-Posting-Date: Mon, 15 Sep 2003 23:40:21 +0000 (UTC) X-Newsreader: Forte Free Agent 1.21/32.243 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newscore.univie.ac.at!skynet.be!skynet.be!ngpeer.news.aol.com!news.compuserve.com!news-master.compuserve.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:32991 On Mon, 15 Sep 2003 17:07:22 -0400, "jakab tanko" wrote: >Thanks for the suggestion, it looks like they also have USB 2.0 chip, >the board you have looks interesting too. I will search a bit more before >deciding. Their chip will not run USB2.0 high speed, only full speed. ( I have been able to get 1 MB/sec max on a real board ) Otherwise it is great, I have used it on several boards. They are going to have a high speed chip but it is at least a year off as it is just in planning , this is a major bummer for my projects. >--- >jakab >"Nial Stewart" wrote in message >news:3f65cb6d$0$10961$fa0fcedb@lovejoy.zen.co.uk... >> jakab tanko wrote in message >> news:bk4g4g$j0f$1@news.storm.ca... >> > Hi, >> > >> > I am looking for an USB transceiver chip that can be interfaced to an >> > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. >> > Any suggestions? >> >> The FTDI 245BM sounds like what you want (although it's only 1.1). >> >> See.. >> >> http://www.ftdichip.com/ >> >> ..for details. >> >> I've a board based on this I built for my own use (see under >> downloads on my web site). I've a couple sitting here that >> someone said they wanted but money hasn't been forthcoming. >> >> Yours for £30 each if you want one/both for prototyping. >> >> See my downloads page for details of an example project showing >> how to drive it, it's relatively easy. >> >> >> Nial Stewart >> >> ------------------------------------------------ >> Nial Stewart Developments Ltd >> FPGA and High Speed Digital Design >> www.nialstewartdevelopments.co.uk >> >> >> > > ###### From: "Kenneth Land" Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Mon, 15 Sep 2003 19:11:11 -0500 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 X-Complaints-To: abuse@supernews.com Lines: 22 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-01!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:32995 Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? I looked very closely at the 1.1 version and found it took only 6 pins and $1.75 transceiver chip. Ken "jakab tanko" wrote in message news:bk4g4g$j0f$1@news.storm.ca... > Hi, > > I am looking for an USB transceiver chip that can be interfaced to an > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > Any suggestions? > > Thanks, > --- > jakab > > ###### From: antti@case2000.com (Antti Lukats) Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: 16 Sep 2003 00:48:54 -0700 Organization: http://groups.google.com/ Lines: 12 Message-ID: <80a3aea5.0309152348.5ffd5049@posting.google.com> References: NNTP-Posting-Host: 80.142.121.58 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1063698535 13886 127.0.0.1 (16 Sep 2003 07:48:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 16 Sep 2003 07:48:55 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news.linkpendium.com!nntp-relay.ihug.net!ihug.co.nz!nntp.cs.ubc.ca!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33009 "Kenneth Land" wrote in message news:... > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > I looked very closely at the 1.1 version and found it took only 6 pins and > $1.75 transceiver chip. > > Ken there is a japanese design (VHDL, and Visual basic host example) that uses no tranceiver at all, ie USB DM,DP directly to FPGa antti ###### From: "Ken Land" Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Tue, 16 Sep 2003 08:55:40 -0500 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <80a3aea5.0309152348.5ffd5049@posting.google.com> X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.3790.0 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.3790.0 X-Complaints-To: abuse@supernews.com Lines: 30 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-out1.nntp.be!propagator2-sterling!news-in-sterling.newsfeed.com!pd2nf1so.cg.shawcable.net!residential.shaw.ca!sn-xit-03!sn-xit-01!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33023 Is it free? :) That is very interesting and that is what I went looking for. I imagined the logic in the FPGA would wiggle D+ and D- appropriately. I understand that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1 might be doable. I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0? Of course going to Stratix would negate any BOM savings. Ken "Antti Lukats" wrote in message news:80a3aea5.0309152348.5ffd5049@posting.google.com... > "Kenneth Land" wrote in message news:... > > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > > > I looked very closely at the 1.1 version and found it took only 6 pins and > > $1.75 transceiver chip. > > > > Ken > > there is a japanese design (VHDL, and Visual basic host example) > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > antti ###### From: "jakab tanko" Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Tue, 16 Sep 2003 11:38:22 -0400 Organization: Storm Internet Services Lines: 43 Sender: ics@gw-interactive-cir-sys.storm.ca Message-ID: References: <80a3aea5.0309152348.5ffd5049@posting.google.com> NNTP-Posting-Host: gw-interactive-cir-sys.storm.ca X-Trace: news.storm.ca 1063726803 14130 209.87.237.58 (16 Sep 2003 15:40:03 GMT) X-Complaints-To: abuse@storm.ca NNTP-Posting-Date: 16 Sep 2003 15:40:03 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4927.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4927.1200 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!east1.newsfeed.sprint-canada.net!news.storm.ca!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33024 480 MHz LVDS IO is not out of question on Xilinx FPGAs (Altera ? don't know) in terms of frequency; what I question is the voltage/current levels to/from the USB, have to dig into the USB spec to figure this one out. Any pointers to this japanese design or its documentation? --- jakab "Ken Land" wrote in message news:vme5iv66sv911@news.supernews.com... > Is it free? :) > > That is very interesting and that is what I went looking for. I imagined > the logic in the FPGA would wiggle D+ and D- appropriately. I understand > that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1 > might be doable. > > I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0? Of > course going to Stratix would negate any BOM savings. > > Ken > > "Antti Lukats" wrote in message > news:80a3aea5.0309152348.5ffd5049@posting.google.com... > > "Kenneth Land" wrote in message > news:... > > > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > > > > > I looked very closely at the 1.1 version and found it took only 6 pins > and > > > $1.75 transceiver chip. > > > > > > Ken > > > > there is a japanese design (VHDL, and Visual basic host example) > > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > > > antti > > ###### NNTP-Posting-Date: Tue, 16 Sep 2003 10:40:23 -0500 From: "Colin Jackson" Newsgroups: comp.arch.fpga References: <1sOdnZlEhZ77j_uiU-KYuA@comcast.com> Subject: Re: USB transceiver for FPGA Date: Tue, 16 Sep 2003 11:40:16 -0400 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Lines: 50 NNTP-Posting-Host: 66.176.51.78 X-Trace: sv3-ntkS+SlC/P2rvs+S3K1jpIqyToqegTll4Q2EkjmzF4cru3fCipwXkZ5N5SJNT2+UxGArAUp4anrtHtE!4072vCY15ll/XLMMB3YENndkSPOw4HCoF+EErERKZf6s4L/Z+2D43aMw/RRl X-Complaints-To: abuse@comcast.net X-DMCA-Complaints-To: dmca@comcast.net X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.1 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-out1.nntp.be!propagator2-sterling!news-in-sterling.nuthinbutnews.com!cyclone1.gnilink.net!small1.nntp.aus1.giganews.com!border1.nntp.aus1.giganews.com!intern1.nntp.aus1.giganews.com!nntp.giganews.com!nntp.comcast.com!news.comcast.com.POSTED!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33025 We were just sending the design to the layout guys. What's that saying? "Don't shoot the messenger!!!" Thanks for the heads up. Years ago Phillips did the same thing to me on a stepper driver. They need to forecast a little better. Now that I've been burned twice I think it's time to take them off my "favorites" list. (I think I said that last time.) I never looked into the eval board. Colin "jakab tanko" wrote in message news:bk59jk$pf2$1@news.storm.ca... > I have looked at that one some time ago but there was a message on > the Philips website that the chip is going obsolete and that scared me > away... > I tried to confirm with the Philips rep. here in Ottawa,Canada but > all I got to talk to was an answering machine!. Did you manage to get an > eval board for it? > --- > jakab > "Colin Jackson" wrote in message > news:1sOdnZlEhZ77j_uiU-KYuA@comcast.com... > > I'm working on a project with USB to a XILINX FPGA. > > The interface chip I'm going with is Phillips ISP-1501 > > http://www.semiconductors.philips.com/cgi-bin/pldb/pip/isp1501 > > > > Good Luck, > > Colin > > > > "jakab tanko" wrote in message > > news:bk4g4g$j0f$1@news.storm.ca... > > > Hi, > > > > > > I am looking for an USB transceiver chip that can be interfaced to an > > > FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok. > > > Any suggestions? > > > > > > Thanks, > > > --- > > > jakab > > > > > > > > > > > > ###### From: antti@case2000.com (Antti Lukats) Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: 16 Sep 2003 11:18:32 -0700 Organization: http://groups.google.com/ Lines: 11 Message-ID: <80a3aea5.0309161018.7d241a8d@posting.google.com> References: <80a3aea5.0309152348.5ffd5049@posting.google.com> NNTP-Posting-Host: 80.142.90.123 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1063736313 22875 127.0.0.1 (16 Sep 2003 18:18:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 16 Sep 2003 18:18:33 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33035 "Ken Land" wrote in message news:... > Is it free? :) its free but I cant give yout the url, tried to find it again for you but failed, searching on japanese sites is a bit difficult :) it is from some-one who wrote it for XSP-009 board, but there are no links to it from XSP-009 official site(s) as much as I see. I have the files, can send you per email if you wish, let me know antti ###### From: Lasse Langwadt Christensen Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Tue, 16 Sep 2003 20:36:54 +0200 Organization: Cybercity Lines: 22 Message-ID: <3F675846.1090007@ieee.org> References: <80a3aea5.0309152348.5ffd5049@posting.google.com> NNTP-Posting-Host: port354.ds1-abc.adsl.cybercity.dk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.cybercity.dk 1063737390 42999 217.157.139.107 (16 Sep 2003 18:36:30 GMT) X-Complaints-To: abuse@cybercity.dk NNTP-Posting-Date: Tue, 16 Sep 2003 18:36:30 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-us, en Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!npeer.de.kpn-eurorings.net!newsfeed.kabelfoon.nl!195.129.110.21.MISMATCH!bnewsfeed00.bru.ops.eu.uu.net!bnewsinpeer01.bru.ops.eu.uu.net!emea.uu.net!news.cybercity.dk!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33041 Antti Lukats wrote: > "Kenneth Land" wrote in message news:... > >>Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? >> >>I looked very closely at the 1.1 version and found it took only 6 pins and >>$1.75 transceiver chip. >> >>Ken > > > there is a japanese design (VHDL, and Visual basic host example) > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > antti I've thought about that, two pins programmed for 3V3-cmos should be good for tx and rx of SE0 but I never got around to checking if one of the differential standards on the FPGA would be within spec for USB? -Lasse ###### From: antti@case2000.com (Antti Lukats) Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: 16 Sep 2003 11:52:54 -0700 Organization: http://groups.google.com/ Lines: 9 Message-ID: <80a3aea5.0309161052.6ea1cb11@posting.google.com> References: <80a3aea5.0309152348.5ffd5049@posting.google.com> NNTP-Posting-Host: 80.142.90.123 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1063738375 25157 127.0.0.1 (16 Sep 2003 18:52:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 16 Sep 2003 18:52:55 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33044 "Ken Land" wrote in message news:... > Is it free? :) google usb.lzh => http://member.nifty.ne.jp/fpga/freeip/usb/ :) found! antti ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Tue, 16 Sep 2003 14:53:40 -0400 Organization: Arius, Inc Lines: 44 Message-ID: <3F675C34.6EE3FCBF@yahoo.com> References: <80a3aea5.0309152348.5ffd5049@posting.google.com> <3F675846.1090007@ieee.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVaiJa17zgLKb/2tn3sB3Lj4GE5C+tDPu+Uy3I5JpJ7Zx3CgU9yrYDwy X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 16 Sep 2003 18:53:47 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!in.100proofnews.com!in.100proofnews.com!elnk-atl-nf1!newsfeed.earthlink.net!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33045 Lasse Langwadt Christensen wrote: > > Antti Lukats wrote: > > "Kenneth Land" wrote in message news:... > > > >>Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > >> > >>I looked very closely at the 1.1 version and found it took only 6 pins and > >>$1.75 transceiver chip. > >> > >>Ken > > > > > > there is a japanese design (VHDL, and Visual basic host example) > > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > > > antti > > I've thought about that, two pins programmed for 3V3-cmos should be good > for tx and rx of SE0 but I never got around to checking if one of the > differential standards on the FPGA would be within spec for USB? > > -Lasse It has been awhile since I looked at the USB spec, but I seem to recall that there is a non-standard state that is used to signal the rate or some other aspect of the interface. I want to say this state is both signals high or both low at the same time. Am I out to lunch on this? If there is a non-standard state on these pins, you would not be able to use an LVDS driver. You would need two independant outputs. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: johnp3+nospam@probo.com (John Providenza) Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: 16 Sep 2003 14:16:15 -0700 Organization: http://groups.google.com/ Lines: 44 Message-ID: <349ef8f4.0309161316.62c75235@posting.google.com> References: <80a3aea5.0309152348.5ffd5049@posting.google.com> NNTP-Posting-Host: 63.105.24.220 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1063746978 2501 127.0.0.1 (16 Sep 2003 21:16:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 16 Sep 2003 21:16:18 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!proxad.net!news.tele.dk!news.tele.dk!small.news.tele.dk!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33052 I did a quick & dirty project based on the OpenCores USB 1.1 design and drove the D+ and D- pins straight from the FPGA. I wasn't concerned about strict compliance to the USB spec... I got the project to work fine, but I only tried it on a couple of computers. Different USB hosts might complain about the direct D+ D- interface. I did have to do some mods to the OpenCore USB design. As I looked though it I found some things I was not real happy with. There was no problem meeting timing with the Xilinx Spartan-2 chip I used. John Providenza "Ken Land" wrote in message news:... > Is it free? :) > > That is very interesting and that is what I went looking for. I imagined > the logic in the FPGA would wiggle D+ and D- appropriately. I understand > that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1 > might be doable. > > I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0? Of > course going to Stratix would negate any BOM savings. > > Ken > > "Antti Lukats" wrote in message > news:80a3aea5.0309152348.5ffd5049@posting.google.com... > > "Kenneth Land" wrote in message > news:... > > > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > > > > > I looked very closely at the 1.1 version and found it took only 6 pins > and > > > $1.75 transceiver chip. > > > > > > Ken > > > > there is a japanese design (VHDL, and Visual basic host example) > > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > > > antti ###### From: Uwe Bonnes Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Supersedes: Date: Tue, 16 Sep 2003 21:46:32 +0000 (UTC) Organization: Technische Universitaet Darmstadt Lines: 21 Sender: Uwe Bonnes Message-ID: References: <80a3aea5.0309152348.5ffd5049@posting.google.com> <349ef8f4.0309161316.62c75235@posting.google.com> NNTP-Posting-Host: hertz.ikp.physik.tu-darmstadt.de X-Trace: news.tu-darmstadt.de 1063748792 29038 130.83.24.91 (16 Sep 2003 21:46:32 GMT) X-Complaints-To: news@news.tu-darmstadt.de NNTP-Posting-Date: Tue, 16 Sep 2003 21:46:32 +0000 (UTC) User-Agent: tin/1.4.4-20000803 ("Vet for the Insane") (UNIX) (Linux/2.4.21-75-default (i686)) Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!feed.news.nacamar.de!news.tu-darmstadt.de!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33054 John Providenza wrote: : I did a quick & dirty project based on the OpenCores USB 1.1 : design and drove the D+ and D- pins straight from the FPGA. : I wasn't concerned about strict compliance to the USB spec... : I got the project to work fine, but I only tried it on a couple : of computers. Different USB hosts might complain about the : direct D+ D- interface. : I did have to do some mods to the OpenCore USB design. As I looked : though it I found some things I was not real happy with. There was : no problem meeting timing with the Xilinx Spartan-2 chip I used. Do you plan to contribute the mods back? It would be appreciated... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- ###### From: "Ken Land" Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Tue, 16 Sep 2003 16:57:37 -0500 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <80a3aea5.0309152348.5ffd5049@posting.google.com> <349ef8f4.0309161316.62c75235@posting.google.com> X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.3790.0 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.3790.0 X-Complaints-To: abuse@supernews.com Lines: 66 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!sjc70.webusenet.com!news.webusenet.com!sn-xit-02!sn-xit-06!sn-post-02!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33056 John, That's pretty cool. I might try it some day after I get some more experience under my belt. My problem was that I needed an fpga IP solution at an OTS price and reliability, but all I found were extremes. Either the core was "free" and not guaranteed fully compiant or the price was sky high. So I wound up sticking with my old reliable NetChip @ $8. Ken "John Providenza" wrote in message news:349ef8f4.0309161316.62c75235@posting.google.com... > I did a quick & dirty project based on the OpenCores USB 1.1 > design and drove the D+ and D- pins straight from the FPGA. > I wasn't concerned about strict compliance to the USB spec... > > I got the project to work fine, but I only tried it on a couple > of computers. Different USB hosts might complain about the > direct D+ D- interface. > > I did have to do some mods to the OpenCore USB design. As I looked > though it I found some things I was not real happy with. There was > no problem meeting timing with the Xilinx Spartan-2 chip I used. > > John Providenza > > > "Ken Land" wrote in message news:... > > Is it free? :) > > > > That is very interesting and that is what I went looking for. I imagined > > the logic in the FPGA would wiggle D+ and D- appropriately. I understand > > that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1 > > might be doable. > > > > I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0? Of > > course going to Stratix would negate any BOM savings. > > > > Ken > > > > "Antti Lukats" wrote in message > > news:80a3aea5.0309152348.5ffd5049@posting.google.com... > > > "Kenneth Land" wrote in message > > news:... > > > > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > > > > > > > I looked very closely at the 1.1 version and found it took only 6 pins > > and > > > > $1.75 transceiver chip. > > > > > > > > Ken > > > > > > there is a japanese design (VHDL, and Visual basic host example) > > > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > > > > > antti ###### From: Lasse Langwadt Christensen Newsgroups: comp.arch.fpga Subject: Re: USB transceiver for FPGA Date: Wed, 17 Sep 2003 00:44:27 +0200 Organization: Cybercity Lines: 43 Message-ID: <3F67924B.4090900@ieee.org> References: <80a3aea5.0309152348.5ffd5049@posting.google.com> <3F675846.1090007@ieee.org> <3F675C34.6EE3FCBF@yahoo.com> NNTP-Posting-Host: port354.ds1-abc.adsl.cybercity.dk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.cybercity.dk 1063752221 58505 217.157.139.107 (16 Sep 2003 22:43:41 GMT) X-Complaints-To: abuse@cybercity.dk NNTP-Posting-Date: Tue, 16 Sep 2003 22:43:41 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-us, en Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!news-peer.gradwell.net!newsfeed.kabelfoon.nl!195.129.110.21.MISMATCH!bnewsfeed00.bru.ops.eu.uu.net!bnewsinpeer00.bru.ops.eu.uu.net!emea.uu.net!news.cybercity.dk!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33058 rickman wrote: > Lasse Langwadt Christensen wrote: > >>Antti Lukats wrote: >> >>>"Kenneth Land" wrote in message news:... >>> >>> >>>>Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? >>>> >>>>I looked very closely at the 1.1 version and found it took only 6 pins and >>>>$1.75 transceiver chip. >>>> >>>>Ken >>> >>> >>>there is a japanese design (VHDL, and Visual basic host example) >>>that uses no tranceiver at all, ie USB DM,DP directly to FPGa >>> >>>antti >> >>I've thought about that, two pins programmed for 3V3-cmos should be good >>for tx and rx of SE0 but I never got around to checking if one of the >>differential standards on the FPGA would be within spec for USB? >> >>-Lasse > > > It has been awhile since I looked at the USB spec, but I seem to recall > that there is a non-standard state that is used to signal the rate or > some other aspect of the interface. I want to say this state is both > signals high or both low at the same time. Am I out to lunch on this? > > If there is a non-standard state on these pins, you would not be able to > use an LVDS driver. You would need two independant outputs. > single ended zero (SE0) is both both pins low and afair you have to both detect and generate that, my idea was to use two standard cmos IO's for that and wire a diffential set in parallel. -Lasse