Reply-To: "Martin Euredjian" <0_0_0_0_@pacbell.net> From: "Martin Euredjian" <0_0_0_0_@pacbell.net> Newsgroups: comp.arch.fpga Subject: Floorplanning, Routing, FPGA Editor Lines: 36 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: <654hb.12932$ln2.10690@newssvr25.news.prodigy.com> NNTP-Posting-Host: 64.170.224.250 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr25.news.prodigy.com 1065668034 ST000 64.170.224.250 (Wed, 08 Oct 2003 22:53:54 EDT) NNTP-Posting-Date: Wed, 08 Oct 2003 22:53:54 EDT Organization: SBC http://yahoo.sbc.com X-UserInfo1: SCSYASREVJTORT\XOBCD^VX@WB]^PCPDLXUNNHPIMASJETAANVW[AKWZE\]^XQWIGNE_[EBL@^_\^JOCQ^RSNVLGTFTKHTXHHP[NB\_C@\SD@EP_[KCXX__AGDDEKGFNB\ZOKLRNCY_CGG[RHT_UN@C_BSY\G__IJIX_PLSA[CCFAULEY\FL\VLGANTQQ]FN Date: Thu, 09 Oct 2003 02:53:54 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!elnk-atl-nf1!newsfeed.earthlink.net!newshosting.com!news-xfer2.atl.newshosting.com!diablo.voicenet.com!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr25.news.prodigy.com.POSTED!003b42bf!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:34162 In wanting to gain a greater understanding of routing options (particularly as related to making floorplanning decisions) I find myself studing devices in the FPGA Editor. One question that occured to me is: How accurate a representation of the actual device layout does this tool provide? Example: I'm looking at an XC2V100-4FG456. I see that all embedded multipliers have the I/O on the left side only. Obviously all PIP's are on that side as well. And there are four switch boxes that would seem to be the best place to connect in/out of the multipler. These switch boxes, in turn, would be the way to access the CLB's to the immediate left and right(through their own switch boxes). Double interconnect lines seem to be the best possible path. Are these accurate representations of the geometry? Accurate enough to decide, for example, that the path from a multiplier, through its switch box, via a double line, into the CLB to the left is slightly faster than using the same double line to go to the CLB on the right? Can any sort of assumptions be made in terms of ps per unit length from what is seen in FPGA Editor? What's the cost (delay wise) of going through a PIP FET? Is this the wrong approach to making floorplanning decisions? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" ###### Reply-To: "Martin Euredjian" <0_0_0_0_@pacbell.net> From: "Martin Euredjian" <0_0_0_0_@pacbell.net> Newsgroups: comp.arch.fpga References: <654hb.12932$ln2.10690@newssvr25.news.prodigy.com> Subject: Re: Floorplanning, Routing, FPGA Editor Lines: 15 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: NNTP-Posting-Host: 64.170.224.250 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr25.news.prodigy.com 1065671192 ST000 64.170.224.250 (Wed, 08 Oct 2003 23:46:32 EDT) NNTP-Posting-Date: Wed, 08 Oct 2003 23:46:32 EDT Organization: SBC http://yahoo.sbc.com X-UserInfo1: SCSYQNONPZVABQ\YCJKDM^P@VZ\LPCXLLBWLOOAFBATBTSUBYFWEAE[YJLYPIWKHTFCMZKVMB^[Z^DOBRVVMOSPFHNSYXVDIE@X\BUC@GTSX@DL^GKFFHQCCE\G[JJBMYDYIJCZM@AY]GNGPJD]YNNW\GSX^GSCKHA[]@CCB\[@LATPD\L@J\\PF]VR[QPJN Date: Thu, 09 Oct 2003 03:46:32 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!solnet.ch!solnet.ch!newsfeed.stueberl.de!opentransit.net!news-out.cwix.com!newsfeed.cwix.com!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr25.news.prodigy.com.POSTED!003b42bf!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:34163 > I'm looking at an XC2V100-4FG456. Sorry, XC2V1000 -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" ###### Message-ID: <3F84E56F.C2D3ED0C@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Floorplanning, Routing, FPGA Editor References: <654hb.12932$ln2.10690@newssvr25.news.prodigy.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 54 Date: Thu, 09 Oct 2003 00:34:55 -0400 NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: lakeread05 1065673496 68.15.41.165 (Thu, 09 Oct 2003 00:24:56 EDT) NNTP-Posting-Date: Thu, 09 Oct 2003 00:24:56 EDT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!peer01.cox.net!cox.net!p01!lakeread05.POSTED!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:34165 the FPGA editor is about as good as it gets for studying the device. Yes, it is faithful to the device for the connections and relative locations of the blocks. The router in FPGA editor will return timing for each node on a route as well. Martin Euredjian wrote: > In wanting to gain a greater understanding of routing options (particularly > as related to making floorplanning decisions) I find myself studing devices > in the FPGA Editor. One question that occured to me is: How accurate a > representation of the actual device layout does this tool provide? Example: > > I'm looking at an XC2V100-4FG456. I see that all embedded multipliers have > the I/O on the left side only. Obviously all PIP's are on that side as > well. And there are four switch boxes that would seem to be the best place > to connect in/out of the multipler. These switch boxes, in turn, would be > the way to access the CLB's to the immediate left and right(through their > own switch boxes). Double interconnect lines seem to be the best possible > path. > > Are these accurate representations of the geometry? Accurate enough to > decide, for example, that the path from a multiplier, through its switch > box, via a double line, into the CLB to the left is slightly faster than > using the same double line to go to the CLB on the right? > > Can any sort of assumptions be made in terms of ps per unit length from what > is seen in FPGA Editor? What's the cost (delay wise) of going through a PIP > FET? > > Is this the wrong approach to making floorplanning decisions? > > Thanks, > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: "Barry Brown" Newsgroups: comp.arch.fpga Subject: Re: Floorplanning, Routing, FPGA Editor Date: Thu, 9 Oct 2003 09:17:58 -0700 Organization: Agilent Technologies Lines: 53 Message-ID: <1065716279.409531@cswreg.cos.agilent.com> References: <654hb.12932$ln2.10690@newssvr25.news.prodigy.com> Reply-To: "Barry Brown" NNTP-Posting-Host: cswreg.cos.agilent.com X-Trace: cswtrans.cos.agilent.com 1065716282 16267 130.29.154.45 (9 Oct 2003 16:18:02 GMT) X-Complaints-To: usenet@cswtrans.cos.agilent.com NNTP-Posting-Date: Thu, 9 Oct 2003 16:18:02 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4927.1200 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4927.1200 Cache-Post-Path: cswreg.cos.agilent.com!unknown@sanc032620369.soco.agilent.com X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!news.isc.org!agilent.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:34191 Cannot answer your question, but thought I would bring to your attention Xilinx XAPP636, "Optimal Pipelining of I/O Ports of the Virtex-II Multiplier", in case you have not seen it. "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:654hb.12932$ln2.10690@newssvr25.news.prodigy.com... > In wanting to gain a greater understanding of routing options (particularly > as related to making floorplanning decisions) I find myself studing devices > in the FPGA Editor. One question that occured to me is: How accurate a > representation of the actual device layout does this tool provide? Example: > > I'm looking at an XC2V100-4FG456. I see that all embedded multipliers have > the I/O on the left side only. Obviously all PIP's are on that side as > well. And there are four switch boxes that would seem to be the best place > to connect in/out of the multipler. These switch boxes, in turn, would be > the way to access the CLB's to the immediate left and right(through their > own switch boxes). Double interconnect lines seem to be the best possible > path. > > Are these accurate representations of the geometry? Accurate enough to > decide, for example, that the path from a multiplier, through its switch > box, via a double line, into the CLB to the left is slightly faster than > using the same double line to go to the CLB on the right? > > Can any sort of assumptions be made in terms of ps per unit length from what > is seen in FPGA Editor? What's the cost (delay wise) of going through a PIP > FET? > > Is this the wrong approach to making floorplanning decisions? > > Thanks, > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > ###### Reply-To: "Martin Euredjian" <0_0_0_0_@pacbell.net> From: "Martin Euredjian" <0_0_0_0_@pacbell.net> Newsgroups: comp.arch.fpga References: <654hb.12932$ln2.10690@newssvr25.news.prodigy.com> <1065716279.409531@cswreg.cos.agilent.com> Subject: Re: Floorplanning, Routing, FPGA Editor Lines: 20 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: NNTP-Posting-Host: 64.170.224.250 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr25.news.prodigy.com 1065733348 ST000 64.170.224.250 (Thu, 09 Oct 2003 17:02:28 EDT) NNTP-Posting-Date: Thu, 09 Oct 2003 17:02:28 EDT Organization: SBC http://yahoo.sbc.com X-UserInfo1: S[OYR_CD[JWIRVH]^JKBOW@@YJ_ZTB\MV@BT]_MIJQR@EPIB_VUKAH_[MTX\IS[K[NGYJJFNOFZR_G[BUNTAOQLFE^TEHRPI]PZZRP_BMDSFQFL_]CBHXRWCMDCUZAZN@D_AKMNLEI]MWHCSXL^]NNC__CZFGSGHYYXWPFG@SCAVA]\FT\@B\RDGENSUQS^M Date: Thu, 09 Oct 2003 21:02:28 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!opentransit.net!news-out.cwix.com!newsfeed.cwix.com!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr25.news.prodigy.com.POSTED!003b42bf!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:34202 "Barry Brown" wrote in message news:1065716279.409531@cswreg.cos.agilent.com... > Cannot answer your question, but thought I would bring to your attention > Xilinx XAPP636, "Optimal Pipelining of I/O Ports of the Virtex-II > Multiplier", in case you have not seen it. Yes, I have, thanks. I show that I downloaded it back in December '02. Re-studied it a few days ago. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" ###### Message-ID: <3F85D2A9.A0AA5BA4@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Floorplanning, Routing, FPGA Editor References: <654hb.12932$ln2.10690@newssvr25.news.prodigy.com> <1065716279.409531@cswreg.cos.agilent.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 35 Date: Thu, 09 Oct 2003 17:27:05 -0400 NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: lakeread05 1065734223 68.15.41.165 (Thu, 09 Oct 2003 17:17:03 EDT) NNTP-Posting-Date: Thu, 09 Oct 2003 17:17:03 EDT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news-xfer2.atl.newshosting.com!63.218.45.10.MISMATCH!newshosting.com!news-xfer1.atl.newshosting.com!167.206.3.103.MISMATCH!news3.optonline.net!peer02.cox.net!cox.net!p01!lakeread05.POSTED!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:34205 FWIW, you need to put those registers in those spots around the multipliers in order to achieve the data sheet max performance. Martin Euredjian wrote: > "Barry Brown" wrote in message > news:1065716279.409531@cswreg.cos.agilent.com... > > Cannot answer your question, but thought I would bring to your attention > > Xilinx XAPP636, "Optimal Pipelining of I/O Ports of the Virtex-II > > Multiplier", in case you have not seen it. > > Yes, I have, thanks. I show that I downloaded it back in December '02. > Re-studied it a few days ago. > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Reply-To: "Martin Euredjian" <0_0_0_0_@pacbell.net> From: "Martin Euredjian" <0_0_0_0_@pacbell.net> Newsgroups: comp.arch.fpga References: <654hb.12932$ln2.10690@newssvr25.news.prodigy.com> <1065716279.409531@cswreg.cos.agilent.com> <3F85D2A9.A0AA5BA4@andraka.com> Subject: Re: Floorplanning, Routing, FPGA Editor Lines: 25 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: NNTP-Posting-Host: 64.170.224.250 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr25.news.prodigy.com 1065781734 ST000 64.170.224.250 (Fri, 10 Oct 2003 06:28:54 EDT) NNTP-Posting-Date: Fri, 10 Oct 2003 06:28:54 EDT Organization: SBC http://yahoo.sbc.com X-UserInfo1: SCSGW\KE\RUYRPLYNCOF_W\@PJ_^PBQLGPQRZ\YIJYWZUYICD^RAQBKZQTZTX\_I[^G_KGFNON[ZOE_AZNVO^\XGGNTCIRPIJH[@RQKBXLRZ@CD^HKANYVW@RLGEZEJN@\_WZJBNZYYKVIOR]T]MNMG_Z[YVWSCH_Q[GPC_A@CARQVXDSDA^M]@DRVUM@RBM Date: Fri, 10 Oct 2003 10:28:54 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr25.news.prodigy.com.POSTED!003b42bf!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:34236 "Ray Andraka" wrote: > FWIW, you need to put those registers in those spots around the multipliers in > order to achieve the data sheet max performance. Right. I experimented with the XAPP636 placement and studied the routing in and out of the multiplier with FPGA Editor. Makes sense. Can't see a faster way to lay it out. Funny enough, if you let the tools do a layout they will be exceedingly happy to put FF's so far away from multipliers that a monkey with a dart might be able to do better. This, I don't really understand. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" ###### Message-ID: <3F869BBE.27BA9903@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Floorplanning, Routing, FPGA Editor References: <654hb.12932$ln2.10690@newssvr25.news.prodigy.com> <1065716279.409531@cswreg.cos.agilent.com> <3F85D2A9.A0AA5BA4@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 39 Date: Fri, 10 Oct 2003 07:45:02 -0400 NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: lakeread05 1065785699 68.15.41.165 (Fri, 10 Oct 2003 07:34:59 EDT) NNTP-Posting-Date: Fri, 10 Oct 2003 07:34:59 EDT Path: redlance.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed00.sul.t-online.de!t-online.de!news-lei1.dfn.de!news-mue1.dfn.de!newsfeed.vmunix.org!peer02.cox.net!cox.net!p01!lakeread05.POSTED!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:34240 The tools do the same thing with pipeline registers added to BRAMs. They don't seem to do very well with placement of and around the multipliers and BRAMs. Martin Euredjian wrote: > "Ray Andraka" wrote: > > > FWIW, you need to put those registers in those spots around the > multipliers in > > order to achieve the data sheet max performance. > > Right. I experimented with the XAPP636 placement and studied the routing in > and out of the multiplier with FPGA Editor. Makes sense. Can't see a > faster way to lay it out. > > Funny enough, if you let the tools do a layout they will be exceedingly > happy to put FF's so far away from multipliers that a monkey with a dart > might be able to do better. This, I don't really understand. > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759