Reply-To: "SneakerNet" From: "SneakerNet" Newsgroups: comp.arch.fpga Subject: Reducing Clock Speed Lines: 62 Organization: Self X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Message-ID: Date: Fri, 26 Sep 2003 10:18:19 +1200 NNTP-Posting-Host: 202.37.96.43 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 1064528287 202.37.96.43 (Fri, 26 Sep 2003 10:18:07 NZST) NNTP-Posting-Date: Fri, 26 Sep 2003 10:18:07 NZST Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!enews.sgi.com!news.xtra.co.nz!53ab2750!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33439 Hi All I have a Nios Development Board that has a crystal osciallating at 50MHz. This is correct as I have seen the waveform and measured the frequency on an osilloscope. I am trying to implement USB Prototcol, for which I need a clock speed of 48MHz. How can I reduce the clock speed from 50 to 48. I have written a code that reduces a given speed to any speed, however it has its limitations. The code is presented below. This code is fully generic, thus user only has to give the current clock speed and the wanted clock speed. This code works fine as I am using this code to reduce the clock speed to 12.5MHz and 25Mhz. However it does not work for 30Mhz and 48Mhz as the result is a fraction and my code can't handle it. How can i fix this. How can I generate a clock of 48Mhz given that the crystal is 50Mhz. Pls Advice (Aplogoies in advance as the code does not have any comments, but it is very self-explanatory..) Regards ======================================================= LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; entity slow_clk is generic ( Clock_Speed : integer := 50000000; New_ClkSpeed: integer := 50000000 ); port ( clock : in std_logic; slow_clock : out std_logic ); end entity slow_clk; architecture behavioural of slow_clk is constant con_StopCnt : integer := ((Clock_Speed / New_ClkSpeed) / 2); signal main_cnt : integer range 1 to ((Clock_Speed / New_ClkSpeed) / 2); signal sig_TmpClk : std_logic; begin slow_clock <= sig_TmpClk; process is begin wait until rising_edge (clock); if main_cnt = con_StopCnt then sig_TmpClk <= not sig_TmpClk; main_cnt <= 1; end if; else main_cnt <= main_cnt + 1; end if; end process; end architecture behavioural; ======================================================= ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Reducing Clock Speed Date: Thu, 25 Sep 2003 15:58:31 -0700 Organization: Xilinx,Inc Lines: 68 Message-ID: <3F737316.F7015B6A@xilinx.com> References: NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: SneakerNet Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.media.kyoto-u.ac.jp!Spring.edu.tw!news.nctu.edu.tw!netnews.eranet.net!news.ttn.net!feeder.seed.net.tw!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33440 In the spirit of friendly competition let me tell you that Xilinx Virtex-II hs no problem with this. You just tell the DCM to multiply the 50 MHz by 24 and simultaneously divide it by 25 and, voila, you have a 48 MHz output. Peter Alfke, Xilinx Applications ===================== SneakerNet wrote: > > Hi All > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > This is correct as I have seen the waveform and measured the frequency on an > osilloscope. > > I am trying to implement USB Prototcol, for which I need a clock speed of > 48MHz. How can I reduce the clock speed from 50 to 48. I have written a code > that reduces a given speed to any speed, however it has its limitations. > The code is presented below. This code is fully generic, thus user only has > to give the current clock speed and the wanted clock speed. This code works > fine as I am using this code to reduce the clock speed to 12.5MHz and 25Mhz. > However it does not work for 30Mhz and 48Mhz as the result is a fraction and > my code can't handle it. > > How can i fix this. How can I generate a clock of 48Mhz given that the > crystal is 50Mhz. > Pls Advice (Aplogoies in advance as the code does not have any comments, but > it is very self-explanatory..) > > Regards > ======================================================= > LIBRARY IEEE; > USE IEEE.std_logic_1164.all; > USE IEEE.std_logic_arith.all; > > entity slow_clk is > generic ( > Clock_Speed : integer := 50000000; > New_ClkSpeed: integer := 50000000 > ); > port ( > clock : in std_logic; > slow_clock : out std_logic > ); > end entity slow_clk; > > architecture behavioural of slow_clk is > constant con_StopCnt : integer := ((Clock_Speed / New_ClkSpeed) / 2); > signal main_cnt : integer range 1 to ((Clock_Speed / New_ClkSpeed) / 2); > signal sig_TmpClk : std_logic; > > begin > slow_clock <= sig_TmpClk; > > process is > begin > wait until rising_edge (clock); > if main_cnt = con_StopCnt then > sig_TmpClk <= not sig_TmpClk; > main_cnt <= 1; > end if; > else > main_cnt <= main_cnt + 1; > end if; > > end process; > > end architecture behavioural; > ======================================================= ###### Reply-To: "John_H" From: "John_H" Newsgroups: comp.arch.fpga References: <3F737316.F7015B6A@xilinx.com> Subject: Re: Reducing Clock Speed Lines: 49 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Date: Fri, 26 Sep 2003 00:00:43 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1064534443 192.65.17.17 (Thu, 25 Sep 2003 18:00:43 MDT) NNTP-Posting-Date: Thu, 25 Sep 2003 18:00:43 MDT Organization: Xerox Officeprinting NewsReader Service Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!peer01.cox.net!peer02.cox.net!cox.net!news-feed01.roc.ny.frontiernet.net!nntp.frontiernet.net!news-west.eli.net!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33441 "Peter Alfke" wrote in message news:3F737316.F7015B6A@xilinx.com... > In the spirit of friendly competition let me tell you that Xilinx > Virtex-II hs no problem with this. You just tell the DCM to multiply the > 50 MHz by 24 and simultaneously divide it by 25 and, voila, you have a > 48 MHz output. > Peter Alfke, Xilinx Applications > ===================== And the Stratix or Cyclone Nios Development Board that was mentioned should be able to implement a similar frequency ratio with the Altera PLLs. Since, after all, that's the silicon he's using. > SneakerNet wrote: > > > > Hi All > > > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > > This is correct as I have seen the waveform and measured the frequency on an > > osilloscope. > > > > I am trying to implement USB Prototcol, for which I need a clock speed of > > 48MHz. How can I reduce the clock speed from 50 to 48. I have written a code > > that reduces a given speed to any speed, however it has its limitations. > > The code is presented below. This code is fully generic, thus user only has > > to give the current clock speed and the wanted clock speed. This code works > > fine as I am using this code to reduce the clock speed to 12.5MHz and 25Mhz. > > However it does not work for 30Mhz and 48Mhz as the result is a fraction and > > my code can't handle it. > > > > How can i fix this. How can I generate a clock of 48Mhz given that the > > crystal is 50Mhz. > > Pls Advice (Aplogoies in advance as the code does not have any comments, but > > it is very self-explanatory..) > > > > Regards ###### Reply-To: "SneakerNet" From: "SneakerNet" Newsgroups: comp.arch.fpga References: <3F737316.F7015B6A@xilinx.com> Subject: Re: Reducing Clock Speed Lines: 66 Organization: Self X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Message-ID: Date: Fri, 26 Sep 2003 12:56:10 +1200 NNTP-Posting-Host: 202.37.96.43 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 1064537760 202.37.96.43 (Fri, 26 Sep 2003 12:56:00 NZST) NNTP-Posting-Date: Fri, 26 Sep 2003 12:56:00 NZST Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!enews.sgi.com!news.xtra.co.nz!53ab2750!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33445 Ppl Ppl Rather than fighting over which product is better, why not someone help me with the solution.. "John_H" wrote in message news:LkLcb.12$Cr.9187@news-west.eli.net... > "Peter Alfke" wrote in message > news:3F737316.F7015B6A@xilinx.com... > > In the spirit of friendly competition let me tell you that Xilinx > > Virtex-II hs no problem with this. You just tell the DCM to multiply the > > 50 MHz by 24 and simultaneously divide it by 25 and, voila, you have a > > 48 MHz output. > > Peter Alfke, Xilinx Applications > > ===================== > > And the Stratix or Cyclone Nios Development Board that was mentioned should > be able to implement a similar frequency ratio with the Altera PLLs. Since, > after all, that's the silicon he's using. > > > SneakerNet wrote: > > > > > > Hi All > > > > > > I have a Nios Development Board that has a crystal osciallating at > 50MHz. > > > This is correct as I have seen the waveform and measured the frequency > on an > > > osilloscope. > > > > > > I am trying to implement USB Prototcol, for which I need a clock speed > of > > > 48MHz. How can I reduce the clock speed from 50 to 48. I have written a > code > > > that reduces a given speed to any speed, however it has its limitations. > > > The code is presented below. This code is fully generic, thus user only > has > > > to give the current clock speed and the wanted clock speed. This code > works > > > fine as I am using this code to reduce the clock speed to 12.5MHz and > 25Mhz. > > > However it does not work for 30Mhz and 48Mhz as the result is a fraction > and > > > my code can't handle it. > > > > > > How can i fix this. How can I generate a clock of 48Mhz given that the > > > crystal is 50Mhz. > > > Pls Advice (Aplogoies in advance as the code does not have any comments, > but > > > it is very self-explanatory..) > > > > > > Regards > > > > ###### From: johnhandwork@mail.com (John_H) Newsgroups: comp.arch.fpga Subject: Re: Reducing Clock Speed Date: 25 Sep 2003 18:24:57 -0700 Organization: http://groups.google.com/ Lines: 21 Message-ID: <6c803f5f.0309251724.4394c459@posting.google.com> References: NNTP-Posting-Host: 4.5.114.231 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1064539499 32073 127.0.0.1 (26 Sep 2003 01:24:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 26 Sep 2003 01:24:59 GMT Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33446 "SneakerNet" wrote in message news:... > Hi All > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > This is correct as I have seen the waveform and measured the frequency on an > osilloscope. > > I am trying to implement USB Prototcol, for which I need a clock speed of > 48MHz. How can I reduce the clock speed from 50 to 48. [ ahem ] "Use the PLL on your Nois development board's Altera chip." Please see the altera documentation on the altpll megafunction http://www.altera.com/literature/ug/ug_altpll.pdf (Better response?) ###### Reply-To: "SneakerNet" From: "SneakerNet" Newsgroups: comp.arch.fpga References: <6c803f5f.0309251724.4394c459@posting.google.com> Subject: Re: Reducing Clock Speed Lines: 33 Organization: Self X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Message-ID: Date: Fri, 26 Sep 2003 13:45:58 +1200 NNTP-Posting-Host: 202.37.96.43 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 1064540750 202.37.96.43 (Fri, 26 Sep 2003 13:45:50 NZST) NNTP-Posting-Date: Fri, 26 Sep 2003 13:45:50 NZST Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!enews.sgi.com!news.xtra.co.nz!53ab2750!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33447 "John_H" wrote in message news:6c803f5f.0309251724.4394c459@posting.google.com... > "SneakerNet" wrote in message news:... > > Hi All > > > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > > This is correct as I have seen the waveform and measured the frequency on an > > osilloscope. > > > > I am trying to implement USB Prototcol, for which I need a clock speed of > > 48MHz. How can I reduce the clock speed from 50 to 48. > > > > > [ ahem ] > > "Use the PLL on your Nois development board's Altera chip." > Please see the altera documentation on the altpll megafunction > > http://www.altera.com/literature/ug/ug_altpll.pdf > > (Better response?) A lot better. at least this answer was specific to my question ;o) Thanks ###### From: "Kenneth Land" Newsgroups: comp.arch.fpga Subject: Re: Reducing Clock Speed Date: Sat, 27 Sep 2003 07:52:33 -0500 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 X-Complaints-To: abuse@supernews.com Lines: 95 Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!sn-xit-03!sn-xit-01!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33554 "SneakerNet" wrote in message news:zQJcb.159026$JA5.3914623@news.xtra.co.nz... > Hi All > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > This is correct as I have seen the waveform and measured the frequency on an > osilloscope. > > I am trying to implement USB Prototcol, for which I need a clock speed of > 48MHz. How can I reduce the clock speed from 50 to 48. I have written a code > that reduces a given speed to any speed, however it has its limitations. > The code is presented below. This code is fully generic, thus user only has > to give the current clock speed and the wanted clock speed. This code works > fine as I am using this code to reduce the clock speed to 12.5MHz and 25Mhz. > However it does not work for 30Mhz and 48Mhz as the result is a fraction and > my code can't handle it. > > How can i fix this. How can I generate a clock of 48Mhz given that the > crystal is 50Mhz. > Pls Advice (Aplogoies in advance as the code does not have any comments, but > it is very self-explanatory..) > > Regards > ======================================================= > LIBRARY IEEE; > USE IEEE.std_logic_1164.all; > USE IEEE.std_logic_arith.all; > > entity slow_clk is > generic ( > Clock_Speed : integer := 50000000; > New_ClkSpeed: integer := 50000000 > ); > port ( > clock : in std_logic; > slow_clock : out std_logic > ); > end entity slow_clk; > > architecture behavioural of slow_clk is > constant con_StopCnt : integer := ((Clock_Speed / New_ClkSpeed) / 2); > signal main_cnt : integer range 1 to ((Clock_Speed / New_ClkSpeed) / 2); > signal sig_TmpClk : std_logic; > > begin > slow_clock <= sig_TmpClk; > > process is > begin > wait until rising_edge (clock); > if main_cnt = con_StopCnt then > sig_TmpClk <= not sig_TmpClk; > main_cnt <= 1; > end if; > else > main_cnt <= main_cnt + 1; > end if; > > end process; > > end architecture behavioural; > ======================================================= > > (I'm assuming you're using the Nios Dev Board) It's easy. Just type in 48 MHz as the speed in the SOPC builder for your Nios processor, then double click on the PLL that runs the Nios and goto clock C0 screen and enter 24 and 25 for the multiplier and divisor. (I did this to change my C0 to 68 MHz just to see if it would run that fast - no problem!) You should also be able to use clock C1 as well and then not have to alter the Nios's C0 clock. You could also probably alter the already hooked up E0 clock, but I don't know the details. You probably solved this all by now. If you use Nios in the title I will pick up on it quickly. I am working on a Nios project and would like to discuss as many aspects of this technology as possible. I'd like to hear about your USB progress. We're using an external chip on our custom board, but would be interested in a IP Core implementation. Ken ###### Reply-To: "SneakerNet" From: "SneakerNet" Newsgroups: comp.arch.fpga References: Subject: Re: Reducing Clock Speed Lines: 125 Organization: Self X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Message-ID: Date: Mon, 29 Sep 2003 09:13:46 +1200 NNTP-Posting-Host: 202.37.96.43 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 1064783626 202.37.96.43 (Mon, 29 Sep 2003 09:13:46 NZST) NNTP-Posting-Date: Mon, 29 Sep 2003 09:13:46 NZST Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!news.mel.connect.com.au!news.xtra.co.nz!53ab2750!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33581 "Kenneth Land" wrote in message news:vnb20los6n5u3c@news.supernews.com... > > "SneakerNet" wrote in message > news:zQJcb.159026$JA5.3914623@news.xtra.co.nz... > > Hi All > > > > I have a Nios Development Board that has a crystal osciallating at 50MHz. > > This is correct as I have seen the waveform and measured the frequency on > an > > osilloscope. > > > > I am trying to implement USB Prototcol, for which I need a clock speed of > > 48MHz. How can I reduce the clock speed from 50 to 48. I have written a > code > > that reduces a given speed to any speed, however it has its limitations. > > The code is presented below. This code is fully generic, thus user only > has > > to give the current clock speed and the wanted clock speed. This code > works > > fine as I am using this code to reduce the clock speed to 12.5MHz and > 25Mhz. > > However it does not work for 30Mhz and 48Mhz as the result is a fraction > and > > my code can't handle it. > > > > How can i fix this. How can I generate a clock of 48Mhz given that the > > crystal is 50Mhz. > > Pls Advice (Aplogoies in advance as the code does not have any comments, > but > > it is very self-explanatory..) > > > > Regards > > ======================================================= > > LIBRARY IEEE; > > USE IEEE.std_logic_1164.all; > > USE IEEE.std_logic_arith.all; > > > > entity slow_clk is > > generic ( > > Clock_Speed : integer := 50000000; > > New_ClkSpeed: integer := 50000000 > > ); > > port ( > > clock : in std_logic; > > slow_clock : out std_logic > > ); > > end entity slow_clk; > > > > architecture behavioural of slow_clk is > > constant con_StopCnt : integer := ((Clock_Speed / New_ClkSpeed) / 2); > > signal main_cnt : integer range 1 to ((Clock_Speed / New_ClkSpeed) / > 2); > > signal sig_TmpClk : std_logic; > > > > begin > > slow_clock <= sig_TmpClk; > > > > process is > > begin > > wait until rising_edge (clock); > > if main_cnt = con_StopCnt then > > sig_TmpClk <= not sig_TmpClk; > > main_cnt <= 1; > > end if; > > else > > main_cnt <= main_cnt + 1; > > end if; > > > > end process; > > > > end architecture behavioural; > > ======================================================= > > > > > (I'm assuming you're using the Nios Dev Board) > > It's easy. Just type in 48 MHz as the speed in the SOPC builder for your > Nios processor, then double click on the PLL that runs the Nios and goto > clock C0 screen and enter 24 and 25 for the multiplier and divisor. (I did > this to change my C0 to 68 MHz just to see if it would run that fast - no > problem!) > > You should also be able to use clock C1 as well and then not have to alter > the Nios's C0 clock. You could also probably alter the already hooked up E0 > clock, but I don't know the details. > > You probably solved this all by now. If you use Nios in the title I will > pick up on it quickly. I am working on a Nios project and would like to > discuss as many aspects of this technology as possible. > > I'd like to hear about your USB progress. We're using an external chip on > our custom board, but would be interested in a IP Core implementation. > > Ken > > Hi Ken Thanks for the response. I actually got the 48mhz to work but still bit confused on C1 and E0 clocks (in PLL) but no worries, i guess I'll try and figure that out soon. Regarding USB Implementation, I'm still trying my level best to get it to work. Basically I'm trying to get this core working that was mentioned on this newsgroup sometime back (Japanese version). It does not require any hardware, but i'm not able to make any progress on it. I have added my own PLL and connection the outputs to the leds (for debugging), and there are 2 leds that go on/off (USBEN and USBENLED), but becasue of no commenting i have very slight idea as to what's going on. Ken if you are interested in knowing what i have got with regards to USB comm u are welcome to send me a mail @ anangia@mailcity.com with USB/Nios as the subject. I'll be more than happy to send you my progress (though it's bit slow) Regares ###### From: "Paul Leventis" Newsgroups: comp.arch.fpga References: Subject: Re: Reducing Clock Speed Lines: 175 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: <3e6eb.161794$Lnr1.86972@news01.bloor.is.net.cable.rogers.com> Date: Tue, 30 Sep 2003 02:52:47 GMT NNTP-Posting-Host: 24.157.169.82 X-Complaints-To: abuse@rogers.com X-Trace: news01.bloor.is.net.cable.rogers.com 1064890367 24.157.169.82 (Mon, 29 Sep 2003 22:52:47 EDT) NNTP-Posting-Date: Mon, 29 Sep 2003 22:52:47 EDT Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!solnet.ch!solnet.ch!newsfeed.mountaincable.net!cyclone01.bloor.is.net.cable.rogers.com!news01.bloor.is.net.cable.rogers.com.POSTED!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33654 Hi SneakerNet (probably not the name your parents gave you ;-)), In addition to the aforementioned PLL megacore user's guide, I'd also suggest you take a peak at Chapter 6 of the Cyclone data book. You can find it here: http://www.altera.com/literature/lit-cyc.html This Chapter discusses the 1 or 2 PLLs present in Cyclone. They are identical to the Fast PLLs present in the Stratix family. Each PLL provides you with three clocks that are generated off of one reference clock. There are two internal clocks (C0 and C1) and one external clock (E) that is fed to pin for use on your board. The three outputs share a common clock pre-scale (N) and divider (M). Each output can be independently post-scaled (G0/G1/E counters), and can be phase shifted relative to a reference clock (usually a fed back clock from the core). The relationship of the clock frequencies is as follows: f(C0) = f(In) * M/N/G0 f(C1) = f(In) * M/N/G1 f(E) = f(In) * M/N/E But this is detail. I believe all you need to do is use the PLL MegaWizard and tell it the frequencies you'd like the PLL to generate and it will pick the appropriate M, N, G0, G1, and E values for you. Regards, Paul Leventis Altera Corp. "SneakerNet" wrote in message news:eaIdb.161813$JA5.3986469@news.xtra.co.nz... > "Kenneth Land" wrote in message > news:vnb20los6n5u3c@news.supernews.com... > > > > "SneakerNet" wrote in message > > news:zQJcb.159026$JA5.3914623@news.xtra.co.nz... > > > Hi All > > > > > > I have a Nios Development Board that has a crystal osciallating at > 50MHz. > > > This is correct as I have seen the waveform and measured the frequency > on > > an > > > osilloscope. > > > > > > I am trying to implement USB Prototcol, for which I need a clock speed > of > > > 48MHz. How can I reduce the clock speed from 50 to 48. I have written a > > code > > > that reduces a given speed to any speed, however it has its limitations. > > > The code is presented below. This code is fully generic, thus user only > > has > > > to give the current clock speed and the wanted clock speed. This code > > works > > > fine as I am using this code to reduce the clock speed to 12.5MHz and > > 25Mhz. > > > However it does not work for 30Mhz and 48Mhz as the result is a fraction > > and > > > my code can't handle it. > > > > > > How can i fix this. How can I generate a clock of 48Mhz given that the > > > crystal is 50Mhz. > > > Pls Advice (Aplogoies in advance as the code does not have any comments, > > but > > > it is very self-explanatory..) > > > > > > Regards > > > ======================================================= > > > LIBRARY IEEE; > > > USE IEEE.std_logic_1164.all; > > > USE IEEE.std_logic_arith.all; > > > > > > entity slow_clk is > > > generic ( > > > Clock_Speed : integer := 50000000; > > > New_ClkSpeed: integer := 50000000 > > > ); > > > port ( > > > clock : in std_logic; > > > slow_clock : out std_logic > > > ); > > > end entity slow_clk; > > > > > > architecture behavioural of slow_clk is > > > constant con_StopCnt : integer := ((Clock_Speed / New_ClkSpeed) / 2); > > > signal main_cnt : integer range 1 to ((Clock_Speed / New_ClkSpeed) / > > 2); > > > signal sig_TmpClk : std_logic; > > > > > > begin > > > slow_clock <= sig_TmpClk; > > > > > > process is > > > begin > > > wait until rising_edge (clock); > > > if main_cnt = con_StopCnt then > > > sig_TmpClk <= not sig_TmpClk; > > > main_cnt <= 1; > > > end if; > > > else > > > main_cnt <= main_cnt + 1; > > > end if; > > > > > > end process; > > > > > > end architecture behavioural; > > > ======================================================= > > > > > > > > (I'm assuming you're using the Nios Dev Board) > > > > It's easy. Just type in 48 MHz as the speed in the SOPC builder for your > > Nios processor, then double click on the PLL that runs the Nios and goto > > clock C0 screen and enter 24 and 25 for the multiplier and divisor. (I > did > > this to change my C0 to 68 MHz just to see if it would run that fast - no > > problem!) > > > > You should also be able to use clock C1 as well and then not have to alter > > the Nios's C0 clock. You could also probably alter the already hooked up > E0 > > clock, but I don't know the details. > > > > You probably solved this all by now. If you use Nios in the title I will > > pick up on it quickly. I am working on a Nios project and would like to > > discuss as many aspects of this technology as possible. > > > > I'd like to hear about your USB progress. We're using an external chip > on > > our custom board, but would be interested in a IP Core implementation. > > > > Ken > > > > > > Hi Ken > Thanks for the response. I actually got the 48mhz to work but still bit > confused on C1 and E0 clocks (in PLL) but no worries, i guess I'll try and > figure that out soon. > > Regarding USB Implementation, I'm still trying my level best to get it to > work. Basically I'm trying to get this core working that was mentioned on > this newsgroup sometime back (Japanese version). It does not require any > hardware, but i'm not able to make any progress on it. I have added my own > PLL and connection the outputs to the leds (for debugging), and there are 2 > leds that go on/off (USBEN and USBENLED), but becasue of no commenting i > have very slight idea as to what's going on. > > Ken if you are interested in knowing what i have got with regards to USB > comm u are welcome to send me a mail @ anangia@mailcity.com with USB/Nios as > the subject. I'll be more than happy to send you my progress (though it's > bit slow) > > Regares > > ###### Reply-To: "SneakerNet" From: "SneakerNet" Newsgroups: comp.arch.fpga References: <3e6eb.161794$Lnr1.86972@news01.bloor.is.net.cable.rogers.com> Subject: Re: Reducing Clock Speed Lines: 213 Organization: Self X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4927.1200 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4927.1200 Message-ID: Date: Tue, 30 Sep 2003 15:02:54 +1200 NNTP-Posting-Host: 202.37.96.43 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 1064890975 202.37.96.43 (Tue, 30 Sep 2003 15:02:55 NZST) NNTP-Posting-Date: Tue, 30 Sep 2003 15:02:55 NZST Path: redlance.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!canoe.uoregon.edu!arclight.uoregon.edu!enews.sgi.com!news.xtra.co.nz!53ab2750!not-for-mail Xref: redlance.franklin.ch comp.arch.fpga:33656 Hi Paul, Yeah haha on the name bit LOL Anyway yeah i got the pll to work though the megawizard . However thanks for the indepth explanation, as I like to understand whats going on (and was getting confused regarding C0, C1, and E0). I 'll take a peak at the link you have given me. Thanks Paul. "Paul Leventis" wrote in message news:3e6eb.161794$Lnr1.86972@news01.bloor.is.net.cable.rogers.com... > Hi SneakerNet (probably not the name your parents gave you ;-)), > > In addition to the aforementioned PLL megacore user's guide, I'd also > suggest you take a peak at Chapter 6 of the Cyclone data book. You can find > it here: > > http://www.altera.com/literature/lit-cyc.html > > This Chapter discusses the 1 or 2 PLLs present in Cyclone. They are > identical to the Fast PLLs present in the Stratix family. Each PLL provides > you with three clocks that are generated off of one reference clock. There > are two internal clocks (C0 and C1) and one external clock (E) that is fed > to pin for use on your board. The three outputs share a common clock > pre-scale (N) and divider (M). Each output can be independently post-scaled > (G0/G1/E counters), and can be phase shifted relative to a reference clock > (usually a fed back clock from the core). > > The relationship of the clock frequencies is as follows: > > f(C0) = f(In) * M/N/G0 > f(C1) = f(In) * M/N/G1 > f(E) = f(In) * M/N/E > > But this is detail. I believe all you need to do is use the PLL MegaWizard > and tell it the frequencies you'd like the PLL to generate and it will pick > the appropriate M, N, G0, G1, and E values for you. > > Regards, > > Paul Leventis > Altera Corp. > > "SneakerNet" wrote in message > news:eaIdb.161813$JA5.3986469@news.xtra.co.nz... > > "Kenneth Land" wrote in message > > news:vnb20los6n5u3c@news.supernews.com... > > > > > > "SneakerNet" wrote in message > > > news:zQJcb.159026$JA5.3914623@news.xtra.co.nz... > > > > Hi All > > > > > > > > I have a Nios Development Board that has a crystal osciallating at > > 50MHz. > > > > This is correct as I have seen the waveform and measured the frequency > > on > > > an > > > > osilloscope. > > > > > > > > I am trying to implement USB Prototcol, for which I need a clock speed > > of > > > > 48MHz. How can I reduce the clock speed from 50 to 48. I have written > a > > > code > > > > that reduces a given speed to any speed, however it has its > limitations. > > > > The code is presented below. This code is fully generic, thus user > only > > > has > > > > to give the current clock speed and the wanted clock speed. This code > > > works > > > > fine as I am using this code to reduce the clock speed to 12.5MHz and > > > 25Mhz. > > > > However it does not work for 30Mhz and 48Mhz as the result is a > fraction > > > and > > > > my code can't handle it. > > > > > > > > How can i fix this. How can I generate a clock of 48Mhz given that the > > > > crystal is 50Mhz. > > > > Pls Advice (Aplogoies in advance as the code does not have any > comments, > > > but > > > > it is very self-explanatory..) > > > > > > > > Regards > > > > ======================================================= > > > > LIBRARY IEEE; > > > > USE IEEE.std_logic_1164.all; > > > > USE IEEE.std_logic_arith.all; > > > > > > > > entity slow_clk is > > > > generic ( > > > > Clock_Speed : integer := 50000000; > > > > New_ClkSpeed: integer := 50000000 > > > > ); > > > > port ( > > > > clock : in std_logic; > > > > slow_clock : out std_logic > > > > ); > > > > end entity slow_clk; > > > > > > > > architecture behavioural of slow_clk is > > > > constant con_StopCnt : integer := ((Clock_Speed / New_ClkSpeed) / > 2); > > > > signal main_cnt : integer range 1 to ((Clock_Speed / New_ClkSpeed) > / > > > 2); > > > > signal sig_TmpClk : std_logic; > > > > > > > > begin > > > > slow_clock <= sig_TmpClk; > > > > > > > > process is > > > > begin > > > > wait until rising_edge (clock); > > > > if main_cnt = con_StopCnt then > > > > sig_TmpClk <= not sig_TmpClk; > > > > main_cnt <= 1; > > > > end if; > > > > else > > > > main_cnt <= main_cnt + 1; > > > > end if; > > > > > > > > end process; > > > > > > > > end architecture behavioural; > > > > ======================================================= > > > > > > > > > > > (I'm assuming you're using the Nios Dev Board) > > > > > > It's easy. Just type in 48 MHz as the speed in the SOPC builder for > your > > > Nios processor, then double click on the PLL that runs the Nios and goto > > > clock C0 screen and enter 24 and 25 for the multiplier and divisor. (I > > did > > > this to change my C0 to 68 MHz just to see if it would run that fast - > no > > > problem!) > > > > > > You should also be able to use clock C1 as well and then not have to > alter > > > the Nios's C0 clock. You could also probably alter the already hooked > up > > E0 > > > clock, but I don't know the details. > > > > > > You probably solved this all by now. If you use Nios in the title I > will > > > pick up on it quickly. I am working on a Nios project and would like to > > > discuss as many aspects of this technology as possible. > > > > > > I'd like to hear about your USB progress. We're using an external chip > > on > > > our custom board, but would be interested in a IP Core implementation. > > > > > > Ken > > > > > > > > > > Hi Ken > > Thanks for the response. I actually got the 48mhz to work but still bit > > confused on C1 and E0 clocks (in PLL) but no worries, i guess I'll try and > > figure that out soon. > > > > Regarding USB Implementation, I'm still trying my level best to get it to > > work. Basically I'm trying to get this core working that was mentioned on > > this newsgroup sometime back (Japanese version). It does not require any > > hardware, but i'm not able to make any progress on it. I have added my own > > PLL and connection the outputs to the leds (for debugging), and there are > 2 > > leds that go on/off (USBEN and USBENLED), but becasue of no commenting i > > have very slight idea as to what's going on. > > > > Ken if you are interested in knowing what i have got with regards to USB > > comm u are welcome to send me a mail @ anangia@mailcity.com with USB/Nios > as > > the subject. I'll be more than happy to send you my progress (though it's > > bit slow) > > > > Regares > > > > > >