From: Sebastian_Lange@gmx.de (Sebastian Lange) Newsgroups: comp.arch.fpga Subject: FPGA implementation in (V)HDL Date: 22 Sep 2003 06:26:07 -0700 Organization: http://groups.google.com/ Lines: 12 Message-ID: <6877ff81.0309220526.2f5b7d3e@posting.google.com> NNTP-Posting-Host: 139.18.2.187 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1064237169 29066 127.0.0.1 (22 Sep 2003 13:26:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 22 Sep 2003 13:26:09 GMT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33195 This post may seem a bit awkward, but has anyone ever come across a VHDL or Verilog implementation of an FPGA? It would be very instructional to have a look at it. IMHO, it should be at any rate possible to implement a small FPGA as a bit file sitting on top of another FPGA. Our group is currently working on some ideas for minimizing the reconfiguration data in dynamically reconfigurable FPGA applications. It would be very kind if anyone could point me to any resources... Thank you so much in advance... Sebastian ###### From: Philip Freidin Newsgroups: comp.arch.fpga Subject: Re: FPGA implementation in (V)HDL Organization: Fliptronics Reply-To: philip@fliptronics.com Message-ID: References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 NNTP-Posting-Host: 216.103.85.188 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr27.news.prodigy.com 1064238045 ST000 216.103.85.188 (Mon, 22 Sep 2003 09:40:45 EDT) NNTP-Posting-Date: Mon, 22 Sep 2003 09:40:45 EDT X-UserInfo1: Q[R_@S^EYJTSC\@[ARHDM^P@VZ\LPCXLLBWLOOAFJYWZUYICD^RAQBKZQTZTX\_I[^G_KGFNON[ZOE_AZNVO^\XGGNTCIRPIJH[@RQKBXLRZ@CD^HKANYVW@RLGEZEJN@\_WZJBNZYYKVIOR]T]MNMG_Z[YVWSCH_Q[GPC_A@CARQVXDSDA^M]@DRVUM@RBM Date: Mon, 22 Sep 2003 13:40:45 GMT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!newsfeed.ision.net!ision!npeer.de.kpn-eurorings.net!in.100proofnews.com!in.100proofnews.com!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr27.news.prodigy.com.POSTED!7ae961dc!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33192 On 22 Sep 2003 06:26:07 -0700, Sebastian_Lange@gmx.de (Sebastian Lange) wrote: >This post may seem a bit awkward, but has anyone ever come across a >VHDL or >Verilog implementation of an FPGA? It would be very instructional to >have a >look at it. IMHO, it should be at any rate possible to implement a >small FPGA as a bit file sitting on top of another FPGA. Our group is >currently working on some ideas for minimizing the reconfiguration >data in dynamically reconfigurable FPGA applications. >It would be very kind if anyone could point me to any resources... >Thank you so much in advance... > >Sebastian Eric Crabill's course at SJSU covers this as Lab 5 http://www.engr.sjsu.edu/crabill/ Philip Freidin Fliptronics ###### From: "Andras Tantos" Newsgroups: comp.arch.fpga References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> Subject: Re: FPGA implementation in (V)HDL Date: Mon, 22 Sep 2003 10:44:14 -0700 Lines: 34 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 NNTP-Posting-Host: andrast1.redmond.corp.microsoft.com X-Original-NNTP-Posting-Host: andrast1.redmond.corp.microsoft.com Message-ID: <3f6f34ee$1@news.microsoft.com> X-Trace: news.microsoft.com 1064252654 157.59.150.166 (22 Sep 2003 10:44:14 -0700) Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!in.100proofnews.com!in.100proofnews.com!pd2nf1so.cg.shawcable.net!residential.shaw.ca!sea-feed.news.verio.net!news.microsoft.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33179 Also take a look at: http://www.opencores.org/projects/fpga/ Regrads, Andras Tantos "Philip Freidin" wrote in message news:ksutmv8keob45q149tk04kb040lu6l8bl5@4ax.com... > On 22 Sep 2003 06:26:07 -0700, Sebastian_Lange@gmx.de (Sebastian Lange) wrote: > >This post may seem a bit awkward, but has anyone ever come across a > >VHDL or > >Verilog implementation of an FPGA? It would be very instructional to > >have a > >look at it. IMHO, it should be at any rate possible to implement a > >small FPGA as a bit file sitting on top of another FPGA. Our group is > >currently working on some ideas for minimizing the reconfiguration > >data in dynamically reconfigurable FPGA applications. > >It would be very kind if anyone could point me to any resources... > >Thank you so much in advance... > > > >Sebastian > > Eric Crabill's course at SJSU covers this as Lab 5 > > http://www.engr.sjsu.edu/crabill/ > > > > > > Philip Freidin > Fliptronics ###### From: jetmarc@hotmail.com (jetmarc) Newsgroups: comp.arch.fpga Subject: Re: FPGA implementation in (V)HDL Date: 22 Sep 2003 12:15:59 -0700 Organization: http://groups.google.com/ Lines: 7 Message-ID: References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> NNTP-Posting-Host: 80.58.13.42 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1064258160 22603 127.0.0.1 (22 Sep 2003 19:16:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 22 Sep 2003 19:16:00 GMT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!news.tele.dk!news.tele.dk!small.news.tele.dk!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33196 > a VHDL or Verilog implementation of an FPGA? I know that somebody started one about 2 years ago, but I can't find the bookmark anymore. The main problem was that the custom FPGA needs a custom toolchain, and that makes it a really huge project. Marc ###### From: Brian Drummond Newsgroups: comp.arch.fpga Subject: Re: FPGA implementation in (V)HDL Date: Tue, 23 Sep 2003 16:19:07 +0100 Lines: 17 Message-ID: References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> NNTP-Posting-Host: shapes.demon.co.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.demon.co.uk 1064330432 18362 158.152.228.158 (23 Sep 2003 15:20:32 GMT) X-Complaints-To: abuse@demon.net NNTP-Posting-Date: Tue, 23 Sep 2003 15:20:32 +0000 (UTC) X-Newsreader: Forte Agent 1.7/32.534 Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!kibo.news.demon.net!news.demon.co.uk!demon!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33245 On 22 Sep 2003 12:15:59 -0700, jetmarc@hotmail.com (jetmarc) wrote: >> a VHDL or Verilog implementation of an FPGA? > >I know that somebody started one about 2 years ago, but I can't find >the bookmark anymore. The main problem was that the custom FPGA >needs a custom toolchain, and that makes it a really huge project. > >Marc The logical thing to do would be to combine this with the previous thread, implement a XC6216 on top of a Virtex-II, use the XC6200 tools that still exist, and satisfy those folks who can no longer get the XC6200 for research purposes... - Brian ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: FPGA implementation in (V)HDL Date: 24 Sep 2003 00:22:54 +0200 Organization: My own Private Self Lines: 19 Message-ID: <6uu1732lhd.fsf@chonsp.franklin.ch> References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1064355774 558 10.0.3.2 (23 Sep 2003 22:22:54 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 23 Sep 2003 22:22:54 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:33251 jetmarc@hotmail.com (jetmarc) writes: > > a VHDL or Verilog implementation of an FPGA? > > I know that somebody started one about 2 years ago, but I can't find > the bookmark anymore. The main problem was that the custom FPGA > needs a custom toolchain, and that makes it a really huge project. That would have been the: MPGA - Meta Programmable Gate Array http://ce.et.tudelft.nl/~reinoud/mpga/README.html -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: FPGA implementation in (V)HDL Date: Tue, 23 Sep 2003 17:27:38 -0700 Organization: Xilinx,Inc Lines: 2 Message-ID: <3F70E4F9.2A7A642D@xilinx.com> References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> <6uu1732lhd.fsf@chonsp.franklin.ch> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!logbridge.uoregon.edu!nntp-server.caltech.edu!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33254 No comment... Peter Alfke ###### From: "Vinh Pham" Newsgroups: comp.arch.fpga References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> Subject: Re: FPGA implementation in (V)HDL Lines: 14 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Date: Wed, 24 Sep 2003 01:12:18 GMT NNTP-Posting-Host: 66.8.207.16 X-Complaints-To: abuse@rr.com X-Trace: twister.socal.rr.com 1064365938 66.8.207.16 (Tue, 23 Sep 2003 18:12:18 PDT) NNTP-Posting-Date: Tue, 23 Sep 2003 18:12:18 PDT Organization: RoadRunner - West Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-out1.nntp.be!propagator2-sterling!news-in-sterling.nuthinbutnews.com!newshosting.com!news-xfer1.atl.newshosting.com!news-out.superfeed.net!propagator2-maxim!news-in.superfeed.net!news-west.rr.com!news.rr.com!cyclone.kc.rr.com!cyclone2.kc.rr.com!news2.kc.rr.com!twister.socal.rr.com.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33269 > The logical thing to do would be to combine this with the previous > thread, implement a XC6216 on top of a Virtex-II, use the XC6200 tools > that still exist, and satisfy those folks who can no longer get the > XC6200 for research purposes... Heh, someone should implement an Altera architecture on a Virtex :_D (not poking fun at the idea of a meta FPGA, of course) Regards, Vinh Pham ###### From: John Williams Newsgroups: comp.arch.fpga Subject: Re: FPGA implementation in (V)HDL Date: Wed, 24 Sep 2003 11:13:26 +1000 Organization: ITEE, University of Queensland Lines: 22 Message-ID: References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> Reply-To: jwilliams@itee.uq.edu.au NNTP-Posting-Host: g435-9029.itee.uq.edu.au Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: bunyip.cc.uq.edu.au 1064365101 3610 130.102.66.250 (24 Sep 2003 00:58:21 GMT) X-Complaints-To: news@uq.edu.au NNTP-Posting-Date: 24 Sep 2003 00:58:21 GMT User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4) Gecko/20030529 X-Accept-Language: en-us, en In-Reply-To: Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!news.maxwell.syr.edu!news1.optus.net.au!optus!news.mel.connect.com.au!news.syd.connect.com.au!news.bri.connect.com.au!bunyip.cc.uq.edu.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33261 Brian Drummond wrote: > On 22 Sep 2003 12:15:59 -0700, jetmarc@hotmail.com (jetmarc) wrote: > > >>>a VHDL or Verilog implementation of an FPGA? >> >>I know that somebody started one about 2 years ago, but I can't find >>the bookmark anymore. The main problem was that the custom FPGA >>needs a custom toolchain, and that makes it a really huge project. >> >>Marc > > > The logical thing to do would be to combine this with the previous > thread, implement a XC6216 on top of a Virtex-II, use the XC6200 tools > that still exist, and satisfy those folks who can no longer get the > XC6200 for research purposes... That's a great idea... John ###### From: antti@case2000.com (Antti Lukats) Newsgroups: comp.arch.fpga Subject: Re: FPGA implementation in (V)HDL Date: 23 Sep 2003 23:18:17 -0700 Organization: http://groups.google.com/ Lines: 38 Message-ID: <80a3aea5.0309232218.6f2e63b7@posting.google.com> References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> <6uu1732lhd.fsf@chonsp.franklin.ch> <3F70E4F9.2A7A642D@xilinx.com> NNTP-Posting-Host: 80.142.103.221 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1064384298 7112 127.0.0.1 (24 Sep 2003 06:18:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 24 Sep 2003 06:18:18 GMT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33279 Peter Alfke wrote in message news:<3F70E4F9.2A7A642D@xilinx.com>... > No comment... > Peter Alfke Hi Peter, this is something, I mean if someone (like you) doesnt hold it back to say 'no comments' it means something, need to figure out what :) FYI MPGA Meta Gate array pure Xilinx SRL16 oriented design, 1 MPGA cell = 1 Virtex slice bitstream is prepared as ASCII chart that can be directly downloaded! yes you have ASCII chart you edit it and download to FPGA KRPAN (OC embedded FPGA) this is very similar to Algotronix CAL1024 with little bit enhanced interconnect and cell architecture 1 KRPAN cell is approx 26 Virtex slices KRPAN comes with verilog to bitstream tool that does map place and route (simulated annealing), it also has some Floorplanner, software is written 100% in Java and does work. both the cell sized indicated for fpga-fpga include bitstream programmin interface. antti@openchip.org I wonder if your comment is still no comment? guess it is. me smiling here :) ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: FPGA implementation in (V)HDL Date: 25 Sep 2003 00:16:28 +0200 Organization: My own Private Self Lines: 120 Message-ID: <6ur825rfwj.fsf@chonsp.franklin.ch> References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> <6uu1732lhd.fsf@chonsp.franklin.ch> <3F70E4F9.2A7A642D@xilinx.com> <80a3aea5.0309232218.6f2e63b7@posting.google.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1064441788 887 10.0.3.2 (24 Sep 2003 22:16:28 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 24 Sep 2003 22:16:28 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:33286 antti@case2000.com (Antti Lukats) writes: > FYI > > MPGA Meta Gate array > > pure Xilinx SRL16 oriented design, > > 1 MPGA cell = 1 Virtex slice Web page of openchip.org is still empty, so I can only speculate what you are doing. Hmm, only 2 LUTs per cell can only be roughly such an design: N-E-W-S inputs (no far ones) into one 4LUT, function there, out direct and out via FF both to an 2nd 4LUT (what with its other 2 inputs?) and output of that identical in all 4 directions (no space for Nout Eout Sout Wout muxes, hmm, how do signals cross each other?). That would be an minimal SoG-FPGA in LUT+PIP FPGA implementation. SoG = Sea of Gates, FPGA with no specific LUT logic vs PIP routing split, like Algotronix CAL1024 or Xilinx XC6200 or Atmel AT6000. LUT+PIP = the oposite, few luts (10% of chip) and 90% PIP based routing in between, like XC2000, XC3000, XC3100, XV4000, XC5200, Virtex, ... > bitstream is prepared as ASCII chart that can be directly downloaded! > yes you have ASCII chart you edit it and download to FPGA Split up into the LUTs, with all the rest of the host-FPGA unchanged? > KRPAN (OC embedded FPGA) > > this is very similar to Algotronix CAL1024 with little bit enhanced > 1 KRPAN cell is approx 26 Virtex slices That is what most FPGA-in-FPGA designs seem to be like. Emulate CAL1024 or Cal2/XC6200 style designs. In particular an XC6200 bit compatible design will waste a lot of space (them 3 8-Muxes (each 4 LUTs, 2 F5, 1 F6) per cell are expensive, add then 4 4-Muxes for output (each 2 LUTs with F5), add then a few LUTs for the function unit, and then somehow enough FFs for them 24 config bits per cell). So 26 slices is large but believeable. An XC6200 feature-alike (translate XC6200 bitstream to lut values and write them per SLR16) would be smaller (only 2 LUTs per 8-Mux, as selection bits come from the LUTs content) and allow additional features (8-Mux -> 2 LUTs and F5-OR, so offer 16+16 functions instead of just 8 Mux states). Making an optimize for implement-in-Virtex SoG would be massively more space saving, but not compatible (or even translatable) with the XC6200 toolschains. But one can make ones own tools, possibly derived from the many outside-Xilinx ones that are available from universities. Problem is that I dislike SoG style FPGAs. Their "no routing" architecture, which is sold as advantage by the proponents (it is more "elegant", because less details), ends up in real designs being "emulate routing using logic or out muxes", which uses more chip space (wasted cells just for routing) and is slower (even in full-custom chips it is 1 NAND-NAND Mux per cell, instead of one PIP transistors gate per CLB. And the 24bit/cell of an XC6200 compared with the 864bit/CLB of Virtex gives us 36cells at cost of one CLB (assuming SRAM costs dominate). So 9cells at cost of LUT. But an 6x6 grid of cells gives max 6 lines of data traversing it and costs 6 NAND-NAND hops, and so is way inferior to an CLB with 24 lines traversing it and one single PIP stage of delay. Also SoG loses the "1 bit per LUT row" data path design, making hardwired efficient carry chains impossible. So the result is massively slower arithmetic (3 Muxes for bit generating cell (each NAND-NAND) + 2 transfer Muxes per bit, as opposed to the 1 NAND-NAND 2bit lookahead per 2bits, if I reconstruct the Virtex chips layout properly). So that is (3+2*1)*2=10 vs (1/2)*2=1 in propagation delay. > I wonder if your comment is still no comment? > guess it is. > me smiling here :) Perhaps he knows that SoG has no future. XC6200 did not die because someone at Xilinx disliked its name. It was an commercial faillure. IMHO because it is/was an SoG. An design which ist technologically inferior. And can not be made better. Only academia liked it, because its one advantage (bitstream documented), inherited from CAL1032, outweighted performance for their types of jobs (research and test students). But anyone who wants performance, needs an LUT+PIP design, with its space/speed optimal routing by PIPs and 1-LUT-per-bit data paths with fast dedicated carry. At least DSP and soft-CPU people need this, badly. That is IMHO why all the large vendors (X, A, Lucent/Lattice) are all LUT+PIP based. And that is why people like me and Casselmann keep on hammering on Xilinx to open up Virtex or V2 documentation. Only alternative is to either reverse engineer Xilinx, make own FPGAs with documanted bitstream, at least on base of an ASIC to get speed (no FPGA-in-FPGA double speed/density loss). Both cost a lot of time. Of course any successfull OpenFPGA (outside of academia) is therefore going to also have an LUT+PIP structure. All projects I have seen so far do not have it, because they are SoG. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### From: "Paul Leventis" Newsgroups: comp.arch.fpga References: <6877ff81.0309220526.2f5b7d3e@posting.google.com> Subject: Re: FPGA implementation in (V)HDL Lines: 31 X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Date: Tue, 30 Sep 2003 03:57:14 GMT NNTP-Posting-Host: 24.157.169.82 X-Complaints-To: abuse@rogers.com X-Trace: news01.bloor.is.net.cable.rogers.com 1064894234 24.157.169.82 (Mon, 29 Sep 2003 23:57:14 EDT) NNTP-Posting-Date: Mon, 29 Sep 2003 23:57:14 EDT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.tele.dk!news.tele.dk!small.news.tele.dk!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.cwix.com!cyclone01.bloor.is.net.cable.rogers.com!news01.bloor.is.net.cable.rogers.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33559 Hi Sebastian, Prof. Steve Wilton's group at the University of British Columbia is doing work on a Programmable Sytem-on-a-Chip. They generate HDL for an arbitrary sized FPGA core, and implement it in Standard Cells on a ASIC. The tool also spits out a compiler for the core (p & r + bitstream generator). They published a paper at CICC on it, and have some other publications. Take a peak at http://www.ece.ubc.ca/~stevew/soc.html. Regards, Paul Leventis Altera Corp. "Sebastian Lange" wrote in message news:6877ff81.0309220526.2f5b7d3e@posting.google.com... > This post may seem a bit awkward, but has anyone ever come across a > VHDL or > Verilog implementation of an FPGA? It would be very instructional to > have a > look at it. IMHO, it should be at any rate possible to implement a > small FPGA as a bit file sitting on top of another FPGA. Our group is > currently working on some ideas for minimizing the reconfiguration > data in dynamically reconfigurable FPGA applications. > It would be very kind if anyone could point me to any resources... > Thank you so much in advance... > > Sebastian