From: "Roberto Gallo" Newsgroups: comp.arch.fpga Subject: Xilinx Date: Wed, 17 Sep 2003 10:00:28 -0300 Organization: Institute of Computing, University of Campinas,SP, Brazil Lines: 12 Message-ID: NNTP-Posting-Host: crianca.lsc.ic.unicamp.br X-Trace: aracaju.ic.unicamp.br 1063803621 6272 143.106.24.218 (17 Sep 2003 13:00:21 GMT) X-Complaints-To: usenet@ic.unicamp.br NNTP-Posting-Date: Wed, 17 Sep 2003 13:00:21 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2720.3000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2727.1300 Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!newsfeed.berkeley.edu!ucberkeley!dcc.unicamp.br!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32992 Hello everyone, What is the cheapest line of volatile Xilinx´s FPGAs? What is the relation between Altera´s LEs and Xilinx´s Slices? I need the cheapest Xilinx FPGA (or from any other manufacturer) that has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you suggest? Thank you very much, Roberto. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Wed, 17 Sep 2003 09:37:00 -0400 Organization: Arius, Inc Lines: 33 Message-ID: <3F68637C.CD3D9FCA@yahoo.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: UmFuZG9tSVYvfY761L7lV7apjx76JlqOIN7J6c2zSDx4iyDTkqV7+kGS/hWausYY X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 17 Sep 2003 13:37:21 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32974 Roberto Gallo wrote: > > Hello everyone, > > What is the cheapest line of volatile Xilinx´s FPGAs? > What is the relation between Altera´s LEs and Xilinx´s Slices? > I need the cheapest Xilinx FPGA (or from any other manufacturer) that > has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you > suggest? > > Thank you very much, > Roberto. If you won't be in production until next year, the cheapest solution will likely be the Spartan 3. If you need parts now, it would likely be the Spartan IIE. Both families have about 1500 logic cells in the smallest part, regardless of what the data sheets says. Xilinx likes to pad the number since they feel they have "uber-cells" which count as more than 1 each. But then again, they don't define the term "logic cell", so I guess they can count them any way they want. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Wed, 17 Sep 2003 08:49:35 -0700 Organization: Xilinx,Inc Lines: 22 Message-ID: <3F688290.86C3AAC4@xilinx.com> References: NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Roberto Gallo Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!zen.net.uk!newsfeed.media.kyoto-u.ac.jp!Spring.edu.tw!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32976 What Altera calls an LE, Xilinx calls a Logic Cell (yes, I know there is a slight marketing inflation), and two Altera LEs correspond to one Xilinx slice. So you are looking for the XC2S30 (the next-to-smallest member) with the equivalent of 864 LEs ( or the 2S50 with 1536 LE equivalents). Your best bet for low price is the Spartan3 XC3S50 with 1536 LE equivalents. This chip is available in an early version without BlockRAM. Peter Alfke, Xilinx Applications ========================= Roberto Gallo wrote: > > Hello everyone, > > What is the cheapest line of volatile Xilinx´s FPGAs? > What is the relation between Altera´s LEs and Xilinx´s Slices? > I need the cheapest Xilinx FPGA (or from any other manufacturer) that > has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you > suggest? > > Thank you very much, > Roberto. ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Wed, 17 Sep 2003 09:00:26 -0700 Organization: Xilinx,Inc Lines: 17 Message-ID: <3F68851A.74DE66EC@xilinx.com> References: <3F68637C.CD3D9FCA@yahoo.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: rickman Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.media.kyoto-u.ac.jp!Spring.edu.tw!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32979 rickman wrote: > Xilinx likes to > pad the number since they feel they have "uber-cells" which count as > more than 1 each. But then again, they don't define the term "logic > cell", so I guess they can count them any way they want. Not really, the "padding" is exactly 12.5%, so it has been defined and is deterministic. Marketing wants to get credit for the additional multiplexers that the competition does not have. If you are a purist, just count slices and devide by 2, or multiply CLBs by 4 (Virtex and Spartan2) or by 8 (Virtex2 and Spartan3). That gets you the number of LUTs+flip-flops. Peter Alfke > ###### From: Larry Doolittle Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Wed, 17 Sep 2003 17:46:03 +0000 (UTC) Organization: LBNL News Server Lines: 13 Message-ID: References: <3F688290.86C3AAC4@xilinx.com> NNTP-Posting-Host: recycle.lbl.gov X-Trace: overload.lbl.gov 1063820763 23733 131.243.169.124 (17 Sep 2003 17:46:03 GMT) X-Complaints-To: "newsmaster@lbl.gov" NNTP-Posting-Date: Wed, 17 Sep 2003 17:46:03 +0000 (UTC) User-Agent: slrn/0.9.7.4 (Linux) Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!newsfeed.berkeley.edu!ucberkeley!ihnp4.ucsd.edu!dog.ee.lbl.gov!news.lbl.gov!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33044 In article <3F688290.86C3AAC4@xilinx.com>, Peter Alfke wrote: > So you are looking for the XC2S30 (the next-to-smallest member) with the > equivalent of 864 LEs ( or the 2S50 with 1536 LE equivalents). > Your best bet for low price is the Spartan3 XC3S50 with 1536 LE > equivalents. This chip is available in an early version without BlockRAM. The XC2S50E-6PQ208C is in-stock at Digi-Key for $14.55 quantity 1. The cheapest theoretical price I have seen for the XC3S50J is $23.85 (for a -4TQ144CES), and I have yet to see a distributor claim stock. I know which one I would choose. - Larry ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Wed, 17 Sep 2003 11:03:43 -0700 Organization: Xilinx,Inc Lines: 16 Message-ID: <3F68A1FE.521AB676@xilinx.com> References: <3F688290.86C3AAC4@xilinx.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Larry Doolittle Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!in.100proofnews.com!in.100proofnews.com!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33037 Well, newness has its price. But a year from now, the XC3S50 will be the low-cost champion, especially in high volume... But there is nothing wrong with using Spartan2, except for the smaller BRAM and the simpler clock manager, compared to the upcoming production Spartan3-50.... Peter Alfke =========================== Larry Doolittle wrote: > > The XC2S50E-6PQ208C is in-stock at Digi-Key for $14.55 quantity 1. > The cheapest theoretical price I have seen for the XC3S50J is $23.85 > (for a -4TQ144CES), and I have yet to see a distributor claim stock. > > I know which one I would choose. > > - Larry ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Wed, 17 Sep 2003 17:46:27 -0700 Organization: Xilinx,Inc Lines: 13 Message-ID: <3F690063.C63D1FEA@xilinx.com> References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Ray Andraka Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news2.euro.net!in.100proofnews.com!in.100proofnews.com!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33055 So, the 12.5% stand for "virtually useless" multiplexers, useful RAM capability, and the super-useful SRL16 shift-register capability that enhances Ray's formidable talents even more. :-) Peter Alfke ================================== Ray Andraka wrote: > > True, but those muxes are virtually useless for data path because the bit > pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or > flip-flops instead. > > P ###### Message-ID: <3F690C77.2CC92235@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Xilinx References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F690063.C63D1FEA@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 41 Date: Wed, 17 Sep 2003 21:37:59 -0400 NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: lakeread05 1063848533 68.15.41.165 (Wed, 17 Sep 2003 21:28:53 EDT) NNTP-Posting-Date: Wed, 17 Sep 2003 21:28:53 EDT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!peer02.cox.net!cox.net!p01!lakeread05.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33056 Touche' Yes, I agree that the other stuff far outweigh the uselessness of the muxes. It still is a shame the muxes are not oriented so that the inputs are from adjacent columns so that the bit pitches match. The SRL16's are especially powerful as well as under-appreciated. I still count those as LUTs if I am comparing FPGAs though, but keeping in mind there is no equivalent in the competing arrays. I'd trade away the muxes long before I gave up the carry chains and SRL16s (Xilinx still has the best carry chain structure out of all the FPGA vendors). Peter Alfke wrote: > So, the 12.5% stand for "virtually useless" multiplexers, useful RAM > capability, and the super-useful SRL16 shift-register capability that > enhances Ray's formidable talents even more. :-) > > Peter Alfke > ================================== > Ray Andraka wrote: > > > > True, but those muxes are virtually useless for data path because the bit > > pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or > > flip-flops instead. > > > > P -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Thu, 18 Sep 2003 10:29:44 -0400 Organization: Arius, Inc Lines: 50 Message-ID: <3F69C158.C4791464@yahoo.com> References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVa5xOZc9yryzyQ05fm2nMBscAr0Vy9uG14LeZR68oIrF7XpnWHjZLZc X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 18 Sep 2003 14:29:45 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!newsfeed.mathworks.com!news-out.cwix.com!newsfeed.cwix.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33116 Ray Andraka wrote: > > True, but those muxes are virtually useless for data path because the bit > pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or > flip-flops instead. > > Peter Alfke wrote: > > > rickman wrote: > > > Xilinx likes to > > > pad the number since they feel they have "uber-cells" which count as > > > more than 1 each. But then again, they don't define the term "logic > > > cell", so I guess they can count them any way they want. > > > > Not really, the "padding" is exactly 12.5%, so it has been defined and > > is deterministic. > > Marketing wants to get credit for the additional multiplexers that the > > competition does not have. > > If you are a purist, just count slices and devide by 2, or multiply CLBs > > by 4 (Virtex and Spartan2) or by 8 (Virtex2 and Spartan3). That gets you > > the number of LUTs+flip-flops. > > > > Peter Alfke > > > Personally, I find marketing to frequently be irritating and annoying. When I try to get technical information from a data sheet or web site and marketing distorts or glamorizes the information so much that it interferes with my work, I find that both an insult to my intelligence and a waste of my time. I am aware of why Xilinx marketing distorts the cell counts and I don't really care by how much. I care about the fact that I have to ignore a column of data in a data sheet as marketing hype and use a calculator to get the *real* numbers. Clearly the marketing people don't think we can add and multiply ourselves. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Thu, 18 Sep 2003 08:57:58 -0700 Organization: Xilinx,Inc Lines: 21 Message-ID: <3F69D605.63B715DB@xilinx.com> References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.news2me.com!Spring.edu.tw!news.nctu.edu.tw!netnews.eranet.net!news.ttn.net!feeder.seed.net.tw!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33051 Rick, I will not defend the +12,5%, but I can explain it: It is the price we all pay for the intense and sometimes ruthless competition in this market. Without a bloodthirsty competitor "in our rear-view mirror", we would be gentlemanlike and give you conservative numbers. But the way it is, our marketing folks think it would throw away some really (really!) powerful features if they are not somehow represented in the numbers. Each Xilinx Logic Cell does more than an Altera LE, there can be no doubt about that. This is not an excuse (personally I agree with you), but an explanation. Peter Alfke ========================== rickman wrote: I care about the fact that I have to ignore a > column of data in a data sheet as marketing hype and use a calculator to > get the *real* numbers. Clearly the marketing people don't think we can > add and multiply ourselves. > ###### From: "Paul Leventis" Newsgroups: comp.arch.fpga References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> <3F69D605.63B715DB@xilinx.com> Subject: Re: Xilinx Lines: 51 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Date: Fri, 19 Sep 2003 04:36:07 GMT NNTP-Posting-Host: 24.157.169.82 X-Complaints-To: abuse@rogers.com X-Trace: news04.bloor.is.net.cable.rogers.com 1063946167 24.157.169.82 (Fri, 19 Sep 2003 00:36:07 EDT) NNTP-Posting-Date: Fri, 19 Sep 2003 00:36:07 EDT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!newsfeed.cwix.com!cyclone01.bloor.is.net.cable.rogers.com!news04.bloor.is.net.cable.rogers.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33063 I might as well give the Altera view -- 12.5% is a gross overstatement of the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests that nearly the reverse is true (about a 9% advantage for Stratix). Please see the following whitepaper for our reasoning and data. As you can see from Figure 1, your mileage will vary -- depending on your design, you could see vast density advantages from one architecture or the other. http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf If we wanted to, we could start counting our M512 blocks as logic, as they can be used for shift-registers, small memories, and soft multipliers, but we don't bother. Bottom line -- you really need to compile *your* design to both Stratix and Virtex (or whatever families you are interested in) before you will really know what the story is density. Averages don't matter much to you if yours is that design that gets hosed in one architecture or the other! Regards, Paul Leventis Altera Corp. "Peter Alfke" wrote in message news:3F69D605.63B715DB@xilinx.com... > Rick, I will not defend the +12,5%, but I can explain it: > > It is the price we all pay for the intense and sometimes ruthless > competition in this market. Without a bloodthirsty competitor "in our > rear-view mirror", we would be gentlemanlike and give you conservative > numbers. But the way it is, our marketing folks think it would throw > away some really (really!) powerful features if they are not somehow > represented in the numbers. Each Xilinx Logic Cell does more than an > Altera LE, there can be no doubt about that. > > This is not an excuse (personally I agree with you), but an explanation. > > Peter Alfke > ========================== > > rickman wrote: > I care about the fact that I have to ignore a > > column of data in a data sheet as marketing hype and use a calculator to > > get the *real* numbers. Clearly the marketing people don't think we can > > add and multiply ourselves. > > ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Fri, 19 Sep 2003 06:40:38 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> <3F69D605.63B715DB@xilinx.com> X-Complaints-To: abuse@supernews.com Lines: 28 Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!sn-xit-03!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:33070 >Bottom line -- you really need to compile *your* design to both Stratix and >Virtex (or whatever families you are interested in) before you will really >know what the story is density. Averages don't matter much to you if yours >is that design that gets hosed in one architecture or the other! Is just recompiling good enough to be interesting? (Yes, better than nothing and I'll take whatever I can get.) Suppose I start with some "clean" vendor neutral code. How much do I gain in speed or space by hacking the code to take advantage of special features of an architecture? If I have code that has been tweaked for one vendor, does that get in the way (as compared to not help) if I just compile it for another architecture? How often is real code thoroughly tied to a particular chip? Say by adjusting the pipeline to fit well. Or using a multiplier as a shifter because it would otherwise be idle. Or do all interesting FPGAs these days have multipliers and dual port RAMs and ... that are reasonably equivalent? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Fri, 19 Sep 2003 10:06:10 -0700 Organization: Xilinx,Inc Lines: 45 Message-ID: <3F6B3782.FE819602@xilinx.com> References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> <3F69D605.63B715DB@xilinx.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!in.100proofnews.com!in.100proofnews.com!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33050 If anybody designs "vendor neutral" and relies on the compiler to get the best implementation in, say, Xilinx and Altera, the result will most likely the worst of all worlds. FPGA architecture evolution is still young. Certain aspects are almost standardized (4LUTs, carry, dual-ported RAMs, flexible-level I/O), but each vendor tries to outdo the other with clever and (hopefully) useful additions that the competitor does not (yet) have. Xilinx is very proud of its LUTRAMs, SRL16s and DCMs with fine phase stepping. I assume that Altera has their own very different goodies. There is no way that the "generic compiler" will make good use of all this. So it still takes a smart and imaginative designer to navigate between all these exciting capabilities that differentiate the vendors. FPGA are not (yet) a standardized commodity, the way automobiles have become after 100 years of evolution. Thank God ! Peter Alfke Hal Murray wrote: > > >Bottom line -- you really need to compile *your* design to both Stratix and > >Virtex (or whatever families you are interested in) before you will really > >know what the story is density. Averages don't matter much to you if yours > >is that design that gets hosed in one architecture or the other! > > Is just recompiling good enough to be interesting? (Yes, better > than nothing and I'll take whatever I can get.) > > Suppose I start with some "clean" vendor neutral code. How much do > I gain in speed or space by hacking the code to take advantage of > special features of an architecture? > > If I have code that has been tweaked for one vendor, does that get > in the way (as compared to not help) if I just compile it for > another architecture? > > How often is real code thoroughly tied to a particular chip? > Say by adjusting the pipeline to fit well. Or using a multiplier > as a shifter because it would otherwise be idle. > Or do all interesting FPGAs these days have multipliers and > dual port RAMs and ... that are reasonably equivalent? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. ###### From: Mike Treseler Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Fri, 19 Sep 2003 10:50:32 -0700 Organization: Fluke Networks Lines: 51 Message-ID: <3F6B41E8.2040904@flukenetworks.com> References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> <3F69D605.63B715DB@xilinx.com> NNTP-Posting-Host: slick.tc.fluke.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4) Gecko/20030624 X-Accept-Language: en-us, en In-Reply-To: Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!newsfeed3.funet.fi!newsfeed2.funet.fi!newsfeeds.funet.fi!nntp.inet.fi!inet.fi!ash.uu.net!fluke!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33064 Hal Murray wrote: > Is just recompiling good enough to be interesting? (Yes, better > than nothing and I'll take whatever I can get.) I always test synth code on both brands. > Suppose I start with some "clean" vendor neutral code. How much do > I gain in speed or space by hacking the code to take advantage of > special features of an architecture? You can make significant improvements in speed and space. The downside is a longer design time, a commitment to a single family from a single vendor and complications to simulation and design reuse. > If I have code that has been tweaked for one vendor, does that get > in the way (as compared to not help) if I just compile it for > another architecture? In that case, you must learn the alternate architecture and recode all of the vendor specific instances and attributes. > How often is real code thoroughly tied to a particular chip? It's quite easy to do. Both brands A and X lead you down that path with wizards, core generators and app notes. > Say by adjusting the pipeline to fit well. Or using a multiplier > as a shifter because it would otherwise be idle. That is a design decision. If you design with inference only, you lose some options. > Or do all interesting FPGAs these days have multipliers and > dual port RAMs and ... that are reasonably equivalent? The common inferrable set includes carry chains, ram, rom and and pseudo-dual port ram like this: if rising_edge(clk) then if we = '1' then mem(to_integer(push_tail_ptr)) <= data_i; -- raw address end if; data_q <= mem(to_integer(pop_head_ptr)); -- mem data after pop low end if; -- Mike Treseler ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: 19 Sep 2003 22:35:30 +0200 Organization: My own Private Self Lines: 45 Message-ID: <6u3cesectp.fsf@chonsp.franklin.ch> References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F690063.C63D1FEA@xilinx.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1064003730 562 10.0.3.2 (19 Sep 2003 20:35:30 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 19 Sep 2003 20:35:30 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:33117 Peter Alfke writes: > Ray Andraka wrote: > > > > True, but those muxes are virtually useless for data path because the bit > > pitch doesn't match the bit pitch of the arithmetic. No problem at all. 2 LUTs with F5 enabled may by double the vertical size of an data path bit. But as one is not using the carry chain when using F5 (the Lut/Fn/carry MUX ensures this) it is no problem to "zigzag" data path bits. Put each pair of data path bits into 2 vertical stripes of slices, very simple: . . . . . . . . 3 2 3 3 0..3.. = where bit gets processed 2 2>3> 2 > = enabled F5 MUX 1 0 1 1 0 0>1> 0 And with F5 being "vertical" it can be used (combining 2 LUTS to an 8 input AND or OR) in the corresponding control logic of an 1 slice wide data path segment, without having to sacrifice an 2nd slice or use up logic of the next (or even worse previous) segments control logic space. Now F6 using 2 horizontally neighboring slices (which is what you suggest for F5), that messes this scheme up. > So, the 12.5% stand for "virtually useless" multiplexers, useful RAM > capability, and the super-useful SRL16 shift-register capability that > enhances Ray's formidable talents even more. :-) Or the 12.5% stand for "LUT-saving and next to no delay" 2nd level in multiplexers (halves levels, 2/3s LUT usage), usefull RAM (inclusive F5-using 32bit, same trick!) and "I don't reconfigure LUTs" useless SRL16s. :-) Everyone sees their 1/8th of an LUT in different extra features. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Fri, 19 Sep 2003 13:41:54 -0700 Organization: Xilinx, Inc. Lines: 127 Message-ID: <3F6B6A12.1ABD80A8@xilinx.com> References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> <3F69D605.63B715DB@xilinx.com> <3F6B58CD.C243C47D@andraka.com> NNTP-Posting-Host: 149.199.53.89 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.79 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!npeer.de.kpn-eurorings.net!newsfeed.media.kyoto-u.ac.jp!Spring.edu.tw!news.nctu.edu.tw!netnews.eranet.net!news.ttn.net!feeder.seed.net.tw!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33121 Ray, You failed to take into account the many IP cores that are available that are optimized for a particular architecture. Examine the vendor's own free IP, for fee IP, and the community around that vendor for the number of independent or partner vendors of IP. You don't always have to suddenly create the most complex and highest performing logic out of thin air (as that is a tough job for the best of us). And don't forget the many talented consultants that create product specific IP that beats the performance of the best cores that folks may offer. But it is true that the more specialized and targeted you get, the less likely it will port conveniently to any other device, other than the manufacturer that it was originally on (and not even then if it is a new architecture). Austin Ray Andraka wrote: > The equation for utilization is very complex. For arithmetic data path however, > I do find > that the Xilinx structure permits a higher density measured in LUTs occupied > when comparing designs > for the same algorithm but optimized for the particular device. This is due > partially > to the fact that the Altera carry chain breaks the LUTs into a pair of 3 LUTs so > your arithmetic is > 2 input arithmetic where Xilinx's is 4 input arithmetic. Granted, Altera has > greatly improved the situation > by adding dedicated gating for doing an adder-subtracter in one level, as well > as logic to permit an > accumulator with load, which are probably the most common use of more than two > input arithmetic. > To be fair, the average user is not going to fully use the Xilinx capability > because the synthesis tools > do not do a great job at inferring more complex structures such as an add/mux or > mux/add etc. In order > to use that, you more or less need to do some very careful coding. Same is true > for taking advantage of > the SRL16s. > > The fact of the matter is, I think both vendor's numbers are slanted. Unless > you do the design with the > specific architecture in mind, you are not going to get optimum utilization of > that array. A design that is > optimized for one array is going to generally be a poor fit for another. > Presumably, both vendors have > taken a design or designs that were targetted to their parts, and then ported > those designs to the competition > to come up with these numbers. In both cases, naturally, their device is going > to show superior results > simply because the design database they are drawing upon was optimized to their > parts. > > As I've stated many times before, the comparison metric should be a raw count of > the number of 4 LUT/flip-flop > pairs plus a list of additional features with perhaps an equivalent utilization > of that feature if it were not available. > That way, the designer can make an informed decision based on what features he > thinks he will use. In cases > where he doesn't know, the most accurate comparision would be to ignore the > effect of special features altogether, > then accept the gains he gets by using them as gravy. > > Paul Leventis wrote: > > > I might as well give the Altera view -- 12.5% is a gross overstatement of > > the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests > > that nearly the reverse is true (about a 9% advantage for Stratix). Please > > see the following whitepaper for our reasoning and data. As you can see > > from Figure 1, your mileage will vary -- depending on your design, you could > > see vast density advantages from one architecture or the other. > > > > http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf > > > > If we wanted to, we could start counting our M512 blocks as logic, as they > > can be used for shift-registers, small memories, and soft multipliers, but > > we don't bother. > > > > Bottom line -- you really need to compile *your* design to both Stratix and > > Virtex (or whatever families you are interested in) before you will really > > know what the story is density. Averages don't matter much to you if yours > > is that design that gets hosed in one architecture or the other! > > > > Regards, > > > > Paul Leventis > > Altera Corp. > > > > "Peter Alfke" wrote in message > > news:3F69D605.63B715DB@xilinx.com... > > > Rick, I will not defend the +12,5%, but I can explain it: > > > > > > It is the price we all pay for the intense and sometimes ruthless > > > competition in this market. Without a bloodthirsty competitor "in our > > > rear-view mirror", we would be gentlemanlike and give you conservative > > > numbers. But the way it is, our marketing folks think it would throw > > > away some really (really!) powerful features if they are not somehow > > > represented in the numbers. Each Xilinx Logic Cell does more than an > > > Altera LE, there can be no doubt about that. > > > > > > This is not an excuse (personally I agree with you), but an explanation. > > > > > > Peter Alfke > > > ========================== > > > > > > rickman wrote: > > > I care about the fact that I have to ignore a > > > > column of data in a data sheet as marketing hype and use a calculator to > > > > get the *real* numbers. Clearly the marketing people don't think we can > > > > add and multiply ourselves. > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Xilinx Date: Mon, 22 Sep 2003 02:52:03 -0400 Organization: Arius, Inc Lines: 54 Message-ID: <3F6E9C13.3B65F43E@yahoo.com> References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> <3F69D605.63B715DB@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVYZu1OvG37AtTHKCXP84V962A0yJq8BKjTl1+DxzCjRyqMq2kTWYF2E X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 22 Sep 2003 06:52:00 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33159 To Peter, Paul and all the other apostles... :) My point is that as an engineer, I can figure out what is best for my design. If I can't, then shame on me. But giving me phoney numbers (which is what the Xilinx cell counts are no matter how marketing justifies them) just makes the vendor look bad to engineers. If Xilinx has better cells, then tell me that! Don't try to tell me you have more cells than you really do, that is utter nonsense!!! I have always and expect *will* always resent the "spin" that marketing puts on what is really a very technical business. I remember the first time I noticed an overly "marketized" web site that was hard to view because of the large graphic files that added nothing to the information I wanted. I also remember the first time an information file was altered by marketing so much that it was not usable on any of the machines I had available. I have yet to see any added value in any of the documentation or even in the advertising that the marketing people put out. Heck, it was only a few weeks ago that I even learned what a "platform" chip was after having read about it in FPGA advertising for what... three or four years? Before we let Shakespeare kill all the lawyers, let's kill all the marketeers! Paul Leventis wrote: > > I might as well give the Altera view -- 12.5% is a gross overstatement of > the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests > that nearly the reverse is true (about a 9% advantage for Stratix). Please > see the following whitepaper for our reasoning and data. As you can see > from Figure 1, your mileage will vary -- depending on your design, you could > see vast density advantages from one architecture or the other. ...snip... > "Peter Alfke" wrote in message > news:3F69D605.63B715DB@xilinx.com... > > Rick, I will not defend the +12,5%, but I can explain it: ...snip... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Simon Peacock" Newsgroups: comp.arch.fpga References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> <3F69D605.63B715DB@xilinx.com> <3F6E9C13.3B65F43E@yahoo.com> Subject: Re: Xilinx Lines: 74 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 X-Original-NNTP-Posting-Host: 202.154.130.246 Message-ID: <3f6ea06d@news.actrix.gen.nz> Date: Mon, 22 Sep 2003 19:10:25 +1200 NNTP-Posting-Host: 203.96.16.33 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1064214638 203.96.16.33 (Mon, 22 Sep 2003 19:10:38 NZST) NNTP-Posting-Date: Mon, 22 Sep 2003 19:10:38 NZST Organization: TelstraClear Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!news.maxwell.syr.edu!in.100proofnews.com!in.100proofnews.com!news02.tsnz.net!news.actrix.gen.nz!202.154.130.246 Xref: chonsp.franklin.ch comp.arch.fpga:33177 I just noticed that HDD manufacturers are getting sued over binary Megabyte vs. decimal megabyte.. perhaps they could do Xilinx when they are finished ?? :-) But seriously..I hope Xilinx are watching.. I think the same rules would have to apply here. chickens are chickens just don't count them until they hatch :-) Simon "rickman" wrote in message news:3F6E9C13.3B65F43E@yahoo.com... > To Peter, Paul and all the other apostles... :) > > My point is that as an engineer, I can figure out what is best for my > design. If I can't, then shame on me. But giving me phoney numbers > (which is what the Xilinx cell counts are no matter how marketing > justifies them) just makes the vendor look bad to engineers. If Xilinx > has better cells, then tell me that! Don't try to tell me you have more > cells than you really do, that is utter nonsense!!! > > I have always and expect *will* always resent the "spin" that marketing > puts on what is really a very technical business. I remember the first > time I noticed an overly "marketized" web site that was hard to view > because of the large graphic files that added nothing to the information > I wanted. I also remember the first time an information file was > altered by marketing so much that it was not usable on any of the > machines I had available. I have yet to see any added value in any of > the documentation or even in the advertising that the marketing people > put out. Heck, it was only a few weeks ago that I even learned what a > "platform" chip was after having read about it in FPGA advertising for > what... three or four years? > > Before we let Shakespeare kill all the lawyers, let's kill all the > marketeers! > > > Paul Leventis wrote: > > > > I might as well give the Altera view -- 12.5% is a gross overstatement of > > the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests > > that nearly the reverse is true (about a 9% advantage for Stratix). Please > > see the following whitepaper for our reasoning and data. As you can see > > from Figure 1, your mileage will vary -- depending on your design, you could > > see vast density advantages from one architecture or the other. > > ...snip... > > > "Peter Alfke" wrote in message > > news:3F69D605.63B715DB@xilinx.com... > > > Rick, I will not defend the +12,5%, but I can explain it: > > ...snip... > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3F7B6DA7.178FBED8@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Xilinx References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F690063.C63D1FEA@xilinx.com> <6u3cesectp.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 63 Date: Wed, 01 Oct 2003 20:13:27 -0400 NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: lakeread05 1065053026 68.15.41.165 (Wed, 01 Oct 2003 20:03:46 EDT) NNTP-Posting-Date: Wed, 01 Oct 2003 20:03:46 EDT Path: chonsp.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!peer01.cox.net!cox.net!p01!lakeread05.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33657 Yes, in theory that is correct. I've had problems with the mapper and/or floorplanner accepting F5 muxes packed this way in the past. Usually however, I don't use them. Still, in most cases the Virtex2 architecture is a clean hands down winner. Neil Franklin wrote: > Peter Alfke writes: > > Ray Andraka wrote: > > > > > > True, but those muxes are virtually useless for data path because the bit > > > pitch doesn't match the bit pitch of the arithmetic. > > No problem at all. 2 LUTs with F5 enabled may by double the vertical > size of an data path bit. But as one is not using the carry chain > when using F5 (the Lut/Fn/carry MUX ensures this) it is no problem > to "zigzag" data path bits. Put each pair of data path bits into 2 > vertical stripes of slices, very simple: > > . . . . > . . . . > 3 2 3 3 0..3.. = where bit gets processed > 2 2>3> 2 > = enabled F5 MUX > 1 0 1 1 > 0 0>1> 0 > > And with F5 being "vertical" it can be used (combining 2 LUTS to an 8 > input AND or OR) in the corresponding control logic of an 1 slice wide > data path segment, without having to sacrifice an 2nd slice or use up > logic of the next (or even worse previous) segments control logic space. > > Now F6 using 2 horizontally neighboring slices (which is what you > suggest for F5), that messes this scheme up. > > > So, the 12.5% stand for "virtually useless" multiplexers, useful RAM > > capability, and the super-useful SRL16 shift-register capability that > > enhances Ray's formidable talents even more. :-) > > Or the 12.5% stand for "LUT-saving and next to no delay" 2nd level in > multiplexers (halves levels, 2/3s LUT usage), usefull RAM (inclusive > F5-using 32bit, same trick!) and "I don't reconfigure LUTs" useless > SRL16s. :-) > > Everyone sees their 1/8th of an LUT in different extra features. > > -- > Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ > Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith > - hardware runs the world, software controls the hardware > code generates the software, have you coded today? -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3F7B6E55.40DB3EC@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Xilinx References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> <3F69D605.63B715DB@xilinx.com> <3F6B58CD.C243C47D@andraka.com> <3F6B6A12.1ABD80A8@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 146 Date: Wed, 01 Oct 2003 20:16:21 -0400 NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: lakeread05 1065053200 68.15.41.165 (Wed, 01 Oct 2003 20:06:40 EDT) NNTP-Posting-Date: Wed, 01 Oct 2003 20:06:40 EDT Path: chonsp.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!peer01.cox.net!cox.net!p01!lakeread05.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33652 Perhaps I missed saying it here. I have stated many times in the past that the best fit for a particular target is probably going to map pretty poorly to another architecture. My internal IP is for the most part built up out of primitives to even get placement optimal. Austin Lesea wrote: > Ray, > > You failed to take into account the many IP cores that are available that are > optimized for a particular architecture. > > Examine the vendor's own free IP, for fee IP, and the community around that vendor > for the number of independent or partner vendors of IP. > > You don't always have to suddenly create the most complex and highest performing > logic out of thin air (as that is a tough job for the best of us). > > And don't forget the many talented consultants that create product specific IP that > beats the performance of the best cores that folks may offer. > > But it is true that the more specialized and targeted you get, the less likely it > will port conveniently to any other device, other than the manufacturer that it was > originally on (and not even then if it is a new architecture). > > Austin > > Ray Andraka wrote: > > > The equation for utilization is very complex. For arithmetic data path however, > > I do find > > that the Xilinx structure permits a higher density measured in LUTs occupied > > when comparing designs > > for the same algorithm but optimized for the particular device. This is due > > partially > > to the fact that the Altera carry chain breaks the LUTs into a pair of 3 LUTs so > > your arithmetic is > > 2 input arithmetic where Xilinx's is 4 input arithmetic. Granted, Altera has > > greatly improved the situation > > by adding dedicated gating for doing an adder-subtracter in one level, as well > > as logic to permit an > > accumulator with load, which are probably the most common use of more than two > > input arithmetic. > > To be fair, the average user is not going to fully use the Xilinx capability > > because the synthesis tools > > do not do a great job at inferring more complex structures such as an add/mux or > > mux/add etc. In order > > to use that, you more or less need to do some very careful coding. Same is true > > for taking advantage of > > the SRL16s. > > > > The fact of the matter is, I think both vendor's numbers are slanted. Unless > > you do the design with the > > specific architecture in mind, you are not going to get optimum utilization of > > that array. A design that is > > optimized for one array is going to generally be a poor fit for another. > > Presumably, both vendors have > > taken a design or designs that were targetted to their parts, and then ported > > those designs to the competition > > to come up with these numbers. In both cases, naturally, their device is going > > to show superior results > > simply because the design database they are drawing upon was optimized to their > > parts. > > > > As I've stated many times before, the comparison metric should be a raw count of > > the number of 4 LUT/flip-flop > > pairs plus a list of additional features with perhaps an equivalent utilization > > of that feature if it were not available. > > That way, the designer can make an informed decision based on what features he > > thinks he will use. In cases > > where he doesn't know, the most accurate comparision would be to ignore the > > effect of special features altogether, > > then accept the gains he gets by using them as gravy. > > > > Paul Leventis wrote: > > > > > I might as well give the Altera view -- 12.5% is a gross overstatement of > > > the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests > > > that nearly the reverse is true (about a 9% advantage for Stratix). Please > > > see the following whitepaper for our reasoning and data. As you can see > > > from Figure 1, your mileage will vary -- depending on your design, you could > > > see vast density advantages from one architecture or the other. > > > > > > http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf > > > > > > If we wanted to, we could start counting our M512 blocks as logic, as they > > > can be used for shift-registers, small memories, and soft multipliers, but > > > we don't bother. > > > > > > Bottom line -- you really need to compile *your* design to both Stratix and > > > Virtex (or whatever families you are interested in) before you will really > > > know what the story is density. Averages don't matter much to you if yours > > > is that design that gets hosed in one architecture or the other! > > > > > > Regards, > > > > > > Paul Leventis > > > Altera Corp. > > > > > > "Peter Alfke" wrote in message > > > news:3F69D605.63B715DB@xilinx.com... > > > > Rick, I will not defend the +12,5%, but I can explain it: > > > > > > > > It is the price we all pay for the intense and sometimes ruthless > > > > competition in this market. Without a bloodthirsty competitor "in our > > > > rear-view mirror", we would be gentlemanlike and give you conservative > > > > numbers. But the way it is, our marketing folks think it would throw > > > > away some really (really!) powerful features if they are not somehow > > > > represented in the numbers. Each Xilinx Logic Cell does more than an > > > > Altera LE, there can be no doubt about that. > > > > > > > > This is not an excuse (personally I agree with you), but an explanation. > > > > > > > > Peter Alfke > > > > ========================== > > > > > > > > rickman wrote: > > > > I care about the fact that I have to ignore a > > > > > column of data in a data sheet as marketing hype and use a calculator to > > > > > get the *real* numbers. Clearly the marketing people don't think we can > > > > > add and multiply ourselves. > > > > > > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3F7B6EB7.4A2F881E@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Xilinx References: <3F68637C.CD3D9FCA@yahoo.com> <3F68851A.74DE66EC@xilinx.com> <3F68D834.E7081F24@andraka.com> <3F69C158.C4791464@yahoo.com> <3F69D605.63B715DB@xilinx.com> <3F6E9C13.3B65F43E@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 15 Date: Wed, 01 Oct 2003 20:17:59 -0400 NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: lakeread05 1065053298 68.15.41.165 (Wed, 01 Oct 2003 20:08:18 EDT) NNTP-Posting-Date: Wed, 01 Oct 2003 20:08:18 EDT Path: chonsp.franklin.ch!pfaff2.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!in.100proofnews.com!in.100proofnews.com!cox.net!news-xfer.cox.net!p01!lakeread05.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:33656 Nah, Lawyers are still top of the list in my book. -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759