From: oen_br@yahoo.com.br (Luiz Carlos) Newsgroups: comp.arch.fpga Subject: More about metastability Date: 4 Sep 2003 03:55:38 -0700 Organization: http://groups.google.com/ Lines: 13 Message-ID: <8471ba54.0309040255.3d79ed94@posting.google.com> NNTP-Posting-Host: 200.102.50.240 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1062672940 4295 127.0.0.1 (4 Sep 2003 10:55:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 4 Sep 2003 10:55:40 GMT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.news2me.com!elnk-pas-nf1!newsfeed.earthlink.net!newshub.sdsu.edu!headwall.stanford.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32530 Metastability occurs when we don't respect setup and/or hold times. But what does happen when the input for the flip-flop is a DC signal between Vil and Vih? (Or it changes so slowly that looks like a constant.) My guess is there is a voltage, let's say Vth, that: If Vin < Vth => DOUT = 0 after a delay If Vin > Vth => DOUT = 1 after a delay The delay grows as Vin approximates to Vth. Am I right? Luiz Carlos ###### From: "Alvin Andries" Newsgroups: comp.arch.fpga Subject: Re: More about metastability Date: Thu, 4 Sep 2003 13:28:45 +0200 Organization: Agilent Technologies Lines: 34 Message-ID: <1062674929.962020@cswreg.cos.agilent.com> References: <8471ba54.0309040255.3d79ed94@posting.google.com> NNTP-Posting-Host: cswreg.cos.agilent.com X-Trace: cswtrans.cos.agilent.com 1062674930 4976 130.29.154.45 (4 Sep 2003 11:28:50 GMT) X-Complaints-To: usenet@cswtrans.cos.agilent.com NNTP-Posting-Date: Thu, 4 Sep 2003 11:28:50 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4920.2300 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4920.2300 Cache-Post-Path: cswreg.cos.agilent.com!unknown@dhcp-comet-33.belgium.agilent.com X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!sjc70.webusenet.com!news.webusenet.com!news.isc.org!agilent.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32521 "Luiz Carlos" wrote in message news:8471ba54.0309040255.3d79ed94@posting.google.com... > Metastability occurs when we don't respect setup and/or hold times. > But what does happen when the input for the flip-flop is a DC signal > between Vil and Vih? (Or it changes so slowly that looks like a > constant.) > > My guess is there is a voltage, let's say Vth, that: > If Vin < Vth => DOUT = 0 after a delay > If Vin > Vth => DOUT = 1 after a delay > The delay grows as Vin approximates to Vth. > > Am I right? > > Luiz Carlos Hi Luiz, You're right. Things could even be worse: in cmos technology, applying a voltage around Vt at an input consisting of 2 complementary transistors will cause both fets to conduct, resulting in local excessive power dissipation. Depending on the exact design of the input, this may even lead to permanent damage. Assuming that you're using a modern fpga, this is most likely solved by the manufacturer by using an input with hysteresis. As a counter example: I've seen diagrams where a 4000 (or 74HC00) is used as voltage controlled sine oscillator. Regards, Alvin. ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: More about metastability Date: Thu, 04 Sep 2003 07:53:27 -0700 Organization: Xilinx, Inc. Lines: 51 Message-ID: <3F5751E7.A953A7BE@xilinx.com> References: <8471ba54.0309040255.3d79ed94@posting.google.com> <1062674929.962020@cswreg.cos.agilent.com> NNTP-Posting-Host: 149.199.54.205 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.79 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!zen.net.uk!newsfeed.media.kyoto-u.ac.jp!Spring.edu.tw!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32514 Alvin, One common mis-conception is that you can "hurt" or damage the FPGA by having the input voltage float at exactly the wrong point. Un-true: the IOBs are designed with sufficient metal and device contacts to remain in contention forever without damage. The ~500 uA of contention is hardly noticeable in the overall scheme of things. So, don't let inputs float (bad practice) but don't stress about it, as no damage will result in our FPGA input structures. If you think about it, how can we offer LVDS, HSTL, SSTL, GTL, LVCMOS all on the same pin without taking this into account? Austin Alvin Andries wrote: > "Luiz Carlos" wrote in message > news:8471ba54.0309040255.3d79ed94@posting.google.com... > > Metastability occurs when we don't respect setup and/or hold times. > > But what does happen when the input for the flip-flop is a DC signal > > between Vil and Vih? (Or it changes so slowly that looks like a > > constant.) > > > > My guess is there is a voltage, let's say Vth, that: > > If Vin < Vth => DOUT = 0 after a delay > > If Vin > Vth => DOUT = 1 after a delay > > The delay grows as Vin approximates to Vth. > > > > Am I right? > > > > Luiz Carlos > > Hi Luiz, > > You're right. > > Things could even be worse: in cmos technology, applying a voltage around Vt > at an input consisting of 2 complementary transistors will cause both fets > to conduct, resulting in local excessive power dissipation. Depending on the > exact design of the input, this may even lead to permanent damage. Assuming > that you're using a modern fpga, this is most likely solved by the > manufacturer by using an input with hysteresis. As a counter example: I've > seen diagrams where a 4000 (or 74HC00) is used as voltage controlled sine > oscillator. > > Regards, > Alvin.