From: peter.zhu@utstar.com (peterzhu) Newsgroups: comp.arch.fpga Subject: How to extend a pulse width without clock! Date: 3 Sep 2003 01:30:02 -0700 Organization: http://groups.google.com/ Lines: 6 Message-ID: <61c1427f.0309030030.57cc99c4@posting.google.com> NNTP-Posting-Host: 210.21.224.54 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1062577803 6405 127.0.0.1 (3 Sep 2003 08:30:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 3 Sep 2003 08:30:03 GMT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32494 Due to a chip bug, I have to extend a pulse width(negative)from 10ns to 100ms in CPLD(Altera 7128). But the difficult is that I have no any clock into the CPLD, so the CPLD is pure combination logic. how to extend it in such case? Help me! ###### From: "Simon Peacock" Newsgroups: comp.arch.fpga References: <61c1427f.0309030030.57cc99c4@posting.google.com> Subject: Re: How to extend a pulse width without clock! Date: Wed, 3 Sep 2003 20:50:36 +1200 Lines: 18 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 NNTP-Posting-Host: 202.154.130.118 X-Original-NNTP-Posting-Host: 202.154.130.118 Message-ID: <3f55ab5d$1@news.actrix.gen.nz> X-Trace: 3 Sep 2003 20:50:37 NZST, 202.154.130.118 Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!in.100proofnews.com!in.100proofnews.com!news02.tsnz.net!newsfeed01.tsnz.net!news!news.iprolink.co.nz!news.actrix.gen.nz!202.154.130.118 Xref: chonsp.franklin.ch comp.arch.fpga:32465 Am not sure you can.. all the logic on the chip can't generate that kind of delay.. but you might find another signal which you can use as a clock A0 if you have a micro.. or ALE.. WR.. RD something like that.. failing that.. an RC off chip :-) Simon "peterzhu" wrote in message news:61c1427f.0309030030.57cc99c4@posting.google.com... > Due to a chip bug, I have to extend a pulse width(negative)from 10ns > to 100ms in CPLD(Altera 7128). But the difficult is that I have no any > clock into the CPLD, so the CPLD is pure combination logic. how to > extend it in such case? > > Help me! ###### From: antti@case2000.com (Antti Lukats) Newsgroups: comp.arch.fpga Subject: Re: How to extend a pulse width without clock! Date: 3 Sep 2003 06:47:13 -0700 Organization: http://groups.google.com/ Lines: 18 Message-ID: <80a3aea5.0309030547.ee9b1cb@posting.google.com> References: <61c1427f.0309030030.57cc99c4@posting.google.com> <3f55ab5d$1@news.actrix.gen.nz> NNTP-Posting-Host: 80.142.84.100 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1062596834 25311 127.0.0.1 (3 Sep 2003 13:47:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 3 Sep 2003 13:47:14 GMT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32504 > "peterzhu" wrote in message > news:61c1427f.0309030030.57cc99c4@posting.google.com... > > Due to a chip bug, I have to extend a pulse width(negative)from 10ns > > to 100ms in CPLD(Altera 7128). But the difficult is that I have no any > > clock into the CPLD, so the CPLD is pure combination logic. how to > > extend it in such case? uups, bad luck - not recommended but if you have enough free pins and logic you and if the timing is not critical it is possible to make free running oscillator without external RC components, just connect uneven count of inverters in ring (ie 3 inverters) as this is astable it will oscillate with pretty high frequency, this could be divided down, but from about 40MHz down to 100ms its pretty long counter ... and this approuch really isnt 'recommended' as other options build simple RC on IO cells and use that signal antti ###### From: Jon Elson Newsgroups: comp.arch.fpga Subject: Re: How to extend a pulse width without clock! Date: Thu, 04 Sep 2003 00:32:17 -0500 Organization: Pico Systems Lines: 25 Message-ID: <3F56CE61.5010802@pico-systems.com> References: <61c1427f.0309030030.57cc99c4@posting.google.com> NNTP-Posting-Host: h-69-3-230-106.chcgilgm.covad.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: sun-news.laserlink.net 1062653288 15815 69.3.230.106 (4 Sep 2003 05:28:08 GMT) X-Complaints-To: abuse@covad.net NNTP-Posting-Date: Thu, 4 Sep 2003 05:28:08 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.0.2) Gecko/20030208 Netscape/7.02 X-Accept-Language: en-us, en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.abs.net!ash.uu.net!sun-news.laserlink.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32518 peterzhu wrote: >Due to a chip bug, I have to extend a pulse width(negative)from 10ns >to 100ms in CPLD(Altera 7128). But the difficult is that I have no any >clock into the CPLD, so the CPLD is pure combination logic. how to >extend it in such case? > >Help me! > > I have delayed strobe signals several hundred nS with an external series resistor, and used the input capacitance of the chip as the C of the RC network. For mS, you will need an external capacitor, of course. if you want the delay to be asymmetric (like a one-shot), you might need to put a diode in parallel with the R. You feed the signal out one pin, through a series R, to a pin loaded with a cap to ground, and then take the signal in from that pin. This may cause multiple pulses with a delay this long, however. So, you might end up using a 74HC4538 or similar one shot, or a 74HC14 Schmitt trigger to prevent the pulses as the output of the RC crosses the threshold. Jon ###### From: peter.zhu@utstar.com (peterzhu) Newsgroups: comp.arch.fpga Subject: Re: How to extend a pulse width without clock! Date: 4 Sep 2003 18:57:49 -0700 Organization: http://groups.google.com/ Lines: 29 Message-ID: <61c1427f.0309041757.486865d@posting.google.com> References: <61c1427f.0309030030.57cc99c4@posting.google.com> <3F56CE61.5010802@pico-systems.com> NNTP-Posting-Host: 210.21.224.54 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1062727071 28291 127.0.0.1 (5 Sep 2003 01:57:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 5 Sep 2003 01:57:51 GMT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32601 Jon Elson wrote in message news:<3F56CE61.5010802@pico-systems.com>... > peterzhu wrote: > > >Due to a chip bug, I have to extend a pulse width(negative)from 10ns > >to 100ms in CPLD(Altera 7128). But the difficult is that I have no any > >clock into the CPLD, so the CPLD is pure combination logic. how to > >extend it in such case? > > > >Help me! > > > > > I have delayed strobe signals several hundred nS with an external series > resistor, and used the input capacitance of the chip as the C of the RC > network. For mS, you will need an external capacitor, of course. if you > want the delay to be asymmetric (like a one-shot), you might need to > put a diode in parallel with the R. You feed the signal out one pin, > through a series R, to a pin loaded with a cap to ground, and then take > the signal in from that pin. This may cause multiple pulses with a > delay this long, however. So, you might end up using a 74HC4538 > or similar one shot, or a 74HC14 Schmitt trigger to prevent the > pulses as the output of the RC crosses the threshold. > > Jon The board is in production, so I can not change the SCH and PCB, all things should be done in CPLD. Peter ###### From: "Stephan Flock" Newsgroups: comp.arch.fpga Subject: Re: How to extend a pulse width without clock! Date: Fri, 5 Sep 2003 06:50:55 +0200 Organization: T-Online Lines: 8 Message-ID: References: <61c1427f.0309030030.57cc99c4@posting.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: news.t-online.com 1062737711 04 20942 jwsjVOXVSjY40m 030905 04:55:11 X-Complaints-To: usenet-abuse@t-online.de X-ID: XLVLhcZeweDaqazVeBykYpn0ij6pbbhanJtpBzQLh-MGuMaWkL-W4i X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!npeer.de.kpn-eurorings.net!newsfeed00.sul.t-online.de!newsmm00.sul.t-online.com!t-online.de!news.t-online.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32587 You could take two cascaded flip-flops, feed the first with '1' and use your 10 ns strobe as async reset for both. Take a 100 ms (10 Hz) clock or clock enable signal for the FFs and combine both outputs to a 100 ms strobe. Regards, Stephan Flock