From: nitin@tenet.res.in (Nitin Chandrachoodan) Newsgroups: comp.arch.fpga Subject: FPGA minimum operating frequencies Date: 25 Aug 2003 23:21:45 -0700 Organization: http://groups.google.com/ Lines: 12 Message-ID: <587c2bd7.0308252221.18186863@posting.google.com> NNTP-Posting-Host: 202.144.28.162 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1061878906 8033 127.0.0.1 (26 Aug 2003 06:21:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 26 Aug 2003 06:21:46 GMT Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.media.kyoto-u.ac.jp!headwall.stanford.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32214 Hello, I was wondering if there were any *lower* limits on the clock frequency that can be used to clock FPGAs (in particular the Xilinx Virtex II : XC2V3000). I know there are certain kinds of high speed logic families using precharge-discharge operation, where the leakage sets a lower limit on operating speed. Is there such a limit for these FPGAs, and if so, what is it (ballpark figures are fine). Thanks, Nitin ###### From: Mario Trams Newsgroups: comp.arch.fpga Subject: Re: FPGA minimum operating frequencies Date: Tue, 26 Aug 2003 10:46:30 +0200 Organization: TU Chemnitz Lines: 22 Message-ID: References: <587c2bd7.0308252221.18186863@posting.google.com> Reply-To: Mario.Trams@informatik.tu-chemnitz.de NNTP-Posting-Host: salomo.informatik.tu-chemnitz.de Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit X-Trace: anderson.hrz.tu-chemnitz.de 1061886473 21731 134.109.192.187 (26 Aug 2003 08:27:53 GMT) X-Complaints-To: abuse@tu-chemnitz.de NNTP-Posting-Date: Tue, 26 Aug 2003 08:27:53 +0000 (UTC) User-Agent: KNode/0.7.2 Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.freenet.de!news-lei1.dfn.de!news.tu-chemnitz.de!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32217 Nitin Chandrachoodan wrote: > Hello, > > I was wondering if there were any *lower* limits on the clock > frequency that can be used to clock FPGAs (in particular the Xilinx > Virtex II : XC2V3000). I know there are certain kinds of high speed > logic families using precharge-discharge operation, where the leakage > sets a lower limit on operating speed. Is there such a limit for these > FPGAs, and if so, what is it (ballpark figures are fine). All FPGAs (including Virtex II) and other programmable logic devices I know about are static devices. That is, all FlipFlops inside are complete static ones suitable for a clock from 0 to Fmax. Even more, there is no clock required at all. However, some FPGAs might contain special units that could require a minimum clock. The DCMs of the Virtex II are such an example. But when you do not need them, it's no matter at all... Regards, Mario ###### From: Allan Herriman Newsgroups: comp.arch.fpga Subject: Re: FPGA minimum operating frequencies Date: Tue, 26 Aug 2003 19:03:59 +1000 Organization: Global Crossing Internet Lines: 23 Message-ID: <3f4b22df@dnews.tpgi.com.au> References: <587c2bd7.0308252221.18186863@posting.google.com> NNTP-Posting-Host: nnrp1.phx1.gblx.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: node21.cwnet.roc.gblx.net 1061888741 21154 64.214.31.40 (26 Aug 2003 09:05:41 GMT) X-Complaints-To: abuse@gblx.net NNTP-Posting-Date: Tue, 26 Aug 2003 09:05:41 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.4) Gecko/20030624 X-Accept-Language: en-us, en In-Reply-To: <587c2bd7.0308252221.18186863@posting.google.com> X-Original-NNTP-Posting-Host: 203.219.10.94 X-Original-Trace: 26 Aug 2003 19:05:35 +1000, 203.219.10.94 Cache-Post-Path: nnrp1.phx1.gblx.net!203.12.160.33 X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!diablo.theplanet.net!mephistopheles.news.clara.net!news.clara.net!news-out1.nntp.be!propagator2-sterling!In.nntp.be!news-out.visi.com!petbe.visi.com!nntp1.roc.gblx.net!nntp.gblx.net!nntp.gblx.net!news.globalcrossing.net!dnews.tpgi.com.au!tpg.com.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32206 Nitin Chandrachoodan wrote: > Hello, > > I was wondering if there were any *lower* limits on the clock > frequency that can be used to clock FPGAs (in particular the Xilinx > Virtex II : XC2V3000). I know there are certain kinds of high speed > logic families using precharge-discharge operation, where the leakage > sets a lower limit on operating speed. Is there such a limit for these > FPGAs, and if so, what is it (ballpark figures are fine). Most of the internal logic is (or gives the appearance of being) static. The DLLs and PLLs are an obvious exception. As long as you don't use a DLL or PLL, you can quite happily clock your logic all the way down to 0Hz. I do recall that one of the older families (Xilinx 4000e?) had a maximum active time for one of the strobes on a CLB ram, which would limit the lowest operating frequency. I think that might have been a bug, and it has been fixed in more modern parts. Regards, Allan. ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: FPGA minimum operating frequencies Date: Tue, 26 Aug 2003 08:06:32 -0700 Organization: Xilinx, Inc. Lines: 25 Message-ID: <3F4B7778.A0B80C05@xilinx.com> References: <587c2bd7.0308252221.18186863@posting.google.com> NNTP-Posting-Host: 149.199.54.205 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.79 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.media.kyoto-u.ac.jp!ctu-gate!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32225 All, Good answers, and they are correct. All static, no precharge tricks. You can go to 1 milli-hertz if you like. Austin Nitin Chandrachoodan wrote: > Hello, > > I was wondering if there were any *lower* limits on the clock > frequency that can be used to clock FPGAs (in particular the Xilinx > Virtex II : XC2V3000). I know there are certain kinds of high speed > logic families using precharge-discharge operation, where the leakage > sets a lower limit on operating speed. Is there such a limit for these > FPGAs, and if so, what is it (ballpark figures are fine). > > Thanks, > > Nitin ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: FPGA minimum operating frequencies Date: Tue, 26 Aug 2003 08:51:53 -0700 Organization: Xilinx,Inc Lines: 23 Message-ID: <3F4B8218.B4687128@xilinx.com> References: <587c2bd7.0308252221.18186863@posting.google.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Nitin Chandrachoodan Path: chonsp.franklin.ch!pfaff2.ethz.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.media.kyoto-u.ac.jp!ctu-gate!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:32224 Xilinx FPGAs have no minimum limit on the clock frequency. I just finished a design where a section is clocked at 2 Hz. But you cannot use the DCM at low frequencies, 24 MHz is the limit. (In synthesis mode you can drive the DCM at a lower frequency, but must still come out with >24 MHz) All flip-flops and all global clocks work fine down to dc. Peter Alfke, Xilinx =========== Nitin Chandrachoodan wrote: > > Hello, > > I was wondering if there were any *lower* limits on the clock > frequency that can be used to clock FPGAs (in particular the Xilinx > Virtex II : XC2V3000). I know there are certain kinds of high speed > logic families using precharge-discharge operation, where the leakage > sets a lower limit on operating speed. Is there such a limit for these > FPGAs, and if so, what is it (ballpark figures are fine). > > Thanks, > > Nitin