From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: 'Virtual Grounds' Date: Mon, 04 Aug 2003 07:41:43 -0700 Organization: Xilinx, Inc. Lines: 37 Message-ID: <3F2E70A7.61609D47@xilinx.com> References: <5V_Wa.31676$Mc.2501134@newsread1.prod.itd.earthlink.net> NNTP-Posting-Host: 149.199.54.205 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.79 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!hammer.uoregon.edu!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:31508 cfk, Not "all", just one extra per Vcco power/ground pin pair is all that is required to reduce ground bounce by another 20% (roughly). The IO is set to a strong standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'. The pin is connected to the ground plane just like a ground pin. Adding pins past the first leads to a very small improvement (not worth it). Making these grounds adjacent to clock inputs, or Vref pins can also aid in the reduction of user pcb crosstalk. The packages already have 3X spacing for every Vref, which means that x-talk coupling to/from Vref pins is 1/9 that of the coupling to any other pin in the package (ie, the package is not the 'problem'). Austin cfk wrote: > And just to add a little spice to that broth, it was suggested one of the > local Xilinx support folks on our last design to ground all the unused IOB > pins and create more of a "virtual ground" (their term, not mine). > > "William LenihanIii" wrote in message > news:5V_Wa.31676$Mc.2501134@newsread1.prod.itd.earthlink.net... > > We will be designing with a large (xc2v6000) Virtex-II part in a ball-grid > > array package that has maybe ~1000 balls, but we are using fairly few > (~250) > > "mission logic" I/O. Add in power & ground, configuration, etc., we will > > have 100's of general-purpose I/O balls that are not needed. > > > > What should we do with them? Ground them? Let them float? If we can let > them > > float, do we even need a solder pad on the PWB for them to "land on"? > > > > ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: 'Virtual Grounds' Date: Tue, 05 Aug 2003 03:51:33 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <5V_Wa.31676$Mc.2501134@newsread1.prod.itd.earthlink.net> <3F2E70A7.61609D47@xilinx.com> X-Complaints-To: abuse@supernews.com Lines: 14 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:31555 >Not "all", just one extra per Vcco power/ground pin pair is all that is required >to reduce ground bounce by another 20% (roughly). The IO is set to a strong >standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'. The pin is >connected to the ground plane just like a ground pin. Adding pins past the >first leads to a very small improvement (not worth it). Does it do any good to use a similar setup for power? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: 'Virtual Grounds' Date: Tue, 05 Aug 2003 07:38:10 -0700 Organization: Xilinx, Inc. Lines: 32 Message-ID: <3F2FC152.6F3FC377@xilinx.com> References: <5V_Wa.31676$Mc.2501134@newsread1.prod.itd.earthlink.net> <3F2E70A7.61609D47@xilinx.com> NNTP-Posting-Host: 149.199.54.205 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.79 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:31516 Hal, Vcc bounce is hardly an issue with most designs. That is why it is not often considered. Ground bounce affects everything: slicing level, jitter, timing, function of the device (etc). Vcc bounce my affect IO output timing, jitter, but is generally a second order effect. You can use "virtual Vcco" pins as well, but it is rare that it is done (and ends up being useful). Austin Hal Murray wrote: > >Not "all", just one extra per Vcco power/ground pin pair is all that is required > >to reduce ground bounce by another 20% (roughly). The IO is set to a strong > >standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'. The pin is > >connected to the ground plane just like a ground pin. Adding pins past the > >first leads to a very small improvement (not worth it). > > Does it do any good to use a similar setup for power? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: 'Virtual Grounds' Date: Wed, 06 Aug 2003 06:22:00 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <5V_Wa.31676$Mc.2501134@newsread1.prod.itd.earthlink.net> <3F2E70A7.61609D47@xilinx.com> <3F2FC152.6F3FC377@xilinx.com> X-Complaints-To: abuse@supernews.com Lines: 27 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!sjc70.webusenet.com!news.webusenet.com!pd2nf1so.cg.shawcable.net!residential.shaw.ca!sn-xit-03!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:31610 >Vcc bounce is hardly an issue with most designs. That is why it is not often >considered. >Ground bounce affects everything: slicing level, jitter, timing, function of the >device (etc). >Vcc bounce my affect IO output timing, jitter, but is generally a second order >effect. Thanks. Why the asymmetry? I'd expect TTL type inputs (referenced to 2 diodes above ground) to be sensitive to ground bounce only, but what about others? I thought the reference for CMOS was roughly 1/2 way between Vcc and Ground. Wouldn't that wiggle if Vcc wiggled? Is PECL referenced to Vcc? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### Message-ID: <3F30A99E.230C@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: 'Virtual Grounds' References: <5V_Wa.31676$Mc.2501134@newsread1.prod.itd.earthlink.net> <3F2E70A7.61609D47@xilinx.com> <3F2FC152.6F3FC377@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 39 Date: Wed, 06 Aug 2003 19:09:18 +1200 NNTP-Posting-Host: 210.246.3.198 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1060153758 210.246.3.198 (Wed, 06 Aug 2003 19:09:18 NZST) NNTP-Posting-Date: Wed, 06 Aug 2003 19:09:18 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!enews.sgi.com!news-out.superfeed.net!propagator2-maxim!news-in-maxim.spamkiller.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:31599 Hal Murray wrote: > > >Vcc bounce is hardly an issue with most designs. That is why it is not often > >considered. > > >Ground bounce affects everything: slicing level, jitter, timing, function of the > >device (etc). > > >Vcc bounce my affect IO output timing, jitter, but is generally a second order > >effect. > > Thanks. > > Why the asymmetry? > > I'd expect TTL type inputs (referenced to 2 diodes above ground) to be > sensitive to ground bounce only, but what about others? > > I thought the reference for CMOS was roughly 1/2 way between Vcc and > Ground. Wouldn't that wiggle if Vcc wiggled? Yes. What separates the issue on FPGA and bigger CPLD, is the core Vcc is not the same pins as Vcc[io] - whilst bounce on the common GND can disturb the core (where it is certainly noticed :) Vcc[io] bounce WILL disturb the IO threshold, but most digital signals pass thru the threshold very quickly. In a jitter paranoid application, you could expect to notice Vcc related crosstalk. > Is PECL referenced to Vcc? Outputs are emitter followers on open collectors, so yes. PECL is normally differential, so you get PSR that way, plus you also reduce any spikes, due to the balance drive. - jg