From: "t hicks" Newsgroups: comp.arch.embedded,comp.arch.fpga Subject: edge card connectors and high speed design Date: Sat, 12 Jul 2003 22:45:12 -0400 Organization: Michigan State University Lines: 29 Message-ID: NNTP-Posting-Host: pm651-18.dialip.mich.net X-AUTHid: hicksthe X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4910.0300 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!cyclone.bc.net!logbridge.uoregon.edu!msunews!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30709 Hi, I am in the process of doing a re-design on a multi-board system that I have working right now. We are redesigning to convert to USB2.0 and to add some features. The system is a low noise data acquistion system using a pulse width modulator to control the sensor. The current generation unit uses a ribbon cable with alternating signal/ground connections for the backplane and the clock is being distributed as a LVPECL differential signal using two 50 ohm coaxes and MCX connectors. I am being pushed to go to an edge card connector to use for power, logic signal and clock distribution (200 MHz clock). The connectors would be put on a real backplane. I should note that the bus has as many as 18 daughter cards and 1 master card. Some of the logic signals are bi-directional (tri-state drivers from a spartan2e FPGA). My concerns are two-fold. First is can the clock be distributed adequately over an edge card (for example something like an AGP connector). Second, can I get the bus working correctly for the data stuff. Note: the bus uses standard lvttl (3.3v) for logic signals at a minimum pulse width of about 40 ns. I am quite concerned that I not get into any signal integrity issues. I tried to do something like this earlier and had some problems. One concern is that the data strobe could ring and generate a false data write condition. Does anyone have any experience with this sort of thing? Especially with getting edge card connectors with a known characteristic impedance? The bus has a total of 19 connectors spaced at about .75" apart. Some of the connectors could be left open and also there will be a sort stub on the individual cards that must be terminated in some fashion. Thanks, Theron Hicks ###### From: "Norm Dresner" Newsgroups: comp.arch.embedded,comp.arch.fpga References: Subject: Re: edge card connectors and high speed design Lines: 22 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Message-ID: <8a7Qa.52586$3o3.3515323@bgtnsc05-news.ops.worldnet.att.net> Date: Sun, 13 Jul 2003 06:41:08 GMT NNTP-Posting-Host: 12.91.173.238 X-Complaints-To: abuse@worldnet.att.net X-Trace: bgtnsc05-news.ops.worldnet.att.net 1058078468 12.91.173.238 (Sun, 13 Jul 2003 06:41:08 GMT) NNTP-Posting-Date: Sun, 13 Jul 2003 06:41:08 GMT Organization: AT&T Worldnet Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-out1.nntp.be!propagator2-sterling!news-in-sterling.nuthinbutnews.com!cyclone1.gnilink.net!wn12feed!worldnet.att.net!bgtnsc05-news.ops.worldnet.att.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30707 "t hicks" wrote in message news:beqgl8$8m8$1@msunews.cl.msu.edu... > Hi, > I am in the process of doing a re-design on a multi-board system that I > have working right now. We are redesigning to convert to USB2.0 and to add [SNIP] > Thanks, > Theron Hicks Just some anecdotal evidence. We had a fairly simple multi-card PCI setup where we had to use very short line-lengths to an on-card PCI bridge for each card because the signals with simple daughter cards were unusable. Known impedance and proper termination is critical even at the PCI's 33/66 MHz. 200 MHz would be many times worse. Norm ###### From: Peter Wallace Newsgroups: comp.arch.fpga Subject: Re: edge card connectors and high speed design Date: Sun, 13 Jul 2003 08:28:40 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: User-Agent: Pan/0.11.4 (Unix) Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: "t hicks" X-Complaints-To: abuse@supernews.com Lines: 39 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-04!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30712 On Sat, 12 Jul 2003 20:45:12 -0700, t hicks wrote: > Hi, > I am in the process of doing a re-design on a multi-board system > that I > have working right now. We are redesigning to convert to USB2.0 and to > add some features. The system is a low noise data acquistion system > using a pulse width modulator to control the sensor. The current > generation unit uses a ribbon cable with alternating signal/ground > connections for the backplane and the clock is being distributed as a > LVPECL differential signal using two 50 ohm coaxes and MCX connectors. I > am being pushed to go to an edge card connector to use for power, logic > signal and clock distribution (200 MHz clock). The connectors would be > put on a real backplane. I should note that the bus has as many as 18 > daughter cards and 1 master card. Some of the logic signals are > bi-directional (tri-state drivers from a spartan2e FPGA). My concerns > are two-fold. First is can the clock be distributed adequately over an > edge card (for example something like an AGP connector). Second, can I > get the bus working correctly for the data stuff. Note: the bus uses > standard lvttl (3.3v) for logic signals at a minimum pulse width of > about 40 ns. I am quite concerned that I not get into any signal > integrity issues. I tried to do something like this earlier and had > some problems. One concern is that the data strobe could ring and > generate a false data write condition. Does anyone have any experience > with this sort of thing? Especially with getting edge card connectors > with a known characteristic impedance? The bus has a total of 19 > connectors spaced at about .75" apart. Some of the connectors could be > left open and also there will be a sort stub on the individual cards > that must be terminated in some fashion. > > Thanks, > Theron Hicks You will probably have to have one 200MHz clock line per card to have any thing like controlled impedance in the clock distribution net.... PCW ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.embedded,comp.arch.fpga Subject: Re: edge card connectors and high speed design Date: Wed, 16 Jul 2003 08:47:44 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: X-Complaints-To: abuse@supernews.com Lines: 34 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!proxad.net!freenix!sn-xit-02!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:30829 >Second, can I get the bus working correctly for the data stuff. Note: the >bus uses standard lvttl (3.3v) for logic signals at a minimum pulse width of >about 40 ns. As a straw man, consider PCI. It runs a bit faster than 40 ns, but it doesn't get anywhere near 18 slots. > The bus has a total of 19 connectors spaced at about .75" apart. > Some of the connectors could be left open and also there will be a sort stub > on the individual cards that must be terminated in some fashion. Usual practice with multidrop back plane busses is to make that stub as short as possible and live with it. (no termination) It screws things up, generally by looking like a small cap which reduces the effective impedance of the backplane. (Same math as a row of memory chips on a bus.) Sometimes with things like this, you can gain a factor of 2 by putting the master card in the middle and splitting the bus into two. Or you split it into 4 and interlace the cards on each side. One thing to consider is putting terminators at each end of the backplane and using something other than LVTTL. I expect you will be doing lots of simulations. Please let us know what you decide to build and/or how well it works. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.