From: Jon Elson Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Fri, 11 Jul 2003 14:49:27 -0500 Organization: Washington University Lines: 66 Message-ID: <3F0F14C7.1030303@artsci.wustl.edu> References: NNTP-Posting-Host: 128.252.127.204 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: newsreader.wustl.edu 1057957228 20215 128.252.127.204 (11 Jul 2003 21:00:28 GMT) X-Complaints-To: usenet@newsreader.wustl.edu NNTP-Posting-Date: Fri, 11 Jul 2003 21:00:28 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-us, en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!skynet.be!skynet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-out1.nntp.be!propagator2-sterling!In.nntp.be!gumby.it.wmich.edu!newsreader.wustl.edu!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30697 ..:: Gabster ::.. wrote: >Hi, > >I'm made many 2-layer PCB's in the past years, but I'm about to start the >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx >Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply >regulators, an oscillator block, a PROM and a logic IC. > >In addition to other literature, I read the following document: >http://www.xilinx.com/xapp/xapp623.pdf >but it is rather complicated and not straight foward for a rookie like me in >FPGA design! So here's a few direct questions: > >1) 4-layer, why is it so important? > > It allows you to have wide power and ground planes, which drastically reduces inductance. I have successfully made some boards with 5 V Spartan FPGAs with just 2 layers, but I had to pay a lot of attention to providing wide ground and power nets in a manner that was likely to keep impedance low. Having layers dedicated to power and ground frees up routing area for the signal traces. >2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or >TOP/POWER/GND/BOTTOM), why? > > For lowest power impedance, either of these are fine. For best shielding, power/signal1/signal2/ground is used in a lot of mil-spec gear. >3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF per >power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is >that accurate? Should I do more? What should I avoid? > > That is most likely fine. Especially if Xilinx recommends that, it should be OK. >4) What is the concept surrounding islands on the power plane? What should >that plane look like? What should I avoid? What the hell about it, this >plane is a mystery for me!!! > > Well, you need to carve the power plane regions based on the geometry of the power pins on each net. If you can get it so that a net is a simple rectangle, that's nice, but it often comes out as a very convoluted region. There isn't much you can do about it in some cases. But, it is best to avoid having one net made up of lots of thin fingers, as that raises impedance. Also, (been there, done that) board manufacturers may alter the clearance around holes in the inner layers, causing regions that were connected by ample copper in your Gerber plots to become isolated in the finished board! Not a good situation, then you have to argue whether it is a manufacturing defect or whether your original design violated their manufacturing specs on inner-plane clearance. Jon ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Fri, 11 Jul 2003 17:16:48 -0400 Organization: Arius, Inc Lines: 105 Message-ID: <3F0F2940.9F555623@yahoo.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: UmFuZG9tSVYEGvG98s7DUBzLYg3QnJOEZVI/zCwYr4pXwztcfi5yDoANUtTQrzmN X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 11 Jul 2003 21:17:29 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30700 Power design is one of those things that is full of mysterious incatations and voodoo. That is because even though the science behind it is not hard to understand, it is very difficult to apply and then verify that what you have done works the way you think it will. Basically either your board will work or it won't and you won't have the time to figure out exactly what was wrong. If it fails due to noise you will throw the kitchen sink at it to make sure it works the next time. Not much learning involved there. I think there is a lot that people agree on and much that they don't. Based on everything I have read and my personal experience, your board will not be a tough one to design with quiet power. "..:: Gabster ::.." wrote: > > Hi, > > I'm made many 2-layer PCB's in the past years, but I'm about to start the > desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx > Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply > regulators, an oscillator block, a PROM and a logic IC. I would advise using an isolated region of the ground plane for each switching regulator with a single connection to the rest of the ground plane. They tend to create very large ground currents. Also pay close attention to the design notes for that device. The key to minimizing EMI as well as the voltage spikes is to minimize the area of high current loops. This is a common theme in power supply design and distribution. It may also help to provide an isolated power to the oscillator using a ferrite bead or filter. Many PLLs require this. > In addition to other literature, I read the following document: > http://www.xilinx.com/xapp/xapp623.pdf > but it is rather complicated and not straight foward for a rookie like me in > FPGA design! So here's a few direct questions: I would also recommend that you check with the capacitor manufacturers. I believe AVX has some good notes on this. > 1) 4-layer, why is it so important? The important part is using two layers for the power and ground. This reduces the resistance to nearly zero and provides a well defined impedance for the high frequency noise. The two planes should be very close together (10 mil) to maximize the capacitance and reduce the impedance. > 2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or > TOP/POWER/GND/BOTTOM), why? I have never heard anyone say one is preferred over the other. I would say pick one based on any logistical issues you may have. > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF per > power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is > that accurate? Should I do more? What should I avoid? If you can get a cap on each pin you will be doing fine. The main point is to minimize the total loop area from a power pin, through the cap and back to a ground pin. So more than just lead length, you need to optimize cap placement. > 4) What is the concept surrounding islands on the power plane? What should > that plane look like? What should I avoid? What the hell about it, this > plane is a mystery for me!!! I have heard about the island theory, but never tried it myself. Your board is not going to be a critcal one, so just stick to one large power plane, divided up for each power region of course. If the board is really as simple as you describe above you don't really have any big issues. > In order to avoid asking 1000's other questions, I wonder if someone could > also direct me toward a complete document talking about PCB design > guidelines for PQ package FPGA's. I found that for the BGA packages on > xilinx website, but it didn't help me much. The quad flat packages are inherently more noisy for the chip inside due to the longer leads. So your board design can only do so much. A big help will be to drive your outputs as lightly as possible and as slow as possible. The SpartanIIE's have several variations in drive strength and speed. Also if you are concerned about a lot of outputs switching at the same time, you can try to stagger them a bit. But this is not normally needed except in extreme cases. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Fri, 11 Jul 2003 17:21:39 -0400 Organization: Arius, Inc Lines: 22 Message-ID: <3F0F2A63.C758E3FE@yahoo.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVYnV1eKKjWiHxZ/6YLwpvBRZvUvXkCS6agTYiuKWDbqfHZaaalkF+cR X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 11 Jul 2003 21:22:19 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30696 One other point I would like to make. A lot of people will tell you to use multiple Tantalum caps, including the Xilinx app notes. But Tantalum caps are inherently slow compared to the noise on the board. So you can get away with a single cap anywhere on each power plane it will fit. But 10 uF may be a bit small. I build a board with a 10 uF cap and found that the power line impedance coming to the board created voltage spikes enough to show up in the analog circuits. A larger Tantalum cap on the board would have prevented this. Of course better power conductors solved the problem as well. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "..:: Gabster ::.." Newsgroups: comp.arch.fpga References: <3F0F2A63.C758E3FE@yahoo.com> Subject: Re: Graduation Day: My first 4-layer PCB Lines: 32 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Date: Fri, 11 Jul 2003 17:45:45 -0400 NNTP-Posting-Host: 24.202.119.98 X-Complaints-To: abuse@videotron.ca X-Trace: wagner.videotron.net 1057959942 24.202.119.98 (Fri, 11 Jul 2003 17:45:42 EDT) NNTP-Posting-Date: Fri, 11 Jul 2003 17:45:42 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!sjc70.webusenet.com!news.webusenet.com!wesley.videotron.net!wagner.videotron.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30699 This is really an appropriate reply and I feel confident to start the design of my board. Thanks, this is really appreciated. Gabriel "rickman" wrote in message news:3F0F2A63.C758E3FE@yahoo.com... > One other point I would like to make. A lot of people will tell you to > use multiple Tantalum caps, including the Xilinx app notes. But > Tantalum caps are inherently slow compared to the noise on the board. > So you can get away with a single cap anywhere on each power plane it > will fit. But 10 uF may be a bit small. I build a board with a 10 uF > cap and found that the power line impedance coming to the board created > voltage spikes enough to show up in the analog circuits. A larger > Tantalum cap on the board would have prevented this. Of course better > power conductors solved the problem as well. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Klaus Vestergaard Kragelund" Newsgroups: comp.arch.fpga References: <3F0F2A63.C758E3FE@yahoo.com> Subject: Re: Graduation Day: My first 4-layer PCB Date: Sat, 12 Jul 2003 09:27:40 +0200 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Lines: 38 Message-ID: <3f0fb7bf$0$24657$edfadb0f@dread14.news.tele.dk> Organization: TDC Internet NNTP-Posting-Host: 80.163.211.66 X-Trace: 1057994687 dread14.news.tele.dk 24657 80.163.211.66 X-Complaints-To: abuse@post.tele.dk Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!colt.net!news.tele.dk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30722 "..:: Gabster ::.." wrote in message news:aeGPa.22934$Pe2.782024@wagner.videotron.net... > This is really an appropriate reply and I feel confident to start the design > of my board. > > Thanks, this is really appreciated. > Gabriel > > "rickman" wrote in message > news:3F0F2A63.C758E3FE@yahoo.com... > > One other point I would like to make. A lot of people will tell you to > > use multiple Tantalum caps, including the Xilinx app notes. But > > Tantalum caps are inherently slow compared to the noise on the board. > > So you can get away with a single cap anywhere on each power plane it > > will fit. But 10 uF may be a bit small. I build a board with a 10 uF > > cap and found that the power line impedance coming to the board created > > voltage spikes enough to show up in the analog circuits. A larger > > Tantalum cap on the board would have prevented this. Of course better > > power conductors solved the problem as well. > > > > -- AND if noone mentioned it the most important part is lots of 47nF ceramic caps distributed and centered at the EMI generating components. I don't aggree with the statement that the supplies should be joined in a " star" connection. Thats asking for trouble. If you have a solid power/ground plane with addequate decoupling there is no reason to split the power-plane up. Allthough other rules apply when you are talking microvolt analog circuits and if the board get so big that the ressonace of the powerplanes will kick in. Cheers Klaus ###### From: "Glen Herrmannsfeldt" Newsgroups: comp.arch.fpga References: <3F0F2A63.C758E3FE@yahoo.com> <3f0fb7bf$0$24657$edfadb0f@dread14.news.tele.dk> Subject: Re: Graduation Day: My first 4-layer PCB Lines: 31 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Message-ID: NNTP-Posting-Host: 12.207.204.17 X-Complaints-To: abuse@comcast.net X-Trace: sccrnsc01 1058061802 12.207.204.17 (Sun, 13 Jul 2003 02:03:22 GMT) NNTP-Posting-Date: Sun, 13 Jul 2003 02:03:22 GMT Organization: Comcast Online Date: Sun, 13 Jul 2003 02:03:22 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!nntp.infostrada.it!in.100proofnews.com!in.100proofnews.com!attla2!ip.att.net!attbi_feed3!attbi_feed4!attbi.com!sccrnsc01.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30702 "Klaus Vestergaard Kragelund" wrote in message news:3f0fb7bf$0$24657 (snip) > AND if noone mentioned it the most important part is lots of 47nF ceramic > caps distributed and centered at the EMI generating components. > > I don't aggree with the statement that the supplies should be joined in a " > star" connection. Thats asking for trouble. If you have a solid power/ground > plane with addequate decoupling there is no reason to split the power-plane > up. Allthough other rules apply when you are talking microvolt analog > circuits and if the board get so big that the ressonace of the powerplanes > will kick in. I thought that was because there are multiple power voltages. If you can't afford a separate power plane for each, and I don't believe many do that, then you have to split them up somehow. If you can arrange all the parts for for each voltage together, it should be easier. Then put the regulators near the junction between the different voltage planes. That is what I thought was meant by star pattern. -- glen ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Sun, 13 Jul 2003 04:22:54 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <3F0F2A63.C758E3FE@yahoo.com> <3f0fb7bf$0$24657$edfadb0f@dread14.news.tele.dk> X-Complaints-To: abuse@supernews.com Lines: 17 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!newspeer1-gui.server.ntli.net!ntli.net!sn-xit-02!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:30713 >If you can arrange all the parts for for each voltage together, it should be >easier. Then put the regulators near the junction between the different >voltage planes. I think the star approach comes from the analog guys. The idea is that heavy currents in one section won't add IR drop on the ground traces of another section that is processing low level signals. The cost is another (ground) wire for the low level signal. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: james <> Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Sun, 13 Jul 2003 17:10:55 -0400 Organization: MindSpring Enterprises Lines: 82 Message-ID: References: Reply-To: james@NOSPAM.gate.net NNTP-Posting-Host: 42.20.e2.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Server-Date: 13 Jul 2003 21:09:40 GMT X-Newsreader: Forte Agent 1.92/32.572 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!zen.net.uk!62.24.240.106.MISMATCH!peer2.news.opaltelecom.net!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.news2me.com!elnk-pas-nf2!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!stamper.news.atl.earthlink.net!harp.news.atl.earthlink.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30754 Many of the comments here have been great. I would add this from some thoughts and experience in layout. If the device is not being used near any RF circuitry then the bypass caps are of adequate value. If there is nearby RF circuitry then add either 100pF or 30pF caps. The 100pF is good for VHF frequencies and the 30pF cap is good for UHF. I would change from tant caps to ceramic for the 10uF caps though. Still all the steps used to elliminate EMI suggested are good. A note on the 208 pin package, it is big and it will radiate no matter how careful your bypasses are and board layout. I reccommend that the you do a signal layer, followed by a ground layer, then power, and finally the bottom layer can be mixed but should primarily be signal. The power layer can have multiple voltages on the plane. It is best to keep a 20 to 1 separation between powers. Thus if you are using a 0.062 laminate, you will have between 18 and 22 mils between layers. I then would leave at least 40 mils preferably 80 mils between traces on the different power busses. This will minimize E-fields that fringe off the power runners. I am not a big fan of blind vias as Xilinx shows in their app note. They are expensive and difficult to troubleshoot. Heaven forbid if one is open either. The board is then shot. Avoid them at all costs. Vias to the ground plane and power should be at least two of them per trace. Especially in high current, peak or constant, traces. Good idea in case the PCB fabricator screws up on the plated through holes. Vias through the power and ground planes should have at least 20 mil anular space around the via. More on faster switching lines if possible. One very important thing. Layout power and ground first. Before you route any signal line do power and ground first. They should be as direct from the source to the devices as possible. Avoid power loops. Branch power from the power buss to the components. Also keep all power runners 40 to 80 mils from the edge of the board. Ground plane can extend to about 10 mils to the edge. Signals should not be closer than 20 mils to the edge. some thoughts james On Fri, 11 Jul 2003 15:51:01 -0400, "..:: Gabster ::.." wrote: >Hi, > >I'm made many 2-layer PCB's in the past years, but I'm about to start the >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx >Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply >regulators, an oscillator block, a PROM and a logic IC. > >In addition to other literature, I read the following document: >http://www.xilinx.com/xapp/xapp623.pdf >but it is rather complicated and not straight foward for a rookie like me in >FPGA design! So here's a few direct questions: > >1) 4-layer, why is it so important? > >2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or >TOP/POWER/GND/BOTTOM), why? > >3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF per >power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is >that accurate? Should I do more? What should I avoid? > >4) What is the concept surrounding islands on the power plane? What should >that plane look like? What should I avoid? What the hell about it, this >plane is a mystery for me!!! > >In order to avoid asking 1000's other questions, I wonder if someone could >also direct me toward a complete document talking about PCB design >guidelines for PQ package FPGA's. I found that for the BGA packages on >xilinx website, but it didn't help me much. > >Thanks a lot, >Gabriel > ###### From: james <> Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Sun, 13 Jul 2003 17:52:04 -0400 Organization: MindSpring Enterprises Lines: 31 Message-ID: <85j3hv860hf43vjkc3s2k6fsqgih1v40ap@4ax.com> References: <3F0F2A63.C758E3FE@yahoo.com> <3f0fb7bf$0$24657$edfadb0f@dread14.news.tele.dk> Reply-To: james@NOSPAM.gate.net NNTP-Posting-Host: 42.20.e2.19 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Server-Date: 13 Jul 2003 21:50:48 GMT X-Newsreader: Forte Agent 1.92/32.572 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!newshub.sdsu.edu!elnk-pas-nf2!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!stamper.news.atl.earthlink.net!harp.news.atl.earthlink.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30752 On Sun, 13 Jul 2003 04:22:54 -0000, hmurray@suespammers.org (Hal Murray) wrote: >>If you can arrange all the parts for for each voltage together, it should be >>easier. Then put the regulators near the junction between the different >>voltage planes. > >I think the star approach comes from the analog guys. > >The idea is that heavy currents in one section won't add IR drop >on the ground traces of another section that is processing >low level signals. The cost is another (ground) wire for the >low level signal. ********************************************* To some point yes. Actually more from when digital and RF circuits reside near each other. Clock signals and high and medium speed switching lines generate harmonics well into the VHF region. Add any loops in the signal or power runners along with distributed capacitances can form a resonace that will reradiate undesired signals to the RF circuits. There are also harmonics that are conducted on power and signal lines common to both digital and RF circuits. Conducted harmonics are easier to minimize than radiation from traces. Radiation from the ICs themselves can really only be minimized by reduced package size. Chip on board/glass is by far the best to minimize IC radiation. Costly as it requires fine pitch runners, 3 mil or less runner widths and spacing. Also requires that IC fabrication to be compatable to direct chip placement. james ###### From: "t hicks" Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Sun, 13 Jul 2003 22:53:46 -0400 Organization: Michigan State University Lines: 115 Message-ID: References: NNTP-Posting-Host: pm839-41.dialip.mich.net X-AUTHid: hicksthe X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4910.0300 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!msunews!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30737 James, Some good points, however I will disagree on two issues. First, I personally do my power routing last on multilayer boards. I expect that I will need to shove some traces slightly in order to get them in. However, for me this gets better overall routing with very short traces to power pads. The one exception to this is in FPGA designs where I do carefully route the FPGA supplies first. Even then I expect that I will need to do some substantial re-routing to finally get all the signals in. Also, I detest high value ceramics. From painful experiences with strange leakage behavior (such as behaving like a low voltage zener) I am now avoiding them like the plague. Of course, these are only my personal experiences. The routing, I am sure is puerly a matter of personal preference. I know that many people use large value ceramics with no problems, so consider that to be just a warning. If you see the same issues, then you usually can get away with mounting a small tantalum on a large (1206 size or bigger) ceramic as long as the voltage is very low. By the way, I use many more bulk capacitors that the norm as I have had problems with noise showing up in the low noise analog parts of my system. On a spartan2e, I am using 8 0.1uf ceramics and 8 10uf 4v tantalums per supply (1 pair {tant and ceramic} per bank per supply) . And before you ask... Is that _really_ necessary? Yes, it does seem to show up in the final system noise behavior. Thanks, Theron wrote in message news:cog3hv8kgkapng9q83fr24h9n7nqtgiud3@4ax.com... > Many of the comments here have been great. > > I would add this from some thoughts and experience in layout. > > If the device is not being used near any RF circuitry then the bypass > caps are of adequate value. If there is nearby RF circuitry then add > either 100pF or 30pF caps. The 100pF is good for VHF frequencies and > the 30pF cap is good for UHF. I would change from tant caps to ceramic > for the 10uF caps though. > > Still all the steps used to elliminate EMI suggested are good. A note > on the 208 pin package, it is big and it will radiate no matter how > careful your bypasses are and board layout. > > I reccommend that the you do a signal layer, followed by a ground > layer, then power, and finally the bottom layer can be mixed but > should primarily be signal. The power layer can have multiple voltages > on the plane. It is best to keep a 20 to 1 separation between powers. > Thus if you are using a 0.062 laminate, you will have between 18 and > 22 mils between layers. I then would leave at least 40 mils preferably > 80 mils between traces on the different power busses. This will > minimize E-fields that fringe off the power runners. > > I am not a big fan of blind vias as Xilinx shows in their app note. > They are expensive and difficult to troubleshoot. Heaven forbid if one > is open either. The board is then shot. Avoid them at all costs. > > Vias to the ground plane and power should be at least two of them per > trace. Especially in high current, peak or constant, traces. Good idea > in case the PCB fabricator screws up on the plated through holes. Vias > through the power and ground planes should have at least 20 mil anular > space around the via. More on faster switching lines if possible. > > One very important thing. Layout power and ground first. Before you > route any signal line do power and ground first. They should be as > direct from the source to the devices as possible. Avoid power loops. > Branch power from the power buss to the components. Also keep all > power runners 40 to 80 mils from the edge of the board. Ground plane > can extend to about 10 mils to the edge. Signals should not be closer > than 20 mils to the edge. > > some thoughts > > james > > On Fri, 11 Jul 2003 15:51:01 -0400, "..:: Gabster ::.." > wrote: > > >Hi, > > > >I'm made many 2-layer PCB's in the past years, but I'm about to start the > >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx > >Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply > >regulators, an oscillator block, a PROM and a logic IC. > > > >In addition to other literature, I read the following document: > >http://www.xilinx.com/xapp/xapp623.pdf > >but it is rather complicated and not straight foward for a rookie like me in > >FPGA design! So here's a few direct questions: > > > >1) 4-layer, why is it so important? > > > >2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or > >TOP/POWER/GND/BOTTOM), why? > > > >3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF per > >power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is > >that accurate? Should I do more? What should I avoid? > > > >4) What is the concept surrounding islands on the power plane? What should > >that plane look like? What should I avoid? What the hell about it, this > >plane is a mystery for me!!! > > > >In order to avoid asking 1000's other questions, I wonder if someone could > >also direct me toward a complete document talking about PCB design > >guidelines for PQ package FPGA's. I found that for the BGA packages on > >xilinx website, but it didn't help me much. > > > >Thanks a lot, > >Gabriel > > > ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Mon, 14 Jul 2003 03:00:03 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: X-Complaints-To: abuse@supernews.com Lines: 13 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!teaser.fr!freenix!sn-xit-02!sn-xit-04!sn-xit-06!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:30743 > Also, I detest high value ceramics. From painful experiences with >strange leakage behavior (such as behaving like a low voltage zener) I am >now avoiding them like the plague. Seems strange. Was it just one cap, or one batch? Lots of people are using them because they have better ESR than tantalum for the same value. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: yuhaiwen@hotmail.com (Jay) Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: 13 Jul 2003 21:15:28 -0700 Organization: http://groups.google.com/ Lines: 13 Message-ID: <4c1bc2c3.0307132015.12754bad@posting.google.com> References: NNTP-Posting-Host: 61.171.15.149 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1058156128 30663 127.0.0.1 (14 Jul 2003 04:15:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 14 Jul 2003 04:15:28 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30753 "..:: Gabster ::.." wrote in message news:... > Hi, > > In order to avoid asking 1000's other questions, I wonder if someone could > also direct me toward a complete document talking about PCB design > guidelines for PQ package FPGA's. I found that for the BGA packages on > xilinx website, but it didn't help me much. > > Thanks a lot, > Gabriel AN-75 from Altera: "High-speed Board Designs" just FYI ###### From: news@sulimma.de (Kolja Sulimma) Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: 14 Jul 2003 12:22:14 -0700 Organization: http://groups.google.com/ Lines: 14 Message-ID: References: NNTP-Posting-Host: 213.23.219.211 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1058210534 22453 127.0.0.1 (14 Jul 2003 19:22:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 14 Jul 2003 19:22:14 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30794 hmurray@suespammers.org (Hal Murray) wrote in message news:... > > Also, I detest high value ceramics. From painful experiences with > >strange leakage behavior (such as behaving like a low voltage zener) I am > >now avoiding them like the plague. I made good experiences with large ceramic caps, but one should note that some linear regulators such as the LM1086 need the higher ESR for the large caps to avoid oszillation. Also everyone concerned about high frequency noise shoul read: "High Speed Digital Design - A Handbook of Black Magic". It has been recommended in this newsgroup a couple of times before. Kolja Sulimma ###### From: news@sulimma.de (Kolja Sulimma) Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: 14 Jul 2003 12:22:40 -0700 Organization: http://groups.google.com/ Lines: 14 Message-ID: References: NNTP-Posting-Host: 213.23.219.211 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1058210561 22505 127.0.0.1 (14 Jul 2003 19:22:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 14 Jul 2003 19:22:41 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30798 hmurray@suespammers.org (Hal Murray) wrote in message news:... > > Also, I detest high value ceramics. From painful experiences with > >strange leakage behavior (such as behaving like a low voltage zener) I am > >now avoiding them like the plague. I made good experiences with large ceramic caps, but one should note that some linear regulators such as the LM1086 need the higher ESR for the large caps to avoid oszillation. Also everyone concerned about high frequency noise shoul read: "High Speed Digital Design - A Handbook of Black Magic". It has been recommended in this newsgroup a couple of times before. Kolja Sulimma ###### From: james <> Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Mon, 14 Jul 2003 15:57:45 -0400 Organization: MindSpring Enterprises Lines: 21 Message-ID: References: Reply-To: james@NOSPAM.gate.net NNTP-Posting-Host: 42.20.e2.19 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Server-Date: 14 Jul 2003 19:56:23 GMT X-Newsreader: Forte Agent 1.92/32.572 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!peer01.cox.net!cox.net!elnk-pas-nf1!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!stamper.news.atl.earthlink.net!harp.news.atl.earthlink.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30810 On Mon, 14 Jul 2003 03:00:03 -0000, hmurray@suespammers.org (Hal Murray) wrote: >> Also, I detest high value ceramics. From painful experiences with >>strange leakage behavior (such as behaving like a low voltage zener) I am >>now avoiding them like the plague. > >Seems strange. Was it just one cap, or one batch? Lots of people are >using them because they have better ESR than tantalum for the same value. ********************************************* Ceramics do have their problems. If the case or the terminations have micro cracks then mositure leakage can occur. Also the termination can have dendritic growth if not properly plated or the board properly cleaned of chlorides. Still I prefer them in the 1 to 10 uF range over tants, especially in supply lines to RF circuits. james ###### From: james <> Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Mon, 14 Jul 2003 16:07:55 -0400 Organization: MindSpring Enterprises Lines: 136 Message-ID: References: Reply-To: james@NOSPAM.gate.net NNTP-Posting-Host: 42.20.e2.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Server-Date: 14 Jul 2003 20:06:34 GMT X-Newsreader: Forte Agent 1.92/32.572 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!elk.ncren.net!arclight.uoregon.edu!newshub.sdsu.edu!elnk-nf2-pas!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!stamper.news.atl.earthlink.net!harp.news.atl.earthlink.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30815 My experience comes from layout of small circuit boards for wireless data communications. In this arena the reciever antenna was generally not more than 0.5 inch distance from one to two microcontrollers and memeory chips. So the minimization of any ground and power loops and radiation was a primary concern as they were the high current carrying traces. Even at 1 Mhz internal buss frequency you would be surprised how much noise comes out of an MC68HC11 micro controller. Especially when the receiveing antenna is only half an inch away from the chip. Ceramic chips do have their problems with dendrites if the PCB is not thoroughly cleaned of chlorides. Tantalums can be damaged during drops. They also do not like RF currents either. Then there is ESD spikes! that is another subject to its own. james On Sun, 13 Jul 2003 22:53:46 -0400, "t hicks" wrote: >James, > Some good points, however I will disagree on two issues. First, I >personally do my power routing last on multilayer boards. I expect that I >will need to shove some traces slightly in order to get them in. However, >for me this gets better overall routing with very short traces to power >pads. The one exception to this is in FPGA designs where I do carefully >route the FPGA supplies first. Even then I expect that I will need to do >some substantial re-routing to finally get all the signals in. > Also, I detest high value ceramics. From painful experiences with >strange leakage behavior (such as behaving like a low voltage zener) I am >now avoiding them like the plague. > Of course, these are only my personal experiences. The routing, I am >sure is puerly a matter of personal preference. I know that many people use >large value ceramics with no problems, so consider that to be just a >warning. If you see the same issues, then you usually can get away with >mounting a small tantalum on a large (1206 size or bigger) ceramic as long >as the voltage is very low. By the way, I use many more bulk capacitors >that the norm as I have had problems with noise showing up in the low noise >analog parts of my system. On a spartan2e, I am using 8 0.1uf ceramics and >8 10uf 4v tantalums per supply (1 pair {tant and ceramic} per bank per >supply) . And before you ask... Is that _really_ necessary? Yes, it does >seem to show up in the final system noise behavior. > >Thanks, >Theron > > wrote in message news:cog3hv8kgkapng9q83fr24h9n7nqtgiud3@4ax.com... >> Many of the comments here have been great. >> >> I would add this from some thoughts and experience in layout. >> >> If the device is not being used near any RF circuitry then the bypass >> caps are of adequate value. If there is nearby RF circuitry then add >> either 100pF or 30pF caps. The 100pF is good for VHF frequencies and >> the 30pF cap is good for UHF. I would change from tant caps to ceramic >> for the 10uF caps though. >> >> Still all the steps used to elliminate EMI suggested are good. A note >> on the 208 pin package, it is big and it will radiate no matter how >> careful your bypasses are and board layout. >> >> I reccommend that the you do a signal layer, followed by a ground >> layer, then power, and finally the bottom layer can be mixed but >> should primarily be signal. The power layer can have multiple voltages >> on the plane. It is best to keep a 20 to 1 separation between powers. >> Thus if you are using a 0.062 laminate, you will have between 18 and >> 22 mils between layers. I then would leave at least 40 mils preferably >> 80 mils between traces on the different power busses. This will >> minimize E-fields that fringe off the power runners. >> >> I am not a big fan of blind vias as Xilinx shows in their app note. >> They are expensive and difficult to troubleshoot. Heaven forbid if one >> is open either. The board is then shot. Avoid them at all costs. >> >> Vias to the ground plane and power should be at least two of them per >> trace. Especially in high current, peak or constant, traces. Good idea >> in case the PCB fabricator screws up on the plated through holes. Vias >> through the power and ground planes should have at least 20 mil anular >> space around the via. More on faster switching lines if possible. >> >> One very important thing. Layout power and ground first. Before you >> route any signal line do power and ground first. They should be as >> direct from the source to the devices as possible. Avoid power loops. >> Branch power from the power buss to the components. Also keep all >> power runners 40 to 80 mils from the edge of the board. Ground plane >> can extend to about 10 mils to the edge. Signals should not be closer >> than 20 mils to the edge. >> >> some thoughts >> >> james >> >> On Fri, 11 Jul 2003 15:51:01 -0400, "..:: Gabster ::.." >> wrote: >> >> >Hi, >> > >> >I'm made many 2-layer PCB's in the past years, but I'm about to start the >> >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx >> >Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply >> >regulators, an oscillator block, a PROM and a logic IC. >> > >> >In addition to other literature, I read the following document: >> >http://www.xilinx.com/xapp/xapp623.pdf >> >but it is rather complicated and not straight foward for a rookie like me >in >> >FPGA design! So here's a few direct questions: >> > >> >1) 4-layer, why is it so important? >> > >> >2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or >> >TOP/POWER/GND/BOTTOM), why? >> > >> >3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF >per >> >power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is >> >that accurate? Should I do more? What should I avoid? >> > >> >4) What is the concept surrounding islands on the power plane? What >should >> >that plane look like? What should I avoid? What the hell about it, this >> >plane is a mystery for me!!! >> > >> >In order to avoid asking 1000's other questions, I wonder if someone >could >> >also direct me toward a complete document talking about PCB design >> >guidelines for PQ package FPGA's. I found that for the BGA packages on >> >xilinx website, but it didn't help me much. >> > >> >Thanks a lot, >> >Gabriel >> > >> > ###### From: "t hicks" Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Tue, 15 Jul 2003 22:44:29 -0400 Organization: Michigan State University Lines: 159 Message-ID: References: NNTP-Posting-Host: pm842-38.dialip.mich.net X-AUTHid: hicksthe X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4910.0300 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!msunews!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30826 Can anyone tell me what the effect of dendrites is? I think I know what they are physically, but I wonder what the effect is electrically and over what sort of time frame they develop. Thanks, Theron wrote in message news:pr26hv0eeukppkjos0ehr7nm6un5l8c9oo@4ax.com... > My experience comes from layout of small circuit boards for wireless > data communications. In this arena the reciever antenna was generally > not more than 0.5 inch distance from one to two microcontrollers and > memeory chips. So the minimization of any ground and power loops and > radiation was a primary concern as they were the high current carrying > traces. Even at 1 Mhz internal buss frequency you would be surprised > how much noise comes out of an MC68HC11 micro controller. Especially > when the receiveing antenna is only half an inch away from the chip. > > Ceramic chips do have their problems with dendrites if the PCB is not > thoroughly cleaned of chlorides. Tantalums can be damaged during > drops. They also do not like RF currents either. > > Then there is ESD spikes! that is another subject to its own. > > james > > > On Sun, 13 Jul 2003 22:53:46 -0400, "t hicks" > wrote: > > >James, > > Some good points, however I will disagree on two issues. First, I > >personally do my power routing last on multilayer boards. I expect that I > >will need to shove some traces slightly in order to get them in. However, > >for me this gets better overall routing with very short traces to power > >pads. The one exception to this is in FPGA designs where I do carefully > >route the FPGA supplies first. Even then I expect that I will need to do > >some substantial re-routing to finally get all the signals in. > > Also, I detest high value ceramics. From painful experiences with > >strange leakage behavior (such as behaving like a low voltage zener) I am > >now avoiding them like the plague. > > Of course, these are only my personal experiences. The routing, I am > >sure is puerly a matter of personal preference. I know that many people use > >large value ceramics with no problems, so consider that to be just a > >warning. If you see the same issues, then you usually can get away with > >mounting a small tantalum on a large (1206 size or bigger) ceramic as long > >as the voltage is very low. By the way, I use many more bulk capacitors > >that the norm as I have had problems with noise showing up in the low noise > >analog parts of my system. On a spartan2e, I am using 8 0.1uf ceramics and > >8 10uf 4v tantalums per supply (1 pair {tant and ceramic} per bank per > >supply) . And before you ask... Is that _really_ necessary? Yes, it does > >seem to show up in the final system noise behavior. > > > >Thanks, > >Theron > > > > wrote in message news:cog3hv8kgkapng9q83fr24h9n7nqtgiud3@4ax.com... > >> Many of the comments here have been great. > >> > >> I would add this from some thoughts and experience in layout. > >> > >> If the device is not being used near any RF circuitry then the bypass > >> caps are of adequate value. If there is nearby RF circuitry then add > >> either 100pF or 30pF caps. The 100pF is good for VHF frequencies and > >> the 30pF cap is good for UHF. I would change from tant caps to ceramic > >> for the 10uF caps though. > >> > >> Still all the steps used to elliminate EMI suggested are good. A note > >> on the 208 pin package, it is big and it will radiate no matter how > >> careful your bypasses are and board layout. > >> > >> I reccommend that the you do a signal layer, followed by a ground > >> layer, then power, and finally the bottom layer can be mixed but > >> should primarily be signal. The power layer can have multiple voltages > >> on the plane. It is best to keep a 20 to 1 separation between powers. > >> Thus if you are using a 0.062 laminate, you will have between 18 and > >> 22 mils between layers. I then would leave at least 40 mils preferably > >> 80 mils between traces on the different power busses. This will > >> minimize E-fields that fringe off the power runners. > >> > >> I am not a big fan of blind vias as Xilinx shows in their app note. > >> They are expensive and difficult to troubleshoot. Heaven forbid if one > >> is open either. The board is then shot. Avoid them at all costs. > >> > >> Vias to the ground plane and power should be at least two of them per > >> trace. Especially in high current, peak or constant, traces. Good idea > >> in case the PCB fabricator screws up on the plated through holes. Vias > >> through the power and ground planes should have at least 20 mil anular > >> space around the via. More on faster switching lines if possible. > >> > >> One very important thing. Layout power and ground first. Before you > >> route any signal line do power and ground first. They should be as > >> direct from the source to the devices as possible. Avoid power loops. > >> Branch power from the power buss to the components. Also keep all > >> power runners 40 to 80 mils from the edge of the board. Ground plane > >> can extend to about 10 mils to the edge. Signals should not be closer > >> than 20 mils to the edge. > >> > >> some thoughts > >> > >> james > >> > >> On Fri, 11 Jul 2003 15:51:01 -0400, "..:: Gabster ::.." > >> wrote: > >> > >> >Hi, > >> > > >> >I'm made many 2-layer PCB's in the past years, but I'm about to start the > >> >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx > >> >Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply > >> >regulators, an oscillator block, a PROM and a logic IC. > >> > > >> >In addition to other literature, I read the following document: > >> >http://www.xilinx.com/xapp/xapp623.pdf > >> >but it is rather complicated and not straight foward for a rookie like me > >in > >> >FPGA design! So here's a few direct questions: > >> > > >> >1) 4-layer, why is it so important? > >> > > >> >2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or > >> >TOP/POWER/GND/BOTTOM), why? > >> > > >> >3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF > >per > >> >power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is > >> >that accurate? Should I do more? What should I avoid? > >> > > >> >4) What is the concept surrounding islands on the power plane? What > >should > >> >that plane look like? What should I avoid? What the hell about it, this > >> >plane is a mystery for me!!! > >> > > >> >In order to avoid asking 1000's other questions, I wonder if someone > >could > >> >also direct me toward a complete document talking about PCB design > >> >guidelines for PQ package FPGA's. I found that for the BGA packages on > >> >xilinx website, but it didn't help me much. > >> > > >> >Thanks a lot, > >> >Gabriel > >> > > >> > > > ###### Message-ID: <3F14D330.1070104@mail.com> From: John_H User-Agent: Mozilla/5.0 (Windows; U; Win98; en-US; rv:1.0.2) Gecko/20030208 Netscape/7.02 X-Accept-Language: en-us, en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB References: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 209 Date: Wed, 16 Jul 2003 04:21:37 GMT NNTP-Posting-Host: 4.5.119.89 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc01.gnilink.net 1058329297 4.5.119.89 (Wed, 16 Jul 2003 00:21:37 EDT) NNTP-Posting-Date: Wed, 16 Jul 2003 00:21:37 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-out1.nntp.be!propagator2-sterling!news-in-sterling.nuthinbutnews.com!cyclone1.gnilink.net!spamkiller.gnilink.net!nwrddc01.gnilink.net.POSTED!1ae4b49c!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30846 Dendrites (small migrations of metals or other conductive material) will short out adjacent connections. Exotic materials (like silver without the anti-dendrite palladium) or normal materials under a bias during processing can cause the growth of dendrites. We had a battery for our Real Time Clock that went through the solder wave. The battery was spec'ed for the process, allowing the short duration short circuit. But once through the wave, the battery provided a nice little field between ADJACENT power and ground pins on the RTC chip. Some boards outright didn't come up. Other boards failed over time or were out of spec because the dendrites provided a resistive path rather than a dead short. Fun! t hicks wrote: > Can anyone tell me what the effect of dendrites is? I think I know what > they are physically, but I wonder what the effect is electrically and over > what sort of time frame they develop. > > Thanks, > Theron > > wrote in message news:pr26hv0eeukppkjos0ehr7nm6un5l8c9oo@4ax.com... > >>My experience comes from layout of small circuit boards for wireless >>data communications. In this arena the reciever antenna was generally >>not more than 0.5 inch distance from one to two microcontrollers and >>memeory chips. So the minimization of any ground and power loops and >>radiation was a primary concern as they were the high current carrying >>traces. Even at 1 Mhz internal buss frequency you would be surprised >>how much noise comes out of an MC68HC11 micro controller. Especially >>when the receiveing antenna is only half an inch away from the chip. >> >>Ceramic chips do have their problems with dendrites if the PCB is not >>thoroughly cleaned of chlorides. Tantalums can be damaged during >>drops. They also do not like RF currents either. >> >>Then there is ESD spikes! that is another subject to its own. >> >>james >> >> >>On Sun, 13 Jul 2003 22:53:46 -0400, "t hicks" >>wrote: >> >> >>>James, >>> Some good points, however I will disagree on two issues. First, I >>>personally do my power routing last on multilayer boards. I expect that >> > I > >>>will need to shove some traces slightly in order to get them in. >> > However, > >>>for me this gets better overall routing with very short traces to power >>>pads. The one exception to this is in FPGA designs where I do carefully >>>route the FPGA supplies first. Even then I expect that I will need to do >>>some substantial re-routing to finally get all the signals in. >>> Also, I detest high value ceramics. From painful experiences with >>>strange leakage behavior (such as behaving like a low voltage zener) I am >>>now avoiding them like the plague. >>> Of course, these are only my personal experiences. The routing, I am >>>sure is puerly a matter of personal preference. I know that many people >> > use > >>>large value ceramics with no problems, so consider that to be just a >>>warning. If you see the same issues, then you usually can get away with >>>mounting a small tantalum on a large (1206 size or bigger) ceramic as >> > long > >>>as the voltage is very low. By the way, I use many more bulk capacitors >>>that the norm as I have had problems with noise showing up in the low >> > noise > >>>analog parts of my system. On a spartan2e, I am using 8 0.1uf ceramics >> > and > >>>8 10uf 4v tantalums per supply (1 pair {tant and ceramic} per bank per >>>supply) . And before you ask... Is that _really_ necessary? Yes, it >> > does > >>>seem to show up in the final system noise behavior. >>> >>>Thanks, >>>Theron >>> >>> wrote in message >> > news:cog3hv8kgkapng9q83fr24h9n7nqtgiud3@4ax.com... > >>>>Many of the comments here have been great. >>>> >>>>I would add this from some thoughts and experience in layout. >>>> >>>>If the device is not being used near any RF circuitry then the bypass >>>>caps are of adequate value. If there is nearby RF circuitry then add >>>>either 100pF or 30pF caps. The 100pF is good for VHF frequencies and >>>>the 30pF cap is good for UHF. I would change from tant caps to ceramic >>>>for the 10uF caps though. >>>> >>>>Still all the steps used to elliminate EMI suggested are good. A note >>>>on the 208 pin package, it is big and it will radiate no matter how >>>>careful your bypasses are and board layout. >>>> >>>>I reccommend that the you do a signal layer, followed by a ground >>>>layer, then power, and finally the bottom layer can be mixed but >>>>should primarily be signal. The power layer can have multiple voltages >>>>on the plane. It is best to keep a 20 to 1 separation between powers. >>>>Thus if you are using a 0.062 laminate, you will have between 18 and >>>>22 mils between layers. I then would leave at least 40 mils preferably >>>>80 mils between traces on the different power busses. This will >>>>minimize E-fields that fringe off the power runners. >>>> >>>>I am not a big fan of blind vias as Xilinx shows in their app note. >>>>They are expensive and difficult to troubleshoot. Heaven forbid if one >>>>is open either. The board is then shot. Avoid them at all costs. >>>> >>>>Vias to the ground plane and power should be at least two of them per >>>>trace. Especially in high current, peak or constant, traces. Good idea >>>>in case the PCB fabricator screws up on the plated through holes. Vias >>>>through the power and ground planes should have at least 20 mil anular >>>>space around the via. More on faster switching lines if possible. >>>> >>>>One very important thing. Layout power and ground first. Before you >>>>route any signal line do power and ground first. They should be as >>>>direct from the source to the devices as possible. Avoid power loops. >>>>Branch power from the power buss to the components. Also keep all >>>>power runners 40 to 80 mils from the edge of the board. Ground plane >>>>can extend to about 10 mils to the edge. Signals should not be closer >>>>than 20 mils to the edge. >>>> >>>>some thoughts >>>> >>>>james >>>> >>>>On Fri, 11 Jul 2003 15:51:01 -0400, "..:: Gabster ::.." >>>> wrote: >>>> >>>> >>>>>Hi, >>>>> >>>>>I'm made many 2-layer PCB's in the past years, but I'm about to start >>>> > the > >>>>>desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx >>>>>Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power >>>> > supply > >>>>>regulators, an oscillator block, a PROM and a logic IC. >>>>> >>>>>In addition to other literature, I read the following document: >>>>>http://www.xilinx.com/xapp/xapp623.pdf >>>>>but it is rather complicated and not straight foward for a rookie like >>>> > me > >>>in >>> >>>>>FPGA design! So here's a few direct questions: >>>>> >>>>>1) 4-layer, why is it so important? >>>>> >>>>>2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or >>>>>TOP/POWER/GND/BOTTOM), why? >>>>> >>>>>3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF >>>> >>>per >>> >>>>>power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). >>>> > Is > >>>>>that accurate? Should I do more? What should I avoid? >>>>> >>>>>4) What is the concept surrounding islands on the power plane? What >>>> >>>should >>> >>>>>that plane look like? What should I avoid? What the hell about it, >>>> > this > >>>>>plane is a mystery for me!!! >>>>> >>>>>In order to avoid asking 1000's other questions, I wonder if someone >>>> >>>could >>> >>>>>also direct me toward a complete document talking about PCB design >>>>>guidelines for PQ package FPGA's. I found that for the BGA packages on >>>>>xilinx website, but it didn't help me much. >>>>> >>>>>Thanks a lot, >>>>>Gabriel >>>>> >>>> > > ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Wed, 16 Jul 2003 10:05:34 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: X-Complaints-To: abuse@supernews.com Lines: 85 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!proxad.net!freenix!sn-xit-02!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:30828 >I'm made many 2-layer PCB's in the past years, but I'm about to start the >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx >Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply >regulators, an oscillator block, a PROM and a logic IC. I'll start by repeating Kolja's suggestion to get a copy of "High Speed Digital Design - A Handbook of Black Magic". Johnson and Graham. List is $95. It won't solve this problem directly, but it will give you the background you need to think about this area. It's also fun reading. Every time I go to look something up I get sucked into rereading some other section. It's got the right level of math for me. The formulas are there if I ever need them, but it's got enough rules of thumb that I can (mostly) avoid the formulas. One thing to keep in mind is that your 12 MHz isn't the critical parameter, it's the edge rate on the signals. You want to run the edges as slow/gentle as you can. Set the IOBs to low drive current and such. If I was working on a board like this, I'd start by asking how I was going to get the power to the FPGA. Multiple power supplies are a lot simpler if you have a plane per power rail and another for ground. Since you only have 2 layers for power planes, you are off by 2 from the simple case. I'm assuming that you can place the other parts so that the general layout is (say) 2.5 V parts on the left and 3.3 V parts on the right. If so, then you can "split" the power plane down the middle with a "cut" in the copper and get two planes on one layer. Note that you have to think about any signals that cross that cut. The mirror currents have to get from one side of the split to the other. They can't jump across the cut. (General idea is "don't do that".) That cut might run down the middle of the FPGA. That (hopefully) saves one plane, but you still have one to go. Is the routing on your board going to be "nice"? At least around the FPGA? Can you basically run most of the signals directly from the pads on the top layer over to where they connect? (or do you have all sorts of signals crossing and tripping over eachother?) If the routing is clean, then the top layer under the chip isn't needed for routing. I'd put a small plane in there for the core voltage. It gets low inductance connections to all the core pins. Then I'd put bypass caps on the bottom, under the chip, inside the pads. Again, that assumes that space isn't needed for routing. That's where they can get good connections to both the core "plane" and the ground plane. > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF per > power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is > that accurate? Should I do more? What should I avoid? That's a reasoanable ballpark. Inductance is what you want to avoid. Vias count, so do long traces from pads to vias. > 4) What is the concept surrounding islands on the power plane? What should > that plane look like? What should I avoid? What the hell about it, this > plane is a mystery for me!!! A plane is just a convenient way to get low-inductance. You have to find a way to position the planes and the chips (and bypass caps) so they can connect easily (rather than running long traces way over to there). Don't forget remote sense on the power regulator. How much IR drop will you have between the regulator on the far corner of the board and the chip where the power gets used? (Planes are low resistance too.) This is especially important for the core voltage to the FPGA if you don't have a plane to dedicate to it. Might be OK if you can make the feeder trace fat enough. Just another thing for the checklist. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: "..:: Gabster ::.." Newsgroups: comp.arch.fpga References: Subject: Re: Graduation Day: My first 4-layer PCB Lines: 100 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: <5ngRa.62131$O55.1075768@wagner.videotron.net> Date: Wed, 16 Jul 2003 13:58:25 -0400 NNTP-Posting-Host: 24.202.119.98 X-Complaints-To: abuse@videotron.ca X-Trace: wagner.videotron.net 1058378305 24.202.119.98 (Wed, 16 Jul 2003 13:58:25 EDT) NNTP-Posting-Date: Wed, 16 Jul 2003 13:58:25 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!sjc70.webusenet.com!news.webusenet.com!wesley.videotron.net!wagner.videotron.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30856 It's getting pretty clear how I'll route this board. Thanks to all. I hope other rookies like me will read this post as it is very instructive. Hal, can you tell me more about setting the input/output blocks (IOBs)...this is something unknown to me. "Hal Murray" wrote in message news:vha8reee823o6a@corp.supernews.com... > >I'm made many 2-layer PCB's in the past years, but I'm about to start the > >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx > >Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply > >regulators, an oscillator block, a PROM and a logic IC. > > I'll start by repeating Kolja's suggestion to get a copy of > "High Speed Digital Design - A Handbook of Black Magic". > Johnson and Graham. List is $95. > > It won't solve this problem directly, but it will give you > the background you need to think about this area. It's also > fun reading. Every time I go to look something up I get sucked > into rereading some other section. It's got the right level > of math for me. The formulas are there if I ever need them, > but it's got enough rules of thumb that I can (mostly) avoid > the formulas. > > One thing to keep in mind is that your 12 MHz isn't the > critical parameter, it's the edge rate on the signals. You > want to run the edges as slow/gentle as you can. Set the > IOBs to low drive current and such. > > > If I was working on a board like this, I'd start by asking > how I was going to get the power to the FPGA. > > Multiple power supplies are a lot simpler if you have a plane > per power rail and another for ground. Since you only have 2 layers > for power planes, you are off by 2 from the simple case. > > I'm assuming that you can place the other parts so that the general > layout is (say) 2.5 V parts on the left and 3.3 V parts on the right. > If so, then you can "split" the power plane down the middle with a "cut" > in the copper and get two planes on one layer. Note that you have to > think about any signals that cross that cut. The mirror currents have > to get from one side of the split to the other. They can't jump > across the cut. (General idea is "don't do that".) > > That cut might run down the middle of the FPGA. > > That (hopefully) saves one plane, but you still have one to go. > > Is the routing on your board going to be "nice"? At least around > the FPGA? Can you basically run most of the signals directly from > the pads on the top layer over to where they connect? (or do you > have all sorts of signals crossing and tripping over eachother?) > > If the routing is clean, then the top layer under the chip isn't > needed for routing. I'd put a small plane in there for the core > voltage. It gets low inductance connections to all the core pins. > > Then I'd put bypass caps on the bottom, under the chip, inside > the pads. Again, that assumes that space isn't needed for routing. > That's where they can get good connections to both the core "plane" > and the ground plane. > > > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF per > > power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is > > that accurate? Should I do more? What should I avoid? > > That's a reasoanable ballpark. Inductance is what you want to > avoid. Vias count, so do long traces from pads to vias. > > > 4) What is the concept surrounding islands on the power plane? What should > > that plane look like? What should I avoid? What the hell about it, this > > plane is a mystery for me!!! > > A plane is just a convenient way to get low-inductance. You have to > find a way to position the planes and the chips (and bypass caps) > so they can connect easily (rather than running long traces way > over to there). > > Don't forget remote sense on the power regulator. How much IR drop will > you have between the regulator on the far corner of the board and the > chip where the power gets used? (Planes are low resistance too.) This > is especially important for the core voltage to the FPGA if you don't have > a plane to dedicate to it. Might be OK if you can make the feeder trace > fat enough. Just another thing for the checklist. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. > ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Wed, 16 Jul 2003 18:49:05 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <5ngRa.62131$O55.1075768@wagner.videotron.net> X-Complaints-To: abuse@supernews.com Lines: 14 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!switch.ch!news.tele.dk!news.tele.dk!small.news.tele.dk!sn-xit-02!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:30853 >Hal, can you tell me more about setting the input/output blocks >(IOBs)...this is something unknown to me. Look in the data sheets. The LVTTL option has several sub-options with different drive strengths. Lower current takes longer to charge up external caps (traces and other input pins), but it makes less noise and EMI/SSO problems. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: "Martin Schoeberl" Newsgroups: comp.arch.fpga References: Subject: Re: Graduation Day: My first 4-layer PCB Lines: 22 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2720.3000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2727.1300 Message-ID: Date: Fri, 18 Jul 2003 10:55:32 GMT NNTP-Posting-Host: 80.110.200.231 X-Complaints-To: abuse@news.chello.at X-Trace: news.chello.at 1058525732 80.110.200.231 (Fri, 18 Jul 2003 12:55:32 MEST) NNTP-Posting-Date: Fri, 18 Jul 2003 12:55:32 MEST Organization: Customers chello Austria Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!switch.ch!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!195.34.132.48.MISMATCH!newsfeed01.chello.at!news.chello.at.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30906 > > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF per > > power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is > > that accurate? Should I do more? What should I avoid? > > That's a reasoanable ballpark. Inductance is what you want to > avoid. Vias count, so do long traces from pads to vias. Why is everyone talking about 0.1uF caps? Isn't it time to adjust the cap values to the higher speed of the logic and to avoid EMI problems. A standard 0.1uF cap 0805 with X7R dielectric is at resonance at 10 MHz (see datasheet of Kemel caps)! Above 10 MHz the impedance becomes inductive. EMI is measured up to 1 GHz. Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Fri, 18 Jul 2003 09:36:31 -0400 Organization: Arius, Inc Lines: 44 Message-ID: <3F17F7DF.6263AD2E@yahoo.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: UmFuZG9tSVb3h0ji5HCFJYmRHXyE19fQ9ll+GS2QwC0bJIKaNPZNfBzuj+UwrQ44 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 18 Jul 2003 13:37:18 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!peer01.cox.net!cox.net!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30861 Martin Schoeberl wrote: > > > > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF > per > > > power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). > Is > > > that accurate? Should I do more? What should I avoid? > > > > That's a reasoanable ballpark. Inductance is what you want to > > avoid. Vias count, so do long traces from pads to vias. > > Why is everyone talking about 0.1uF caps? Isn't it time to adjust the cap > values to the higher speed of the logic and to avoid EMI problems. A > standard 0.1uF cap 0805 with X7R dielectric is at resonance at 10 MHz (see > datasheet of Kemel caps)! Above 10 MHz the impedance becomes inductive. EMI > is measured up to 1 GHz. Two points I would make. 1) Whether a cap is inductive or capacitive at a given frequency is of no concern. The only thing that matters is the impedance. The purpose of a cap is to lower the impedance of the power to ground path at the frequencies of your noise. A low impedance inductive path is just as good a coupling the noise to ground as a low impedance capacitive path. 2) If you don't like the Kemel (sp? Kemet perhaps) caps, use someone else's caps that are rated with a higher resonance or a lower impedance. I know that the 0.1 uF caps I use have a resonance above 50 MHz. Perhaps you were looking at a larger package which adversely affects the impedance more than does the cap value? 0.1 uF caps come in 0603 packages which have very good high freq characteristics. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Fri, 18 Jul 2003 15:02:19 +0100 Lines: 13 Message-ID: References: <3F17F7DF.6263AD2E@yahoo.com> NNTP-Posting-Host: tile.demon.co.uk X-Trace: news.demon.co.uk 1058544020 29511 158.152.50.250 (18 Jul 2003 16:00:20 GMT) X-Complaints-To: abuse@demon.net NNTP-Posting-Date: Fri, 18 Jul 2003 16:00:20 +0000 (UTC) X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 X-Priority: 3 X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MSMail-Priority: Normal Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!kibo.news.demon.net!news.demon.co.uk!demon!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30912 rickman wrote: > 0.1 uF caps come > in 0603 packages which have very good high freq characteristics. Choose a low-inductance package and get as many pFs as economically available. Reverse geometry packages are worth looking at. And don't blow it by poor layout on the cap power and ground vias. ###### Message-ID: <3F17FFD7.9040901@mail.com> From: John_H User-Agent: Mozilla/5.0 (Windows; U; Win98; en-US; rv:1.0.2) Gecko/20030208 Netscape/7.02 X-Accept-Language: en-us, en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB References: <3F17F7DF.6263AD2E@yahoo.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Lines: 52 Date: Fri, 18 Jul 2003 14:08:49 GMT NNTP-Posting-Host: 4.5.119.89 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc02.gnilink.net 1058537329 4.5.119.89 (Fri, 18 Jul 2003 10:08:49 EDT) NNTP-Posting-Date: Fri, 18 Jul 2003 10:08:49 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-out1.nntp.be!propagator2-sterling!news-in-sterling.nuthinbutnews.com!cyclone1.gnilink.net!spamkiller.gnilink.net!nwrddc02.gnilink.net.POSTED!1ae4b49c!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30971 rickman wrote: > Two points I would make. > > 1) Whether a cap is inductive or capacitive at a given frequency is of > no concern. The only thing that matters is the impedance. The purpose > of a cap is to lower the impedance of the power to ground path at the > frequencies of your noise. A low impedance inductive path is just as > good a coupling the noise to ground as a low impedance capacitive path. I agree with you an this point, but to a degree.... The Kemet value and package mentioned with the SRF at 10MHz has an impedance of about 0.1 ohm at 10MHz. At 100MHz, the impedance is over 1 ohm. Assuming 12 .1uF caps scattered around an FPGA, if the chip uses a 100MHz clock there will be a ripple on the voltage plane of 83mV per amp of dynamic current. In today's lower foltage/higher current devices, can we accept those levels of voltage noise? It would take 1 or 2 caps with an SRF at 100MHz to provide the same filtering as 12 of those Kemet 0.1uF devices, again at 100MHz. > 2) If you don't like the Kemel (sp? Kemet perhaps) caps, use someone > else's caps that are rated with a higher resonance or a lower > impedance. I know that the 0.1 uF caps I use have a resonance above 50 > MHz. Perhaps you were looking at a larger package which adversely > affects the impedance more than does the cap value? 0.1 uF caps come in > 0603 packages which have very good high freq characteristics. Smaller packages do tend to perform better. It might be nasty working with 0402s, but the SRF can be better. As long as the PC layout isn't compromised (e.g., single vias distant from the mounting pads) better results are obtained. I have seen few designers actually do a comprohensive decoupling analysis. I've mentioned on this board before that the technique of using multiple capacitor values with differing SRFs can provide great benefit. As long as you keep the differences small (SRFs a decade apart for adjacent capacitors with have horrible impedance at one point between those SRFs - imagine what an inductor and capacitor in parallel provide at resonance) and the capacitors are nicely distributed, the total number of capacitors could be reduced to achieve the same impedance across a frequency range of interest. Just one capacitor value will work. EMI will suffer, there will be noise on the voltage planes. Poorly designed combinations of caps (e.g., two values laid out adjacent to each other in pairs aren't distributed enough to avoid the resonance mentioned above) will also provide ugly results but tend to "work." To "adjust the cap values to the higher speed of the logic" by reducing the capacitance alone (to increase the SRF) won't "avoid EMA problems" but will move them. Solid decoupling design will get us there. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: Fri, 18 Jul 2003 12:12:33 -0400 Organization: Arius, Inc Lines: 85 Message-ID: <3F181C71.E989B167@yahoo.com> References: <3F17F7DF.6263AD2E@yahoo.com> <3F17FFD7.9040901@mail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVa9N25Xp914k0L1+PvKLYPFo5uhY+Y8ldggrOAL8QcSVJiS8iwtLFMt X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 18 Jul 2003 16:13:22 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!dca1-feed2.news.algx.net!allegiance!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30981 John_H wrote: > > rickman wrote: > > Two points I would make. > > > > 1) Whether a cap is inductive or capacitive at a given frequency is of > > no concern. The only thing that matters is the impedance. The purpose > > of a cap is to lower the impedance of the power to ground path at the > > frequencies of your noise. A low impedance inductive path is just as > > good a coupling the noise to ground as a low impedance capacitive path. > > I agree with you an this point, but to a degree.... The Kemet value and > package mentioned with the SRF at 10MHz has an impedance of about 0.1 > ohm at 10MHz. At 100MHz, the impedance is over 1 ohm. Assuming 12 .1uF > caps scattered around an FPGA, if the chip uses a 100MHz clock there > will be a ripple on the voltage plane of 83mV per amp of dynamic > current. In today's lower foltage/higher current devices, can we accept > those levels of voltage noise? It would take 1 or 2 caps with an SRF at > 100MHz to provide the same filtering as 12 of those Kemet 0.1uF devices, > again at 100MHz. The point is that you need to do the math based on the impedance at your frequency of interest, not based on the resonance freq. The width of the resonant fequency is far too narrow to be of any real use in noise decoupling. So you need to give consideration to the impedance over the frequency range of your noise and pay no attention to whether you are inductive, capacitive or at resonance. > > 2) If you don't like the Kemel (sp? Kemet perhaps) caps, use someone > > else's caps that are rated with a higher resonance or a lower > > impedance. I know that the 0.1 uF caps I use have a resonance above 50 > > MHz. Perhaps you were looking at a larger package which adversely > > affects the impedance more than does the cap value? 0.1 uF caps come in > > 0603 packages which have very good high freq characteristics. > > Smaller packages do tend to perform better. It might be nasty working > with 0402s, but the SRF can be better. As long as the PC layout isn't > compromised (e.g., single vias distant from the mounting pads) better > results are obtained. > > I have seen few designers actually do a comprohensive decoupling > analysis. I've mentioned on this board before that the technique of > using multiple capacitor values with differing SRFs can provide great > benefit. As long as you keep the differences small (SRFs a decade apart > for adjacent capacitors with have horrible impedance at one point > between those SRFs - imagine what an inductor and capacitor in parallel > provide at resonance) and the capacitors are nicely distributed, the > total number of capacitors could be reduced to achieve the same > impedance across a frequency range of interest. I have also heard of problems that can be produced from such an arrangement. I personally don't think any of this is a real issue. I use enough caps of a decent size to be effective without trying to design special effects based on a particular cap. That makes it a lot easier to buy components without having to specify a particular brand to get the "right" tuning. > Just one capacitor value will work. EMI will suffer, there will be > noise on the voltage planes. Poorly designed combinations of caps > (e.g., two values laid out adjacent to each other in pairs aren't > distributed enough to avoid the resonance mentioned above) will also > provide ugly results but tend to "work." > > To "adjust the cap values to the higher speed of the logic" by reducing > the capacitance alone (to increase the SRF) won't "avoid EMA problems" > but will move them. Solid decoupling design will get us there. The one fact that seems to be universally true about power decoupling design is that everyone has their own way of doing it and most of them seem to work. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3F187103.338A@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB References: Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Lines: 29 Date: Sat, 19 Jul 2003 10:13:23 +1200 NNTP-Posting-Host: 210.246.6.159 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1058566381 210.246.6.159 (Sat, 19 Jul 2003 10:13:01 NZST) NNTP-Posting-Date: Sat, 19 Jul 2003 10:13:01 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!in.100proofnews.com!in.100proofnews.com!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30889 Martin Schoeberl wrote: > > > > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF > per > > > power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). > Is > > > that accurate? Should I do more? What should I avoid? > > > > That's a reasoanable ballpark. Inductance is what you want to > > avoid. Vias count, so do long traces from pads to vias. > > Why is everyone talking about 0.1uF caps? Isn't it time to adjust the cap > values to the higher speed of the logic and to avoid EMI problems. A > standard 0.1uF cap 0805 with X7R dielectric is at resonance at 10 MHz (see > datasheet of Kemel caps)! Above 10 MHz the impedance becomes inductive. EMI > is measured up to 1 GHz. They aren't - spread values are common to see, and there is a trend to smaller values. ( But I'll admit many just drop in 100nF ) I did see a good paper from Temic IIRC, on this. The key param, from a Vcc voltage noise perspective, is total system impedance, over the spectrum of the current spikes, at the pins. Another param, for RFI, is current loop area, and there local inductance makes a pi-filter, with any Cd. -jg ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: Graduation Day: My first 4-layer PCB Date: 21 Jul 2003 11:51:14 +0100 Organization: TRW Conekt Lines: 34 Sender: thompsonmj@3PG2D0J-DT Message-ID: References: <3F17F7DF.6263AD2E@yahoo.com> NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.uni-berlin.de 1058784674 15165180 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.3 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!switch.ch!news.belwue.de!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30987 rickman writes: > Martin Schoeberl wrote: > > > > Why is everyone talking about 0.1uF caps? Isn't it time to adjust the cap > > values to the higher speed of the logic and to avoid EMI problems. A > > standard 0.1uF cap 0805 with X7R dielectric is at resonance at 10 MHz (see > > datasheet of Kemel caps)! Above 10 MHz the impedance becomes inductive. EMI > > is measured up to 1 GHz. > > Two points I would make. > 2) If you don't like the Kemel (sp? Kemet perhaps) caps, use someone > else's caps that are rated with a higher resonance or a lower > impedance. I know that the 0.1 uF caps I use have a resonance above 50 > MHz. Perhaps you were looking at a larger package which adversely > affects the impedance more than does the cap value? 0.1 uF caps come in > 0603 packages which have very good high freq characteristics. > And don't forget that the inductance varies depending on both the cap itself, *and how it is mounted on the board*. You can raise the resonance significantly by placed the fanout vias in the pad of the cap, or even providing multiply vias per pad! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt