Reply-To: "William LenihanIii" From: "William LenihanIii" Newsgroups: comp.arch.fpga Subject: SPARTAN-3 vs. VIRTEX-II Lines: 66 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Date: Sun, 29 Jun 2003 23:51:08 GMT NNTP-Posting-Host: 216.244.20.78 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1056930668 216.244.20.78 (Sun, 29 Jun 2003 16:51:08 PDT) NNTP-Posting-Date: Sun, 29 Jun 2003 16:51:08 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-out1.nntp.be!propagator2-sterling!news-in-sterling.nuthinbutnews.com!cyclone1.gnilink.net!newsfeed.news2me.com!elnk-pas-nf2!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30152 ---------------------------------------------------------------------------- ------ HOW DOES SPARTAN-3 DIFFER FROM VIRTEX-II? Spartan-3 is supposed to be = Virtex-II minus "some features". Unfortunately, Xilinx does not appear to provide a comprehensive list of those differences. The following is my attempt at making such a list based on a first-cut review of each families' literature. Anyone have any comments, corrections, additions, or questions about this list? Then post them here and please 'cc' me via email. Thank you. Bill Lenihan lenihan3we@earthlink.net ---------------------------------------------------------------------------- ------ Vccint = 1.2v ..... instead of V-II's 1.5v Are there any off-the-shelf, 1-chip linear regulators (not switching regulators) that can supply 1.2v? Vccaux = 2.5v ..... instead of V-II's 3.3v half the slices are NOT full-featured: missing RAM & shift-register capability up to 4 DCMs ..... instead of V-II's 12 DCM works on input clocks up to 325 Mhz ..... V-II up to 450 Mhz 8 global clocks ..... instead of V-II's 16 data sheet mentions BUFGMUX global clock buffer, but not BUFGCE ..... V-II has both greater # of I/O, due to staggered pad scheme at chip periphery LVPECL I/O not available LVDS only w/ Vcco = 2.5v ..... V-II can run LVDS from Vcco = 2.5v or 3.3v Is there any capability for Spartan-3's +3.3v LVTTL inputs & outputs to interact with other devices that use +5v TTL? ..... V-II (and Virtex-E) +3.3v LVTTL inputs could be driven by +5v TTL outputs if an appropriately sized current-limiting resistor were in series, while V-II (and Virtex-E) +3.3v LVTTL outputs could safely connect directly to +5v TTL input devices with no intervening resistor networks. configuration pins are LVCMOS25 @ 12mA ..... V-II's are LVTTL @ 12mA data sheet mentions a Master/Slave "Parallel" configuration mode that LOOKS the same as V-II's "SelectMap" mode. Are they completely identical? If so, then why do they have different names? (I know, marketing droids -- who specialize in renaming that which already has a name -- rule the universe.) Flip-Chip packages not available 90 nm process ..... V-II uses 120/150 nm [not that the OEM designing with FPGAs really cares] ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Mon, 30 Jun 2003 00:53:53 -0400 Organization: Arius, Inc Lines: 100 Message-ID: <3EFFC261.F57E9987@yahoo.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbVmFwxX+HnSlBbA3TuSzJMv/CJCoVSfrkwRp1X6uAaF9D8KIPLpBEC X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 30 Jun 2003 04:53:58 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30148 William LenihanIii wrote: > > ---------------------------------------------------------------------------- > ------ > HOW DOES SPARTAN-3 DIFFER FROM VIRTEX-II? > > Spartan-3 is supposed to be = Virtex-II minus "some features". > Unfortunately, > Xilinx does not appear to provide a comprehensive list of those differences. > The following is my attempt at making such a list based on a first-cut > review > of each families' literature. > > Anyone have any comments, corrections, additions, or questions about this > list? > Then post them here and please 'cc' me via email. > > Thank you. > > Bill Lenihan lenihan3we@earthlink.net > ---------------------------------------------------------------------------- > ------ > > Vccint = 1.2v ..... instead of V-II's 1.5v > Are there any off-the-shelf, 1-chip linear regulators (not switching > regulators) that can supply 1.2v? Yes, the 1.2 volts is not hard, the question is from what voltage? Using an input voltage lower than 2.0 or 2.5 is not so easy. But there are a few around, Micrel, Maxim and some others. Micrel has a linear controller that if coupled with one of the really small MOSFETs is a smaller total footprint than a one piece solution and has better power numbers. > Vccaux = 2.5v ..... instead of V-II's 3.3v > > half the slices are NOT full-featured: missing RAM & shift-register > capability This has been discussed with mixed opinions. I think most designers won't care since using more than half the chip as SRs is unlikely (other than Ray Andraka). > up to 4 DCMs ..... instead of V-II's 12 Yeah, I would really like to have 5 in my design, but I will settle for 4. > DCM works on input clocks up to 325 Mhz ..... V-II up to 450 Mhz > > 8 global clocks ..... instead of V-II's 16 > > data sheet mentions BUFGMUX global clock buffer, but not BUFGCE ..... V-II > has both > > greater # of I/O, due to staggered pad scheme at chip periphery I don't think this is correct. The number of IOs for a given number of slices or gates is about the same. I spot checked about four parts and did not see a significant difference. > LVPECL I/O not available > > LVDS only w/ Vcco = 2.5v ..... V-II can run LVDS from Vcco = 2.5v or 3.3v > > Is there any capability for Spartan-3's +3.3v LVTTL inputs & outputs to > interact with other devices that use +5v TTL? ..... V-II (and Virtex-E) > +3.3v LVTTL inputs could be driven by +5v TTL outputs if an appropriately > sized current-limiting resistor were in series, while V-II (and Virtex-E) > +3.3v LVTTL outputs could safely connect directly to +5v TTL input devices > with no intervening resistor networks. > > configuration pins are LVCMOS25 @ 12mA ..... V-II's are LVTTL @ 12mA > > data sheet mentions a Master/Slave "Parallel" configuration mode that LOOKS > the same as V-II's "SelectMap" mode. Are they completely identical? If so, > then why do they have different names? (I know, marketing droids -- who > specialize in renaming that which already has a name -- rule the universe.) > > Flip-Chip packages not available > > 90 nm process ..... V-II uses 120/150 nm [not that the OEM designing with > FPGAs really cares] -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: oen_br@yahoo.com.br (Luiz Carlos) Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: 30 Jun 2003 03:19:56 -0700 Organization: http://groups.google.com/ Lines: 13 Message-ID: <8471ba54.0306300219.677d371f@posting.google.com> References: <3EFFC261.F57E9987@yahoo.com> NNTP-Posting-Host: 200.102.50.197 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1056968396 26936 127.0.0.1 (30 Jun 2003 10:19:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 30 Jun 2003 10:19:56 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!switch.ch!news-fra1.dfn.de!news.tele.dk!news.tele.dk!small.news.tele.dk!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30159 > > half the slices are NOT full-featured: missing RAM & shift-register > > capability > > This has been discussed with mixed opinions. I think most designers > won't care since using more than half the chip as SRs is unlikely (other > than Ray Andraka). You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", not half of the ditributed memory! Luiz Carlos Oenning Martins KHOMP solutions ###### Message-ID: <3f003c28$0$23104$5a62ac22@freenews.iinet.net.au> From: hamish@cloud.net.au Subject: Re: SPARTAN-3 vs. VIRTEX-II Newsgroups: comp.arch.fpga References: User-Agent: tin/1.5.19-20030610 ("Darts") (UNIX) (Linux/2.4.20 (i586)) Date: 30 Jun 2003 13:33:29 GMT Lines: 20 NNTP-Posting-Host: 203.217.48.13 X-Trace: 1056980009 freenews.iinet.net.au 23104 203.217.48.13 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeeder.edisontel.com!fu-berlin.de!newsfeed.iinet.net.au!newsfeed.iinet.net.au!freenews.iinet.net.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30179 William LenihanIii wrote: > half the slices are NOT full-featured: missing RAM & shift-register > capability That sounds a bit disappointing. Which half? > 8 global clocks ..... instead of V-II's 16 2V has 16 BUFGMUXs but you can only use 8 global clocks, or 8 clocks in any one quadrant. Not quite the same. > data sheet mentions BUFGMUX global clock buffer, but not BUFGCE ..... V-II > has both Same hardware in the 2V, so it's probably the same in the 3S. Hamish -- Hamish Moffatt VK3SB ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Mon, 30 Jun 2003 10:31:23 -0400 Organization: Arius, Inc Lines: 35 Message-ID: <3F0049BB.5E590511@yahoo.com> References: <3EFFC261.F57E9987@yahoo.com> <8471ba54.0306300219.677d371f@posting.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVb4+zM1OxpQ32dmGMuPdnrggnxv5vAwIx6VCk0SrwRpB9Glz2XDgt6K X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 30 Jun 2003 14:31:18 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30185 Luiz Carlos wrote: > > > > half the slices are NOT full-featured: missing RAM & shift-register > > > capability > > > > This has been discussed with mixed opinions. I think most designers > > won't care since using more than half the chip as SRs is unlikely (other > > than Ray Andraka). > > You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, > RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", > not half of the ditributed memory! Unless I am missing something, I still don't see the issue. My point is that it is a rare design indeed that needs even close to half the LUTs used as distributed RAM or SRs. Most designs use a small number of SRs and RAMs and the rest of the chip is used as logic. If eliminating these functions from the chip reduced the die area significantly, then it was a good thing, IMHO. But from days past I was always told that the routing ate up the lion's share of the chip. The saying goes, "We sell you the routing and give you the logic for free". -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Mon, 30 Jun 2003 14:44:09 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 29 Message-ID: References: <3EFFC261.F57E9987@yahoo.com> <8471ba54.0306300219.677d371f@posting.google.com> <3F0049BB.5E590511@yahoo.com> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1056984249 7054 128.32.112.203 (30 Jun 2003 14:44:09 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Mon, 30 Jun 2003 14:44:09 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30172 In article <3F0049BB.5E590511@yahoo.com>, rickman wrote: >> You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, >> RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", >> not half of the ditributed memory! > >Unless I am missing something, I still don't see the issue. My point is >that it is a rare design indeed that needs even close to half the LUTs >used as distributed RAM or SRs. Most designs use a small number of SRs >and RAMs and the rest of the chip is used as logic. And the wider rams (using all 8 luts in a CLB) can generally be done with a BlockRam without that much wastage for most cases. >If eliminating these functions from the chip reduced the die area >significantly, then it was a good thing, IMHO. But from days past I was >always told that the routing ate up the lion's share of the chip. The >saying goes, "We sell you the routing and give you the logic for free". Well, it doesn't only make the lut smaller, but also saves on a couple of inputs! Removing inputs to a CLB really does save alot, as those are effectively routing. Also, the Spartan 3 doesn't have as rich an interconnect, but Xilinx isn't stating the details yet. Since the parts will be smaller even in the largest case, teh interconnect doesn't HAVE to be as rich anyway. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: oen_br@yahoo.com.br (Luiz Carlos) Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: 30 Jun 2003 10:49:36 -0700 Organization: http://groups.google.com/ Lines: 23 Message-ID: <8471ba54.0306300949.22a2478b@posting.google.com> References: <3EFFC261.F57E9987@yahoo.com> <8471ba54.0306300219.677d371f@posting.google.com> <3F0049BB.5E590511@yahoo.com> NNTP-Posting-Host: 200.102.50.197 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1056995377 8880 127.0.0.1 (30 Jun 2003 17:49:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 30 Jun 2003 17:49:37 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.tele.dk!news.tele.dk!small.news.tele.dk!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30231 > > You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, > > RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", > > not half of the ditributed memory! > > Unless I am missing something, I still don't see the issue. My point is > that it is a rare design indeed that needs even close to half the LUTs > used as distributed RAM or SRs. Most designs use a small number of SRs > and RAMs and the rest of the chip is used as logic. Rick, I donīt know about other applications, but this kind of dual ported memory helps me a lot. I use it primary as memory for filters, and the fact that I can have a write and a read separate ports, save me a lot of logic and let me run the filters at double speed (or half clock rate). The block RAM is not usable because the throughput: I have a lot of filters running in parallel. So these wider memories let me implement bigger filters at high speed without to much complication. Of course I can, and have to live without them in Spartan3, but if Iīm not alone, maybe in Spartan4... Peter and Austin, I know there are Virtex2 and Virtex2Pro! Luiz Carlos Oenning Martins KHOMP Solutions ###### From: billh40@aol.com (Bill Hanna) Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: 30 Jun 2003 10:54:32 -0700 Organization: http://groups.google.com/ Lines: 78 Message-ID: <97d137ce.0306300954.15c7538a@posting.google.com> References: NNTP-Posting-Host: 207.178.213.210 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1056995672 9051 127.0.0.1 (30 Jun 2003 17:54:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 30 Jun 2003 17:54:32 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30238 "William LenihanIii" wrote in message news:... > ---------------------------------------------------------------------------- > ------ > HOW DOES SPARTAN-3 DIFFER FROM VIRTEX-II? > > Spartan-3 is supposed to be = Virtex-II minus "some features". > Unfortunately, > Xilinx does not appear to provide a comprehensive list of those differences. > The following is my attempt at making such a list based on a first-cut > review > of each families' literature. > > Anyone have any comments, corrections, additions, or questions about this > list? > Then post them here and please 'cc' me via email. > > Thank you. > > Bill Lenihan lenihan3we@earthlink.net The key factor is that the Spartan 3 will be 1/2 the cost of the Virtex II. This is a major selling point for large designs. I have a design that uses the XC2V6000-4 at a cost of $4,000 per chip. The design requires 23,000 slices. The Spartan 3 XC3S4000 (27,648 slices) costs $1,531 (1-24). The XC3$5000 (33,280 slices) costs $1,933 (1-24). The costs are $200 lower for the lower pin count BGA packages (900). The lower clock speed is not a problem, limited I/O pads are not a problem and the lower VCC supply voltage is not a problem (1.2 VDC). The parts are not available until 2004. Bill Hanna > ---------------------------------------------------------------------------- > ------ > > Vccint = 1.2v ..... instead of V-II's 1.5v > Are there any off-the-shelf, 1-chip linear regulators (not switching > regulators) that can supply 1.2v? > > Vccaux = 2.5v ..... instead of V-II's 3.3v > > half the slices are NOT full-featured: missing RAM & shift-register > capability > > up to 4 DCMs ..... instead of V-II's 12 > > DCM works on input clocks up to 325 Mhz ..... V-II up to 450 Mhz > > 8 global clocks ..... instead of V-II's 16 > > data sheet mentions BUFGMUX global clock buffer, but not BUFGCE ..... V-II > has both > > greater # of I/O, due to staggered pad scheme at chip periphery > > LVPECL I/O not available > > LVDS only w/ Vcco = 2.5v ..... V-II can run LVDS from Vcco = 2.5v or 3.3v > > Is there any capability for Spartan-3's +3.3v LVTTL inputs & outputs to > interact with other devices that use +5v TTL? ..... V-II (and Virtex-E) > +3.3v LVTTL inputs could be driven by +5v TTL outputs if an appropriately > sized current-limiting resistor were in series, while V-II (and Virtex-E) > +3.3v LVTTL outputs could safely connect directly to +5v TTL input devices > with no intervening resistor networks. > > configuration pins are LVCMOS25 @ 12mA ..... V-II's are LVTTL @ 12mA > > data sheet mentions a Master/Slave "Parallel" configuration mode that LOOKS > the same as V-II's "SelectMap" mode. Are they completely identical? If so, > then why do they have different names? (I know, marketing droids -- who > specialize in renaming that which already has a name -- rule the universe.) > > Flip-Chip packages not available > > 90 nm process ..... V-II uses 120/150 nm [not that the OEM designing with > FPGAs really cares] ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Mon, 30 Jun 2003 23:27:12 -0400 Organization: Arius, Inc Lines: 42 Message-ID: <3F00FF90.FB2A0E20@yahoo.com> References: <3EFFC261.F57E9987@yahoo.com> <8471ba54.0306300219.677d371f@posting.google.com> <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: UmFuZG9tSVY5K4ENGIRA5ONgFYPFSfiiI14A5TTlC5mQIBSTj5sMhr0B23/V0DGR X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Jul 2003 03:27:15 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-out1.nntp.be!propagator2-sterling!In.nntp.be!news-out.visi.com!petbe.visi.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30187 Luiz Carlos wrote: > > > > You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, > > > RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", > > > not half of the ditributed memory! > > > > Unless I am missing something, I still don't see the issue. My point is > > that it is a rare design indeed that needs even close to half the LUTs > > used as distributed RAM or SRs. Most designs use a small number of SRs > > and RAMs and the rest of the chip is used as logic. > > Rick, I donīt know about other applications, but this kind of dual > ported memory helps me a lot. I use it primary as memory for filters, > and the fact that I can have a write and a read separate ports, save > me a lot of logic and let me run the filters at double speed (or half > clock rate). The block RAM is not usable because the throughput: I > have a lot of filters running in parallel. So these wider memories let > me implement bigger filters at high speed without to much > complication. Of course I can, and have to live without them in > Spartan3, but if Iīm not alone, maybe in Spartan4... Again, I don't think you are reading what I am posting. In the XC3S400 there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs capable of being RAMs and SRs. How many do you really need??? That is 56,000 bits of distributed RAM, almost a quarter as much as the block rams! Don't you need some LUTs to use as logic??? I am sure that nearly any design that will run in a VirtexII will also run in a Spartan 3 with as many CLBs (Ray Andraka aside). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Tue, 1 Jul 2003 04:12:49 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 12 Message-ID: References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1057032769 40013 128.32.112.203 (1 Jul 2003 04:12:49 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Tue, 1 Jul 2003 04:12:49 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!newshub.sdsu.edu!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30215 In article <3F00FF90.FB2A0E20@yahoo.com>, rickman wrote: >Again, I don't think you are reading what I am posting. In the XC3S400 >there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs >capable of being RAMs and SRs. How many do you really need??? That is >56,000 bits of distributed RAM, almost a quarter as much as the block >rams! Don't you need some LUTs to use as logic??? The wider address rams will require external muxing/control to implement with only 4 LUTs/CLB usable as ram rather than 8. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: oen_br@yahoo.com.br (Luiz Carlos) Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: 1 Jul 2003 03:03:56 -0700 Organization: http://groups.google.com/ Lines: 18 Message-ID: <8471ba54.0307010203.6a4ca9@posting.google.com> References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> NNTP-Posting-Host: 200.102.50.197 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1057053836 4414 127.0.0.1 (1 Jul 2003 10:03:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 1 Jul 2003 10:03:56 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30229 > >Again, I don't think you are reading what I am posting. In the XC3S400 > >there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs > >capable of being RAMs and SRs. How many do you really need??? That is > >56,000 bits of distributed RAM, almost a quarter as much as the block > >rams! Don't you need some LUTs to use as logic??? > > The wider address rams will require external muxing/control to > implement with only 4 LUTs/CLB usable as ram rather than 8. That is my poit of view. I donīt care (not much) of having just half of the LUTs confurable as memory (Iīve read what you wrote, Rick), but I didnīt like loosing those dual ported bigger blocks (you didnīt read carefully what I wrote). To have the same function I'll need a lot of additional logic and/or a clock two times faster. So, my DSP designs need a lot of more CLBs in Spartan3 than in Virtex2, and I'm not Ray. Luiz Carlos Oenning Martins KHOMP Solutions ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Tue, 01 Jul 2003 10:42:57 -0400 Organization: Arius, Inc Lines: 49 Message-ID: <3F019DF1.753E2C73@yahoo.com> References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: UmFuZG9tSVZdn1gD2aWfriD+vTPRuEMlxZ6zVTtZ4ImxAsICBoDUp/6Xqwnp0b/B X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Jul 2003 14:43:04 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30186 Luiz Carlos wrote: > > > >Again, I don't think you are reading what I am posting. In the XC3S400 > > >there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs > > >capable of being RAMs and SRs. How many do you really need??? That is > > >56,000 bits of distributed RAM, almost a quarter as much as the block > > >rams! Don't you need some LUTs to use as logic??? > > > > The wider address rams will require external muxing/control to > > implement with only 4 LUTs/CLB usable as ram rather than 8. > > That is my poit of view. I donīt care (not much) of having just half > of the LUTs confurable as memory (Iīve read what you wrote, Rick), but > I didnīt like loosing those dual ported bigger blocks (you didnīt read > carefully what I wrote). To have the same function I'll need a lot of > additional logic and/or a clock two times faster. So, my DSP designs > need a lot of more CLBs in Spartan3 than in Virtex2, and I'm not Ray. > > Luiz Carlos Oenning Martins > KHOMP Solutions You can feel how you wish about your designs, but even the loss of the 64 bit dual ports and the 128 bit single port rams is not signficant. To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII) and one LUT for the read mux and possibly two more LUTs for the WEs. But if this is part of a larger ram block you are making half of the WEs would have been required anyway. So it is not a "large" amount of logic, just a bit more. If you are making really large blocks where the longer runs on the address and data can slow it down significantly, then you likely are better off with the block rams. Considering the much lower price of the XC3S parts, all this sounds to me like a benefit, not a liability. Think of it as paying for the LUTs that have RAM and getting the other LUTs for free :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: oen_br@yahoo.com.br (Luiz Carlos) Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: 1 Jul 2003 12:19:01 -0700 Organization: http://groups.google.com/ Lines: 32 Message-ID: <8471ba54.0307011119.27dbf58d@posting.google.com> References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> NNTP-Posting-Host: 200.102.50.197 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1057087142 22199 127.0.0.1 (1 Jul 2003 19:19:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 1 Jul 2003 19:19:02 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30241 > You can feel how you wish about your designs, but even the loss of the > 64 bit dual ports and the 128 bit single port rams is not signficant. > To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII) > and one LUT for the read mux and possibly two more LUTs for the WEs. > But if this is part of a larger ram block you are making half of the WEs > would have been required anyway. So it is not a "large" amount of > logic, just a bit more. Ok, I agree with you, itīs not to much logic. But because these extra delays maybe I have to duplicate the circuits. > If you are making really large blocks where the longer runs on the > address and data can slow it down significantly, then you likely are > better off with the block rams. No, they are not large blocks, but I have 128 to 512 FIR filters (256 coefs) running in parallel, and the sampling rate is 2 megaHertz. Throughput! > Considering the much lower price of the XC3S parts, all this sounds to > me like a benefit, not a liability. Think of it as paying for the LUTs > that have RAM and getting the other LUTs for free :) I'm not complaining, and I know that Xilinx wil not make a special Spartan3 just for me. But I have the right to express what I think, and maybe I'm not alone. Maybe there are a lot of Luizes and Rays, maybe Xilinx will hear us and maybe, at these nanometer scales where the pads are so big, to have all the CLBs configurable as memory is not so significant in silicon area. Luiz Carlos Oenning Martins KHOMP Solutions ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Tue, 01 Jul 2003 14:45:31 -0700 Organization: Xilinx,Inc Lines: 27 Message-ID: <3F0200FB.FF77F1E8@xilinx.com> References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> <8471ba54.0307011119.27dbf58d@posting.google.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Luiz Carlos Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!enews.sgi.com!nntp.wetware.com!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30204 Xilinx has two major product lines. Virtex is for performance and features, Spartan is for low cost. Otherwise, the architectures are very similar. That gives us a chance to really optimize each line. The Spartan developers reduce the cost, accepting that this makes their devices non-optimal for certain applications, but there is always Virtex to deliver higher functionality and performance (at a higher price). The Virtex designers can optimize functionality and speed, knowing that this might increase the cost, but there is always Spartan to satisfy less performance-critical, but more cost-sensitive applications. There is no free lunch, in engineering almost everything is a trade-off. But everybody still asks for champagne on a beer budget :-) Peter Alfke ======================= Luiz Carlos wrote: > > > I'm not complaining, and I know that Xilinx wil not make a special > Spartan3 just for me. But I have the right to express what I think, > and maybe I'm not alone. Maybe there are a lot of Luizes and Rays, > maybe Xilinx will hear us and maybe, at these nanometer scales where > the pads are so big, to have all the CLBs configurable as memory is > not so significant in silicon area. > > Luiz Carlos Oenning Martins > KHOMP Solutions ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Wed, 02 Jul 2003 02:17:33 -0400 Organization: Arius, Inc Lines: 61 Message-ID: <3F0278FD.7C19250A@yahoo.com> References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> <8471ba54.0307011119.27dbf58d@posting.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: UmFuZG9tSVZNE9t3nqycnjfk+pGHGqZqh8YheU1i4QotVDmvrYleUHdk35IIbCvw X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 2 Jul 2003 06:17:34 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30257 Luiz Carlos wrote: > > > You can feel how you wish about your designs, but even the loss of the > > 64 bit dual ports and the 128 bit single port rams is not signficant. > > To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII) > > and one LUT for the read mux and possibly two more LUTs for the WEs. > > But if this is part of a larger ram block you are making half of the WEs > > would have been required anyway. So it is not a "large" amount of > > logic, just a bit more. > > Ok, I agree with you, itīs not to much logic. But because these extra > delays maybe I have to duplicate the circuits. > > > If you are making really large blocks where the longer runs on the > > address and data can slow it down significantly, then you likely are > > better off with the block rams. > > No, they are not large blocks, but I have 128 to 512 FIR filters (256 > coefs) running in parallel, and the sampling rate is 2 megaHertz. > Throughput! > > > Considering the much lower price of the XC3S parts, all this sounds to > > me like a benefit, not a liability. Think of it as paying for the LUTs > > that have RAM and getting the other LUTs for free :) > > I'm not complaining, and I know that Xilinx wil not make a special > Spartan3 just for me. But I have the right to express what I think, > and maybe I'm not alone. Maybe there are a lot of Luizes and Rays, > maybe Xilinx will hear us and maybe, at these nanometer scales where > the pads are so big, to have all the CLBs configurable as memory is > not so significant in silicon area. Yes, certainly you have the right to express your views and to let Xilinx know what you need. But I think you are responding to the idea that "something" is missing without knowing for sure if it is really an issue. When you say above that adding the level of logic may slow down the design, you first need to know how fast these parts run. After all, you are comparing 90 nm Spartan 3s to 150 nm VirtexIIs. It is very possible that the S3s will run faster even with the added delays. I am sorry if my "nagging" is annoying. But I have watched a lot of changes in FPGAs and have often felt they were not for the better. But somewhere around the Virtex or VirtexII parts I started to realize that I needed to forget about how the parts were different and focus on how to solve my design problems using them. With that I have come to understand that often what I saw as a limitation is more than made up for in other areas. I am sure that Xilinx does not remove functionality without considering the trade offs very seriously. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Wed, 02 Jul 2003 02:20:31 -0400 Organization: Arius, Inc Lines: 34 Message-ID: <3F0279AF.CDEC32E4@yahoo.com> References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> <8471ba54.0307011119.27dbf58d@posting.google.com> <3F0200FB.FF77F1E8@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbeCQxxUJnU7aIZFov2sls6ULALxIkmCOOaSzhONjZ34UiI4Xac60Qy X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 2 Jul 2003 06:20:29 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30263 Peter Alfke wrote: > > Xilinx has two major product lines. Virtex is for performance and > features, Spartan is for low cost. Otherwise, the architectures are very similar. > > That gives us a chance to really optimize each line. The Spartan > developers reduce the cost, accepting that this makes their devices > non-optimal for certain applications, but there is always Virtex to > deliver higher functionality and performance (at a higher price). > The Virtex designers can optimize functionality and speed, knowing that > this might increase the cost, but there is always Spartan to satisfy > less performance-critical, but more cost-sensitive applications. > > There is no free lunch, in engineering almost everything is a trade-off. > But everybody still asks for champagne on a beer budget :-) > Peter Alfke I am not looking for champagne on a beer budget, but I would sure like to be able to pour them both into the same glass. That is I would like to have one footprint that I an put a Spartan into for low cost or a Virtex when I need high performance and large size. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Reply-To: "William LenihanIii" From: "William LenihanIii" Newsgroups: comp.arch.fpga References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> <8471ba54.0307011119.27dbf58d@posting.google.com> <3F0200FB.FF77F1E8@xilinx.com> Subject: Re: SPARTAN-3 vs. VIRTEX-II Lines: 58 X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Date: Wed, 02 Jul 2003 07:52:01 GMT NNTP-Posting-Host: 209.179.52.206 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1057132321 209.179.52.206 (Wed, 02 Jul 2003 00:52:01 PDT) NNTP-Posting-Date: Wed, 02 Jul 2003 00:52:01 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newshub.sdsu.edu!elnk-pas-nf2!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30269 Peter -- I have no problem with the fact that these are 2 seperate product lines which target 2 different needs, but when Xilinx states that "Spartan-3 is basically Virtex-II, but whith a few things missing", I think Xilinx ought to be considerate of it's customers and enumerate EXACTLY what those ".... few things missing" are. To paraphrase John Cooley (Synopsys & EDA Gadfly): Customers can accept virtually any truth about a product as long as they don't have to find out about it painfully. I'm not asking for "champagne on a beer budget". What I am saying is: I've spent a good amount of time studying champagne (Virtex-II), but I don't have a lot of time right now to study beer (Spartan-3) from scratch. Since Xilinx claims to be making beer by subtracting a few things from champagne, Xilinx can save me a LOT OF TIME by just telling me what those few subtractions are, and then I can quickly figure out if beer is what I need. My management is experiencing a little sticker shock right now at the cost of champagne, but if I get them hooked on the cost of beer, and we discover that beer can't quite satisfy our tastes 6 months from now, that will be an enormous source of grief & embarrassment that I want to avoid. Can you comment on my list? Additions? Corrections? "Peter Alfke" wrote in message news:3F0200FB.FF77F1E8@xilinx.com... > Xilinx has two major product lines. Virtex is for performance and > features, Spartan is for low cost. Otherwise, the architectures are very similar. > > That gives us a chance to really optimize each line. The Spartan > developers reduce the cost, accepting that this makes their devices > non-optimal for certain applications, but there is always Virtex to > deliver higher functionality and performance (at a higher price). > The Virtex designers can optimize functionality and speed, knowing that > this might increase the cost, but there is always Spartan to satisfy > less performance-critical, but more cost-sensitive applications. > > There is no free lunch, in engineering almost everything is a trade-off. > But everybody still asks for champagne on a beer budget :-) > Peter Alfke > ======================= > Luiz Carlos wrote: > > > > > > I'm not complaining, and I know that Xilinx wil not make a special > > Spartan3 just for me. But I have the right to express what I think, > > and maybe I'm not alone. Maybe there are a lot of Luizes and Rays, > > maybe Xilinx will hear us and maybe, at these nanometer scales where > > the pads are so big, to have all the CLBs configurable as memory is > > not so significant in silicon area. > > > > Luiz Carlos Oenning Martins > > KHOMP Solutions > ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Wed, 2 Jul 2003 10:35:54 +0100 Lines: 14 Message-ID: References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> <8471ba54.0307011119.27dbf58d@posting.google.com> <3F0200FB.FF77F1E8@xilinx.com> NNTP-Posting-Host: tile.demon.co.uk X-Trace: news.demon.co.uk 1057139227 11251 158.152.50.250 (2 Jul 2003 09:47:07 GMT) X-Complaints-To: abuse@demon.net NNTP-Posting-Date: Wed, 2 Jul 2003 09:47:07 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 X-Priority: 3 X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MSMail-Priority: Normal Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!kibo.news.demon.net!news.demon.co.uk!demon!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30282 William LenihanIii wrote: > I'm not asking for "champagne on a beer budget". What I am saying is: > I've spent a good amount of time studying champagne (Virtex-II), but > I don't have a lot of time right now to study beer (Spartan-3) from > scratch. As has been said before in the group, one of the best features of Xilinx datasheets was the section on 'how this part differs from the last generation.' Is that too complex for management to get it? ###### From: oen_br@yahoo.com.br (Luiz Carlos) Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: 2 Jul 2003 02:47:33 -0700 Organization: http://groups.google.com/ Lines: 7 Message-ID: <8471ba54.0307020147.3c19fa1d@posting.google.com> References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> <8471ba54.0307011119.27dbf58d@posting.google.com> <3F0200FB.FF77F1E8@xilinx.com> NNTP-Posting-Host: 200.102.50.197 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1057139254 14579 127.0.0.1 (2 Jul 2003 09:47:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 2 Jul 2003 09:47:34 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30295 > There is no free lunch, in engineering almost everything is a trade-off. > But everybody still asks for champagne on a beer budget :-) > Peter Alfke French champagne, please! :) Luiz Carlos ###### From: oen_br@yahoo.com.br (Luiz Carlos) Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: 2 Jul 2003 03:00:20 -0700 Organization: http://groups.google.com/ Lines: 20 Message-ID: <8471ba54.0307020200.20f810a1@posting.google.com> References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> <8471ba54.0307011119.27dbf58d@posting.google.com> <3F0278FD.7C19250A@yahoo.com> NNTP-Posting-Host: 200.102.50.197 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1057140020 14936 127.0.0.1 (2 Jul 2003 10:00:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 2 Jul 2003 10:00:20 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30290 > After all, > you are comparing 90 nm Spartan 3s to 150 nm VirtexIIs. It is very > possible that the S3s will run faster even with the added delays. It doesn't look like (using the projected speeds for MicroBlaze). > I am sorry if my "nagging" is annoying. But I have watched a lot of > changes in FPGAs and have often felt they were not for the better. But > somewhere around the Virtex or VirtexII parts I started to realize that > I needed to forget about how the parts were different and focus on how > to solve my design problems using them. With that I have come to > understand that often what I saw as a limitation is more than made up > for in other areas. I am sure that Xilinx does not remove functionality > without considering the trade offs very seriously. It's ok. Maybe some day we can take a drink and talk about this. Better, let's invite Peter, he can pay that french champagne! (I like beer too) :) Luiz Carlos ###### From: "BRANE-NEWS" Newsgroups: comp.arch.fpga References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> <8471ba54.0307011119.27dbf58d@posting.google.com> <3F0200FB.FF77F1E8@xilinx.com> <3F0279AF.CDEC32E4@yahoo.com> Subject: Re: SPARTAN-3 vs. VIRTEX-II Lines: 13 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: Date: Tue, 8 Jul 2003 21:43:56 +0200 NNTP-Posting-Host: 193.95.199.9 X-Complaints-To: abuse@siol.net X-Trace: news.siol.net 1057693394 193.95.199.9 (Tue, 08 Jul 2003 21:43:14 MET DST) NNTP-Posting-Date: Tue, 08 Jul 2003 21:43:14 MET DST Organization: Slovenija OnLine - SiOL Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!switch.ch!kanja.arnes.si!news-hub.siol.net!news.siol.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30541 "rickman" wrote in message > I am not looking for champagne on a beer budget, but I would sure like > to be able to pour them both into the same glass. Isn't that a bit of redneck perspective -champagne in Budweiser glass ? ;o) ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SPARTAN-3 vs. VIRTEX-II Date: Wed, 09 Jul 2003 01:10:01 -0400 Organization: Arius, Inc Lines: 24 Message-ID: <3F0BA3A9.547A4622@yahoo.com> References: <3F0049BB.5E590511@yahoo.com> <8471ba54.0306300949.22a2478b@posting.google.com> <3F00FF90.FB2A0E20@yahoo.com> <8471ba54.0307010203.6a4ca9@posting.google.com> <3F019DF1.753E2C73@yahoo.com> <8471ba54.0307011119.27dbf58d@posting.google.com> <3F0200FB.FF77F1E8@xilinx.com> <3F0279AF.CDEC32E4@yahoo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVafzsjoOJlICjR19NOsfMZRiZnyGWQuakmorrpKsn5j0/hN9wOuxXDZ X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 9 Jul 2003 05:10:23 GMT X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!switch.ch!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:30595 BRANE-NEWS wrote: > > "rickman" wrote in message > > > > I am not looking for champagne on a beer budget, but I would sure like > > to be able to pour them both into the same glass. > > Isn't that a bit of redneck perspective -champagne in Budweiser glass ? ;o) That's what we call a Fredneck around here... :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX