From: "Christian Widtmann" Newsgroups: comp.arch.fpga Subject: Problem with tristate-inout-pins of PS/2-Host Date: Fri, 13 Jun 2003 14:53:04 +0200 Organization: Vienna University of Technology, Austria Lines: 35 Message-ID: NNTP-Posting-Host: chello062178081202.28.11.tuwien.teleweb.at X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!news.netway.at!leech.it-austria.net!newsfeed01.univie.ac.at!aconews-feed.univie.ac.at!news.tuwien.ac.at!tuwien-news Xref: chonsp.franklin.ch comp.arch.fpga:29545 Hi! I'm trying to develop a PS/2-host in VHDL, whose entity naturally includes the two inout-ports data and clock. Whenever the line is floating, the host and the testbench both set it to high impedance = Z. That complies with the PS/2-specification, and the synthesis log says that the pins are correctly translatet into tri-state-pins. The problem is, I'm shifting the clock-signal into a 8-bit-FIFO to cope with noise and spikes and to ensure that it is a real falling edge on the clock-signal, but as soon as I shift the Z of the floating bus into the FIFO the whole circuit goes nuts. This only happens after systhesis in pre-layout-simulation, before that everything works fine. Same happens with data, since I have to listen for a potential device's start-bit, which is 0, and a falling edge on the clock, I have to listen to both lines all the time, including the time they are Z. In real life, if both host and device leave the line floating, a pull-up-resistor would pull it to 1, so I tried to model this by the testbench, leaving the line at H rather than Z, which should overwrite the Z supplied by the host, which it did. But still, the same effect, just after a clock-cycle of the fpga (30 MHz) in pre-layout-simulation both data and clock turn from Z or H to X, along with some other signals, and this propagates through the whole circuit. I don't know if this X on data and clock is caused by some feedback from the curcuit or if they are the cause for the Xs within the curcuit, so I'm not sure who is cause and who is effect. Any ideas how to model this or how to model tristate-inout-pins with pull-up-resistor in general? With best regards, Christian Widtmann Vienna University of Technology ###### From: "Glen Herrmannsfeldt" Newsgroups: comp.arch.fpga References: Subject: Re: Problem with tristate-inout-pins of PS/2-Host Lines: 33 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Message-ID: NNTP-Posting-Host: 12.207.204.17 X-Complaints-To: abuse@attbi.com X-Trace: sccrnsc01 1055527608 12.207.204.17 (Fri, 13 Jun 2003 18:06:48 GMT) NNTP-Posting-Date: Fri, 13 Jun 2003 18:06:48 GMT Organization: AT&T Broadband Date: Fri, 13 Jun 2003 18:06:48 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!arclight.uoregon.edu!wn13feed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi.com!sccrnsc01.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:29542 "Christian Widtmann" wrote in message news:bcchea$le3$1@news.tuwien.ac.at... > I'm trying to develop a PS/2-host in VHDL, whose entity naturally includes > the two inout-ports data and clock. Whenever the line is floating, the host > and the testbench both set it to high impedance = Z. That complies with the > PS/2-specification, and the synthesis log says that the pins are correctly > translatet into tri-state-pins. > > The problem is, I'm shifting the clock-signal into a 8-bit-FIFO to cope > with noise and spikes and to ensure that it is a real falling edge on the > clock-signal, but as soon as I shift the Z of the floating bus into the > FIFO the whole circuit goes nuts. This only happens after systhesis in > pre-layout-simulation, before that everything works fine. (snip) Since real signals are either 0 or 1, with the possible exception of the signal on the tri-state bus itself, there are some problems that occur only in simulation. Usually, though, for a properly designed circuit they will "shift out" after a reasonably number of clock cycles. If they don't you should figure out why, and fix it. Consider for example that a signal could be X, unknown. But if that signal is XORed with itself, you and I know the result will be 0, but the simulation will be X. -- glen ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: Problem with tristate-inout-pins of PS/2-Host Date: 16 Jun 2003 08:39:02 +0100 Organization: TRW Conekt Lines: 52 Sender: thompsonmj@1WVMP0J-DT Message-ID: References: NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1055749148 20684275 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:29587 "Christian Widtmann" writes: > Hi! > > I'm trying to develop a PS/2-host in VHDL, whose entity naturally includes > the two inout-ports data and clock. Whenever the line is floating, the host > and the testbench both set it to high impedance = Z. That complies with the > PS/2-specification, and the synthesis log says that the pins are correctly > translatet into tri-state-pins. > > The problem is, I'm shifting the clock-signal into a 8-bit-FIFO to cope > with noise and spikes and to ensure that it is a real falling edge on the > clock-signal, but as soon as I shift the Z of the floating bus into the > FIFO the whole circuit goes nuts. This only happens after systhesis in > pre-layout-simulation, before that everything works fine. Same happens with > data, since I have to listen for a potential device's start-bit, which is > 0, and a falling edge on the clock, I have to listen to both lines all the > time, including the time they are Z. > In real life, if both host and device leave the line floating, a > pull-up-resistor would pull it to 1, so I tried to model this by the > testbench, leaving the line at H rather than Z, which should overwrite the > Z supplied by the host, which it did. But still, the same effect, just > after a clock-cycle of the fpga (30 MHz) in pre-layout-simulation both data > and clock turn from Z or H to X, along with some other signals, and this > propagates through the whole circuit. I don't know if this X on data and > clock is caused by some feedback from the curcuit or if they are the cause > for the Xs within the curcuit, so I'm not sure who is cause and who is > effect. > > Any ideas how to model this or how to model tristate-inout-pins with > pull-up-resistor in general? > You've got most of the way there - you just need to put a to_X01() translation between your bus pin and the logic that uses it. This will convert the 'H' on the bus from the 'pull-up-resistor' to a '1' that the logic can use. This can be tricky with the post-synth results as it means you'll have to track down the appropriate bits of code to insert your to_X01() call in. Maybe you can put some intermediate signals in your source with syn_keep attributes (or whatever *your* synthesiser uses) so that you can automate the inclusion of the function call with a script or something... HTH, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt ###### From: "Christian Widtmann" Newsgroups: comp.arch.fpga Subject: Re: Problem with tristate-inout-pins of PS/2-Host Date: Mon, 16 Jun 2003 12:11:24 +0200 Organization: Vienna University of Technology, Austria Lines: 14 Message-ID: References: NNTP-Posting-Host: chello062178081202.28.11.tuwien.teleweb.at X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.stueberl.de!news.netway.at!leech.it-austria.net!newsfeed01.univie.ac.at!aconews-feed.univie.ac.at!news.tuwien.ac.at!tuwien-news Xref: chonsp.franklin.ch comp.arch.fpga:29590 "Martin Thompson" schrieb im Newsbeitrag news:uptleeajt.fsf@trw.com... > You've got most of the way there - you just need to put a to_X01() > translation between your bus pin and the logic that uses it. This > will convert the 'H' on the bus from the 'pull-up-resistor' to a '1' > that the logic can use. Where would I have to put this? Into the original VHDL-code or into a file generated by synopsis' design_analyzer? Best regards..... ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: Problem with tristate-inout-pins of PS/2-Host Date: 17 Jun 2003 13:17:25 +0100 Organization: TRW Conekt Lines: 23 Sender: thompsonmj@1WVMP0J-DT Message-ID: References: NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1055852252 21673894 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.imp.ch!news.imp.ch!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:29614 "Christian Widtmann" writes: > "Martin Thompson" schrieb im Newsbeitrag > news:uptleeajt.fsf@trw.com... > > You've got most of the way there - you just need to put a to_X01() > > translation between your bus pin and the logic that uses it. This > > will convert the 'H' on the bus from the 'pull-up-resistor' to a '1' > > that the logic can use. > > Where would I have to put this? Into the original VHDL-code or into a file > generated by synopsis' design_analyzer? > Depends on which file you want to simulate - start in the original VHDL files and get that bit working forst. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt