From: nshimizu@bosei.cc.u-tokai.ac.jp (Naohiko Shimizu) Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.arch Subject: PDP11/40 Compatible CPU on an FPGA Date: 13 Jun 2003 07:45:42 GMT Organization: Tokai Univ. Computing Center(Shonan),Hiratsuka,Japan Lines: 79 Message-ID: NNTP-Posting-Host: bosei.cc.u-tokai.ac.jp Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Trace: news.cc.u-tokai.ac.jp 1055490342 84286 150.7.3.2 (13 Jun 2003 07:45:42 GMT) X-Complaints-To: usenet@cc.u-tokai.ac.jp NNTP-Posting-Date: 13 Jun 2003 07:45:42 GMT X-Newsreader: mnews [version 1.22PL4] 2000-05/28(Sun) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.media.kyoto-u.ac.jp!newsfeed.mesh.ad.jp!giga-nspixp2!news1.ttnet.ad.jp!news1.point.ne.jp!news0.ttnet.ad.jp!news01.pwd.ne.jp!150.7.3.5.MISMATCH!news.u-tokai.ac.jp!nshimizu Xref: chonsp.franklin.ch comp.arch.fpga:29552 Hi, For under graduate project, my students Mr.Iida wrote a PDP11/40 compatible CPU and now it boot Unix from an IDE hard drive. We named the CPU as POP11/40 (PDP11 On Programmable chip). Without MMU/EIS it uses only about 1700 logic cells with Altera, and with MMU/EIS it needs about 3600 logic cells. Description language of CPU is SFL and we converted to Verilog with sfl2vl. Now I placed simulation package for Icarus Verilog v0.7 on my web site. http://shimizu-lab.dt.u-tokai.ac.jp/ -------------- simulation log --------------- POP11/40 Simulation Start with disp mode= 0 Copyright 2003 Naohiko Shimizu, Yoshihiro Iida, Tokai University, Japan @rkunix.40 mem = 436 login:root #ls bin dev etc lib mnt mnt2 rkunix rkunix.40 tmp unix usr usr2 # --------------------------------------------- POP-11/40 Simulation package for Icarus Verilog Copyright (c) 2003 Naohiko Shimizu, Yoshihiro Iida, Tokai University, Japan All rights reserved. POP11/40 is a PDP11/40 compatible processor with IDE HDD interface. CPU was written with SFL and converted to Verilog with sfl2vl. When fitting to Altera FPGA, POP11/40 needs about 3600 logic cells Contents: README: this file sim-pop11: Icarus Verilog simulation script. unix: Unix V6 drive image bmem: initial boot loader reside on memory. console.in: console input strings. '7f' will terminate simulation. Makefile: makefile to run simulation AncientUnix.pdf: Unix V6 license file If you did not install Icarus Verilog at /usr/local, you may need to edit `sim-pop11'. Makefile has four simulation entries: sim-help: ./sim-pop11 +help=1 ;show help messages sim: ./sim-pop11 ;full simulation sim-regs: ./sim-pop11 +disp=2 ;full simulation with register dump sim-short:./sim-pop11 +stop=100 +disp=2 ;limited cycle simulation Full simulation takes very long time, about 140 minutes with 64 bit mode Opteron 1.4GHz and Icarus Verilog v0.7. ---------------------------------->--------------------------->> Naohiko Shimizu Department of Communications Engineering, School of Information Technology and Electronics, Tokai University 1117 Kitakaname Hiratsuka 259-1292 Japan TEL.+81-463-58-1211(ext. 4084) FAX.+81-463-58-8320 http://shimizu-lab.dt.u-tokai.ac.jp/ <<--------------------------------<-----------------------------