From: petersommerfeld@hotmail.com (Peter Sommerfeld) Newsgroups: comp.arch.fpga Subject: What's in a bitstream? Date: 10 Jun 2003 07:45:31 -0700 Organization: http://groups.google.com/ Lines: 17 Message-ID: <5c4d983.0306100645.715207af@posting.google.com> NNTP-Posting-Host: 64.235.99.34 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1055256331 16328 127.0.0.1 (10 Jun 2003 14:45:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 10 Jun 2003 14:45:31 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:29448 Has anyone figured out (or tried to) the format of the bitstream used to configure an FPGA. Obviously each vendor's, and maybe each part's, bitstream format is different. I'm curious if it just serially goes along and sets up 16x1 LUTs (in the 4-input LUT case), and then there are all the special cases for embedded RAMs, MACs, etc. I suppose by making a one-LE circuit with the LE manually placed, and then making another one-LE circuit with the LE placed one LE to the right, etc, and then diff'ing the bitstream, one could eventually determine the bitstream layout. Or maybe it is much more involved? I'm asking because I wonder how difficult it would be to write one's own synthesizer and router, if only to see if it can be done without years of man-hours invested. -- Pete ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: What's in a bitstream? Date: Tue, 10 Jun 2003 09:00:21 -0700 Organization: Xilinx,Inc Lines: 33 Message-ID: <3EE60094.F4381BF0@xilinx.com> References: <5c4d983.0306100645.715207af@posting.google.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Peter Sommerfeld Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!zen.net.uk!newsfeed.media.kyoto-u.ac.jp!spring.edu.tw!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:29423 Pete, don't even try! It is easy enough to find the LUT-bit and RAM-bit locations through a systematic search. But most configuration bits are used to control the interconnect. Take the XC2V6000: It has roughly 1 million LUT bits, and 3 million BlockRAM bits, but a total of 19 million configuration bits. That means 15 million of the 19 million config bits are used to control the interconnect structure plus various control functions. It's the old joke: "We sell interconnect, logic comes for free". Peter Alfke =============================== Peter Sommerfeld wrote: > > Has anyone figured out (or tried to) the format of the bitstream used > to configure an FPGA. Obviously each vendor's, and maybe each part's, > bitstream format is different. > > I'm curious if it just serially goes along and sets up 16x1 LUTs (in > the 4-input LUT case), and then there are all the special cases for > embedded RAMs, MACs, etc. I suppose by making a one-LE circuit with > the LE manually placed, and then making another one-LE circuit with > the LE placed one LE to the right, etc, and then diff'ing the > bitstream, one could eventually determine the bitstream layout. Or > maybe it is much more involved? > > I'm asking because I wonder how difficult it would be to write one's > own synthesizer and router, if only to see if it can be done without > years of man-hours invested. > > -- Pete ###### From: jetmarc@hotmail.com (jetmarc) Newsgroups: comp.arch.fpga Subject: Re: What's in a bitstream? Date: 10 Jun 2003 11:00:35 -0700 Organization: http://groups.google.com/ Lines: 24 Message-ID: References: <5c4d983.0306100645.715207af@posting.google.com> NNTP-Posting-Host: 80.58.13.107 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1055268036 26604 127.0.0.1 (10 Jun 2003 18:00:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 10 Jun 2003 18:00:36 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:29452 > I'm asking because I wonder how difficult it would be to write one's > own synthesizer and router, if only to see if it can be done without > years of man-hours invested. Most manufacturers give you detailed bitstream information after you signed an NDA. Even if they didn't, reverse-engineering the bitstream format is the easiest part of "roll my own toolchain". Apart from the sheer complexity of such an undergoing, you face another difficult problem: you can't estimate the timing unless you have insider information (which often is not available, not even under NDA). Timing analysis is very complex, and the manufacturer may also reserve special margins for future process changes. Even when you examine a given silicon, you can't build a reliable timing model for that series. You have to add safety margins (voiding your product for state-of-the- art designs), or reverse-engineer the manufacturers' toolchain. And last not least, the manufacturers have a big database of known problems and bugs. You are likely to oversee the same problems, and they remain unfixed until the users report those bugs to YOU (again). Your product will be inferior to the "original" unless it is employed as widely as, say, GNU G++. Marc ###### From: "Steve Casselman" Newsgroups: comp.arch.fpga References: <5c4d983.0306100645.715207af@posting.google.com> Subject: Re: What's in a bitstream? Lines: 30 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1158 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 Message-ID: NNTP-Posting-Host: 64.164.174.129 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr19.news.prodigy.com 1055275975 ST000 64.164.174.129 (Tue, 10 Jun 2003 16:12:55 EDT) NNTP-Posting-Date: Tue, 10 Jun 2003 16:12:55 EDT Organization: SBC http://yahoo.sbc.com X-UserInfo1: TSU[@IONWJWYB_XYGRNFOFTBTR\B@GXLN@GZ_GYO^BTJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Tue, 10 Jun 2003 20:12:55 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!peernews-us.colt.net!newsfeed.news2me.com!elnk-pas-nf2!elnk-nf1-atl!newsfeed.earthlink.net!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr19.news.prodigy.com.POSTED!2ac7f5fa!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:29460 I don't know much about Altera but I have learned quite a bit about the bitstream by looking at the Xilinx tool outputs. Some of the output files tell exactly where the bits are in the bitstream. You can do a design with one LUT read it in to the FPGA editor and change the LUT value. Then use the partial bitstream capability to see how the bitstream changes. Steve "Peter Sommerfeld" wrote in message news:5c4d983.0306100645.715207af@posting.google.com... > Has anyone figured out (or tried to) the format of the bitstream used > to configure an FPGA. Obviously each vendor's, and maybe each part's, > bitstream format is different. > > I'm curious if it just serially goes along and sets up 16x1 LUTs (in > the 4-input LUT case), and then there are all the special cases for > embedded RAMs, MACs, etc. I suppose by making a one-LE circuit with > the LE manually placed, and then making another one-LE circuit with > the LE placed one LE to the right, etc, and then diff'ing the > bitstream, one could eventually determine the bitstream layout. Or > maybe it is much more involved? > > I'm asking because I wonder how difficult it would be to write one's > own synthesizer and router, if only to see if it can be done without > years of man-hours invested. > > -- Pete ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: What's in a bitstream? Date: 11 Jun 2003 01:35:21 +0200 Organization: My own Private Self Lines: 104 Message-ID: <6un0gpmrpi.fsf@chonsp.franklin.ch> References: <5c4d983.0306100645.715207af@posting.google.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1055288121 575 10.0.3.2 (10 Jun 2003 23:35:21 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 10 Jun 2003 23:35:21 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:29462 petersommerfeld@hotmail.com (Peter Sommerfeld) writes: > Has anyone figured out (or tried to) the format of the bitstream used > to configure an FPGA. Obviously each vendor's, and maybe each part's, > bitstream format is different. Each chip family is different. Inside one family it is just a smaller/larger amount of bits. > I'm curious if it just serially goes along and sets up 16x1 LUTs (in > the 4-input LUT case), and then there are all the special cases for > embedded RAMs, MACs, etc. At least for Xilinx Virtex/Spartan-II/Virtex-E/Spartan-IIE (the ones I am interested in) it goes through columns of CLBs, "striping" them, into so called frames: One CLB is 48 frames of 18 (= 864) bits, of which the LUTS are 4*16 (= 64): /* . = unknown, 0..9A..F = LUT bits (inverted), XY = FF bits (true sense) */ /* Slice 1/L Slice 0/R */ /* */ /* 0 1 2 3 4 frame */ /* 012345678901234567890123456789012345678901234567 addr */ /* .------------------------------------------------ */ /* 0|................................................ */ /* 1|..X.....Y..............................Y.....X.. FFs */ /* 2|FEDCBA9876543210................0123456789ABCDEF G LUTs */ /* 3|FEDCBA9876543210................0123456789ABCDEF F LUTs */ /* 4|................................................ */ /* 5|................................................ */ /* 6|................................................ */ /* 7|................................................ */ /* 8|................................................ */ /* 9|................................................ */ /* 10|................................................ */ /* 11|................................................ */ /* 12|................................................ */ /* 13|................................................ */ /* 14|................................................ */ /* 15|................................................ */ /* 16|................................................ */ /* 17|................................................ */ /* bit addr */ For Virtex-II it seems to be 22 frames of 80 bits (computed from the bitstream sizes in the data sheet), but no further analysis made up till now (nor intended). And yes, above graphic is from the source code of my fledgling FPGA toolset/compiler project: http://neil.franklin.ch/Projects/VirtexTools/ As for what those other bits do, over 700 of them are routing, that is wiring signals from one LUT to others, the "programmable PCB" inside the FPGA. A (partial, no hex lines) sketch of routing I have at: http://neil.franklin.ch/Projects/VirtexTools/Virtex-CLB-PIPs > I suppose by making a one-LE circuit with > the LE manually placed, and then making another one-LE circuit with > the LE placed one LE to the right, etc, and then diff'ing the > bitstream, one could eventually determine the bitstream layout. Or > maybe it is much more involved? Best get yourself what docs Xilinx does give out (at least for the original Virtex, later families do not get such docs): The XAPP138 [1] and XAPP151 [2] application notes (from which above graphic was derived), and the JBits [3] Java toolset (which allows you to set/reset any chip function, not just the 64 of 864 LUT bits. [1] http://www.xilinx.com/xapp/xapp138.pdf [2] http://www.xilinx.com/xapp/xapp151.pdf [3] send mail to jbits@xilinx.com to get FTP URL and password > I'm asking because I wonder how difficult it would be to write one's > own synthesizer and router, if only to see if it can be done without > years of man-hours invested. According to my logfile, I for the first 2 milestones have entries from begin July to mid October 2002, on 43 days. If I assume average 5 hours, that is 215h. Based on that I estimate I will be able to compile minimal bitstreams at around 1000h into the project. That is about 200 days, which is about 1 man year in workdays (dropping weekends and hollidays). Due to many other time sinks, I assume this to actually happen in perhaps 2 years time. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### From: Brian Drummond Newsgroups: comp.arch.fpga Subject: Re: What's in a bitstream? Date: Wed, 11 Jun 2003 15:50:27 +0100 Lines: 32 Message-ID: <8cgeevktb0og18eh3gp737mbdtttdlcc72@4ax.com> References: <5c4d983.0306100645.715207af@posting.google.com> NNTP-Posting-Host: shapes.demon.co.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.demon.co.uk 1055342712 11337 158.152.228.158 (11 Jun 2003 14:45:12 GMT) X-Complaints-To: abuse@demon.net NNTP-Posting-Date: Wed, 11 Jun 2003 14:45:12 +0000 (UTC) X-Newsreader: Forte Agent 1.7/32.534 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!kibo.news.demon.net!news.demon.co.uk!demon!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:29500 On 10 Jun 2003 07:45:31 -0700, petersommerfeld@hotmail.com (Peter Sommerfeld) wrote: >Has anyone figured out (or tried to) the format of the bitstream used >to configure an FPGA. Obviously each vendor's, and maybe each part's, >bitstream format is different. >I'm asking because I wonder how difficult it would be to write one's >own synthesizer and router, if only to see if it can be done without >years of man-hours invested. If this is what you want to do, understanding the bitstream is actually redundant. Look into XDL, which has all the internal details of a design (placement, routing etc) in text format, with converters to/from the internal format used by Xilinx's placement and routing tools. (for synthesis, you don't need to go so far, just use EDIF) This way you could (in theory) replace parts of the Xilinx design flow - e.g. write your own placement tool which took the mapper's output (map.ncd, translated into XDL) - and maybe some other knowledge of the design, e.g. the VHDL source code - and placed logic elements according to the structure inferred from the design, thus eliminating the routing speed problems caused by "random placement". Translate the result back from XDL back into .ncd and run routing passes on it. Inspecting the XDL format of various stages of a design will give some idea of the complexity of the task ... note I'm not suggesting it's easy! - Brian