From: "Brendan Lynskey" Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Selling CPU cores Lines: 17 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Message-ID: Date: Tue, 15 Apr 2003 11:29:47 +0100 NNTP-Posting-Host: 212.56.93.10 X-Complaints-To: abuse@plus.net.uk X-Trace: stones.force9.net 1050402511 212.56.93.10 (Tue, 15 Apr 2003 11:28:31 BST) NNTP-Posting-Date: Tue, 15 Apr 2003 11:28:31 BST Organization: Customer of PlusNet Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!landlord!stones.force9.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27686 Hi. What's the position in writing an well-established type of CPU core (like a Z80) and selling it? Would I have to pay royalties to anyone? Cheers, -- Brendan Lynskey Comodo Research Lab Click on www.comodogroup.com/secure-email to keep your emails confidential with a complementary FREE personal Secure Email Certificate ###### Date: Tue, 15 Apr 2003 13:19:22 +0159 From: Igmar Palsenberg User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.3) Gecko/20030314 X-Accept-Language: en-us, en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Selling CPU cores References: In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Lines: 15 Message-ID: <3e9bee63$0$49106$e4fe514c@news.xs4all.nl> NNTP-Posting-Date: 15 Apr 2003 13:34:59 CEST NNTP-Posting-Host: 62.177.184.210 X-Trace: 1050406499 news.xs4all.nl 49106 igmar/62.177.184.210:37589 X-Complaints-To: abuse@xs4all.nl Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.telebyte.nl!newshub1.home.nl!home.nl!news2.euro.net!transit.news.xs4all.nl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27684 > Hi. > > What's the position in writing an well-established type of CPU core (like a > Z80) and selling it? That depends on patents that apply, and how you got the info. > Would I have to pay royalties to anyone? That also depends. See te above. Igmar ###### From: russelmann@hotmail.com (Rudolf Usselmann) Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Selling CPU cores Date: 15 Apr 2003 09:55:09 -0700 Organization: http://groups.google.com/ Lines: 34 Message-ID: References: NNTP-Posting-Host: 203.121.131.36 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1050425710 22139 127.0.0.1 (15 Apr 2003 16:55:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 15 Apr 2003 16:55:10 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27694 "Brendan Lynskey" wrote in message news:... > Hi. > > What's the position in writing an well-established type of CPU core (like a > Z80) and selling it? > > Would I have to pay royalties to anyone? > > Cheers, I believe it depends how old the CPU and any associated patents are. I believe the US patents last for 17 years. Not sure how it works with copyrighted instruction sets (or if that is even possible). Many very good CPU cores have already been copied and many are freely available at (www.opencores.org). Some, MIPS and ARM come to mind, are so scared of the open/free implementations of their CPUs that they fight very hard to get them removed. OpenCores has even it's own CPU IP core (Open RISC), developed completely from scratch, with it's own development tools as well (the GNU chain of course :*). I wouldn't be surprised if it soon will kick but on any commercial CPU available. -- rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Selling CPU cores Date: 16 Apr 2003 02:06:40 +0200 Organization: My own Private Self Lines: 67 Message-ID: <6ud6jn9ugf.fsf@chonsp.franklin.ch> References: NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1050451602 455 10.0.3.2 (16 Apr 2003 00:06:42 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 16 Apr 2003 00:06:42 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:27724 russelmann@hotmail.com (Rudolf Usselmann) writes: > "Brendan Lynskey" wrote in message news:... > > > > What's the position in writing an well-established type of CPU core (like a > > Z80) and selling it? > > > > Would I have to pay royalties to anyone? > > I believe it depends how old the CPU and any associated > patents are. The patents. Sales of the CPU are irrelevant. > I believe the US patents last for 17 years. 17 from granting (old law) or 20 years from handing in application (new law). I do not know exactly which patents fall under which law. Outside US it seems to be generally 17 from handing in. > Not sure how it works with copyrighted instruction sets > (or if that is even possible). Copyright only applies if you are distributing verbatim copies of an other persons work, i.e. code or documents, or chip layouts (and I assume data sets to compile to layouts). Never instruction sets. Instruction sets can not be patented per se, but specific instructions can, if they implement an new way to solving a problem. The patent actually would have to cover the way. > Some, MIPS and ARM come to mind, are so scared of the > open/free implementations of their CPUs that they fight > very hard to get them removed. MIPS is an example of patented instruction. They solved the problem of loading non-aligned words (2 word reads that are masked and shifted to make one word) in an virtual memory system (either word read may page fault) in an novel way. This required an special set of 2 separate "read 1 word and mask/shift to load partial word" instructions (so each can only fault once). This method is patented. It is impossible to implement the 2 instructions (and so the entire instruction set, and so an compatible chip) without violating this patent. Of course we today are in 2003, so any patent before 1983 (or even 1986?) is dead anyway and MIPS started in the first half of the 1980s. So their patents are running out real soon. ARM I do not know what they use to beat down competition. I would assume also an patent on something, as this is the only effective way againt an independant (from scratch, clean room) implementation. They are also mid 1980s. So also max 5 years to go, if even that. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### From: "Robert Finch" Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog References: <6ud6jn9ugf.fsf@chonsp.franklin.ch> Subject: Re: Selling CPU cores Lines: 37 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2720.3000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: <6l5na.4421$8T6.396912@news20.bellglobal.com> Date: Wed, 16 Apr 2003 00:53:21 -0400 NNTP-Posting-Host: 65.95.22.97 X-Complaints-To: abuse@sympatico.ca X-Trace: news20.bellglobal.com 1050468802 65.95.22.97 (Wed, 16 Apr 2003 00:53:22 EDT) NNTP-Posting-Date: Wed, 16 Apr 2003 00:53:22 EDT Organization: Bell Sympatico Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!news.uunet.ca!nf3.bellglobal.com!nf1.bellglobal.com!nf2.bellglobal.com!news20.bellglobal.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27754 > > > What's the position in writing an well-established type of CPU core (like a > > > Z80) and selling it? Some of the existing CPU cores aren't all that well suited to FPGA's. Better value can be obtained by creating a CPU that's designed around the characteristics of an FPGA. It's also possible to avoid a lot of patent and copyright issues by rolling your own. For instance I have an enhanced 65C02 compatible core that takes about 600 LC's and runs at 48MHz. But a reasonably capable 16 bit RISC running twice as fast would only take about 300 LC's. > > Some, MIPS and ARM come to mind, are so scared of the > > open/free implementations of their CPUs that they fight > > very hard to get them removed. It's easy to understand why. But if you're looking at an open/free implementation, viewer beware. > This method is patented. It is impossible to implement the 2 instructions > (and so the entire instruction set, and so an compatible chip) without > violating this patent. Interesting. I predict a flood of useless, mysterious instructions incorporated into CPU's so that it's impossible to claim compatibility without patent violation. > ARM I do not know what they use to beat down competition. I would Rob ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Selling CPU cores Date: 16 Apr 2003 21:06:40 +0200 Organization: My own Private Self Lines: 34 Message-ID: <6usmsiuurj.fsf@chonsp.franklin.ch> References: <6ud6jn9ugf.fsf@chonsp.franklin.ch> <6l5na.4421$8T6.396912@news20.bellglobal.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1050520002 433 10.0.3.2 (16 Apr 2003 19:06:42 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 16 Apr 2003 19:06:42 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:27766 "Robert Finch" writes: > > This method is patented. It is impossible to implement the 2 instructions > > (and so the entire instruction set, and so an compatible chip) without > > violating this patent. > > Interesting. I predict a flood of useless, mysterious instructions > incorporated into CPU's so that it's impossible to claim compatibility > without patent violation. Problem here: If they are really useless programmers/compilers will ignore them (see how some x86 instructions are avoided by modern x86 compilers, because they are slow). So an "half compatible" clone without them can still be successfull. So you need to actually find some new way, to solve an problem, that makes it possible to drop the normal instructions that could also solve this problem. Such specialists like allignment handling, or memory management, or interrupt/bus control are candidates for this. Trying to reinvent such wheels, not for more roundness, but just for being different, is not easy, if performance is not to suffer. And of course any new architecture, without existing code libraries (the main reason to clone anything), has to compete. And there open architectures will win easily over such deliberately broken stuff. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today?