From: "valentin tihomirov" Newsgroups: comp.arch.fpga Subject: request for simple UART Date: Mon, 14 Apr 2003 12:58:47 +0300 Lines: 10 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2720.3000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 NNTP-Posting-Host: 80.235.104.171 Message-ID: <3e9a865c_2@news.estpak.ee> X-Trace: news.estpak.ee 1050314332 80.235.104.171 (14 Apr 2003 12:58:52 +0300) X-Complaints-To: usenet@estpak.ee Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.gamma.ru!Gamma.RU!comstar.ru!teleglobe.net!news.estpak.ee!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27608 I have an idea to implement all digital logic of my circuit into a CPLD. The only doubt is external UART. I know, additional UART is a big pain, currently I use tl16c750. I think that a price of external uart is the same or greater than an average CPLD chip. All IP cores suggested by google are complex, ie with FIFOs and flow control. I would be satisfied with the 8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, TI, RI flags and a hardwired frecuency. Any suggestions. ###### From: "Valeria Dal Monte" Newsgroups: comp.arch.fpga References: <3e9a865c_2@news.estpak.ee> Subject: Re: request for simple UART Lines: 18 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Mon, 14 Apr 2003 13:28:46 GMT NNTP-Posting-Host: 151.30.8.29 X-Complaints-To: abuse@libero.it X-Trace: twister2.libero.it 1050326926 151.30.8.29 (Mon, 14 Apr 2003 15:28:46 MET DST) NNTP-Posting-Date: Mon, 14 Apr 2003 15:28:46 MET DST Organization: [Infostrada] Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!nntp.infostrada.it!twister2.libero.it.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27622 "valentin tihomirov" ha scritto nel messaggio news:3e9a865c_2@news.estpak.ee... > I have an idea to implement all digital logic of my circuit into a CPLD. The > only doubt is external UART. I know, additional UART is a big pain, > currently I use tl16c750. I think that a price of external uart is the same > or greater than an average CPLD chip. All IP cores suggested by google are > complex, ie with FIFOs and flow control. I would be satisfied with the > 8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, TI, > RI flags and a hardwired frecuency. Any suggestions. I think a such non-programmable UART is very simple to implement and very inexpensive in terms of macrocells, likely less than 32. ###### X-Abuse-Report: abuse@teranews.com Message-ID: <4b32cc45b5325cde65440af339380bee@news.teranews.com> Date: Mon, 14 Apr 2003 14:46:49 GMT Lines: 30 From: Rene Tschaggelar User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-us, en, de-ch MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: request for simple UART References: <3e9a865c_2@news.estpak.ee> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!skynet.be!skynet.be!newsfeed-east.nntpserver.com!nntpserver.com!news.teranews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27602 Valeria Dal Monte wrote: > "valentin tihomirov" ha scritto nel messaggio > news:3e9a865c_2@news.estpak.ee... > >>I have an idea to implement all digital logic of my circuit into a CPLD. > > The >>only doubt is external UART. I know, additional UART is a big pain, >>currently I use tl16c750. I think that a price of external uart is the > same >>or greater than an average CPLD chip. All IP cores suggested by google are >>complex, ie with FIFOs and flow control. I would be satisfied with the >>8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, > >>RI flags and a hardwired frecuency. Any suggestions. > > I think a such non-programmable UART is very simple to implement > and very inexpensive in terms of macrocells, likely less than 32. This may be impossible. A UART uses oversampling and taking the majority. For 8 databits plus 1 startbit and 1 stopbit at 4 times oversampling the shiftregister is 40 bits long. Add 2 bytes for transmission and 2 bytes for reception and you're at 64 bits. Then add a few macrocells for the logic. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net ###### From: Jennifer Jenkins Newsgroups: comp.arch.fpga Subject: Re: request for simple UART Date: Mon, 14 Apr 2003 09:31:56 -0600 Organization: Xilinx, Inc. Lines: 15 Message-ID: <3E9AD46C.E28351CE@xilinx.com> References: <3e9a865c_2@news.estpak.ee> NNTP-Posting-Host: 149.199.109.3 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.79 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en To: valentin tihomirov Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27605 Check out these two reference designs from the Xilinx CPLD team: XAPP341: http://www.xilinx.com/xapp/xapp341.pdf XAPP345: http://www.xilinx.com/xapp/xapp345.pdf valentin tihomirov wrote: > I have an idea to implement all digital logic of my circuit into a CPLD. The > only doubt is external UART. I know, additional UART is a big pain, > currently I use tl16c750. I think that a price of external uart is the same > or greater than an average CPLD chip. All IP cores suggested by google are > complex, ie with FIFOs and flow control. I would be satisfied with the > 8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, TI, > RI flags and a hardwired frecuency. Any suggestions. ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: request for simple UART Date: Mon, 14 Apr 2003 09:26:40 -0700 Organization: Xilinx,Inc Lines: 36 Message-ID: <3E9AE140.34CE3F78@xilinx.com> References: <3e9a865c_2@news.estpak.ee> <4b32cc45b5325cde65440af339380bee@news.teranews.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Rene Tschaggelar Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!canoe.uoregon.edu!arclight.uoregon.edu!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27603 UARTS only oversample the start bit. Once they thus found the center of the bit, they sample open-loop the remaining 8 or 9 bits. Then resynchronize on the next start bit, etc. Peter Alfke Rene Tschaggelar wrote: > > Valeria Dal Monte wrote: > > "valentin tihomirov" ha scritto nel messaggio > > news:3e9a865c_2@news.estpak.ee... > > > >>I have an idea to implement all digital logic of my circuit into a CPLD. > > > > The > >>only doubt is external UART. I know, additional UART is a big pain, > >>currently I use tl16c750. I think that a price of external uart is the > > same > >>or greater than an average CPLD chip. All IP cores suggested by google are > >>complex, ie with FIFOs and flow control. I would be satisfied with the > >>8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, > > > >>RI flags and a hardwired frecuency. Any suggestions. > > > > I think a such non-programmable UART is very simple to implement > > and very inexpensive in terms of macrocells, likely less than 32. > > This may be impossible. A UART uses oversampling and taking the > majority. For 8 databits plus 1 startbit and 1 stopbit at 4 times > oversampling the shiftregister is 40 bits long. Add 2 bytes for > transmission and 2 bytes for reception and you're at 64 bits. > Then add a few macrocells for the logic. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net ###### Message-ID: <3E9B5930.D5C331BA@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: request for simple UART References: <3e9a865c_2@news.estpak.ee> <4b32cc45b5325cde65440af339380bee@news.teranews.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 59 Date: Tue, 15 Apr 2003 00:55:48 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1050368148 68.15.41.165 (Mon, 14 Apr 2003 20:55:48 EDT) NNTP-Posting-Date: Mon, 14 Apr 2003 20:55:48 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27665 Not quite. A UART typically samples the start bit at 16x clock, then from the estimated center of the start bit (determined by a count of 8 clocks from when the start goes active), the rest of the bits are simply sampled at the center of the bit times, ie multiples of 16 clocks from the center of the start bit. It can be accomplished with a 4 bit counter for the bit timing (preload with 8), a bit counter, and a shift register with just enough bits to hold the intended data bits, and parity if desired. The shift register gets enabled by the bit counter terminal count. A simple state machine to hold the bit counter reset (to 8) until the start bit is detected and again after the stop bit rounds the design out. Unless you have a 16x recieve clock available, you'll also need an accumulator to generate the 16x UART clock from your system clock. All you need then, is an 8 bit shift register, a mod 16 counter, a 4bit counter and a few extra flops for the state machine. Plus an accumulator if you need to generate the 16 x clock. Rene Tschaggelar wrote: > Valeria Dal Monte wrote: > > "valentin tihomirov" ha scritto nel messaggio > > news:3e9a865c_2@news.estpak.ee... > > > >>I have an idea to implement all digital logic of my circuit into a CPLD. > > > > The > >>only doubt is external UART. I know, additional UART is a big pain, > >>currently I use tl16c750. I think that a price of external uart is the > > same > >>or greater than an average CPLD chip. All IP cores suggested by google are > >>complex, ie with FIFOs and flow control. I would be satisfied with the > >>8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, > > > >>RI flags and a hardwired frecuency. Any suggestions. > > > > I think a such non-programmable UART is very simple to implement > > and very inexpensive in terms of macrocells, likely less than 32. > > This may be impossible. A UART uses oversampling and taking the > majority. For 8 databits plus 1 startbit and 1 stopbit at 4 times > oversampling the shiftregister is 40 bits long. Add 2 bytes for > transmission and 2 bytes for reception and you're at 64 bits. > Then add a few macrocells for the logic. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### X-Abuse-Report: abuse@teranews.com Message-ID: <5bc89dade4129a475472c171ddcbeb60@news.teranews.com> Date: Tue, 15 Apr 2003 09:50:23 GMT Lines: 31 From: Rene Tschaggelar User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-us, en, de-ch MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: request for simple UART References: <3e9a865c_2@news.estpak.ee> <4b32cc45b5325cde65440af339380bee@news.teranews.com> <3E9B5930.D5C331BA@andraka.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.gamma.ru!Gamma.RU!newsfeed-east.nntpserver.com!nntpserver.com!news.teranews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27652 Thanks. That was interesting. This makes the whole byte transmission very sensitive to the startbit edge then. And it also illuminates the requirement to have he idle level at the stop level. There are some RS485 implementations that cut the stop bit off. Such as using the TxBufferEmpty to reload the data and using the TxShiftEmpty for the disabling of the driver. Unless a timer is used to add the stopbit, it will be cut off. Rene Ray Andraka wrote: > Not quite. A UART typically samples the start bit at 16x clock, then from the > estimated center of the start bit (determined by a count of 8 clocks from when > the start goes active), the rest of the bits are simply sampled at the center of > the bit times, ie multiples of 16 clocks from the center of the start bit. It > can be accomplished with a 4 bit counter for the bit timing (preload with 8), a > bit counter, and a shift register with just enough bits to hold the intended > data bits, and parity if desired. The shift register gets enabled by the bit > counter terminal count. A simple state machine to hold the bit counter reset > (to 8) until the start bit is detected and again after the stop bit rounds the > design out. Unless you have a 16x recieve clock available, you'll also need an > accumulator to generate the 16x UART clock from your system clock. All you need > then, is an 8 bit shift register, a mod 16 counter, a 4bit counter and a few > extra flops for the state machine. Plus an accumulator if you need to generate > the 16 x clock. [ snip ] ###### Message-ID: <3E9C02D6.62998066@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: request for simple UART References: <3e9a865c_2@news.estpak.ee> <4b32cc45b5325cde65440af339380bee@news.teranews.com> <3E9B5930.D5C331BA@andraka.com> <5bc89dade4129a475472c171ddcbeb60@news.teranews.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 53 Date: Tue, 15 Apr 2003 12:59:35 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1050411575 68.15.41.165 (Tue, 15 Apr 2003 08:59:35 EDT) NNTP-Posting-Date: Tue, 15 Apr 2003 08:59:35 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27656 Yes, the transmission is sensitive to the timing of the start bit. The start bit detection can be made more robust by resetting the count clock counter whenever the input is a '1', that way it ignores false edges, but it also is not foolproof. If there is a stop bit, the state machine has to wait for the stop bit before returning to the idle state so that it doesn't trip the start again in the case where the last data bit is a '0'. In cases where there is no stop bit, you still need to delay a bit time before looking again for the start bit to avoid capturing the tail of the last bit. Rene Tschaggelar wrote: > Thanks. > That was interesting. > This makes the whole byte transmission very sensitive to the > startbit edge then. And it also illuminates the requirement > to have he idle level at the stop level. > There are some RS485 implementations that cut the stop bit off. > Such as using the TxBufferEmpty to reload the data > and using the TxShiftEmpty for the disabling of the driver. > Unless a timer is used to add the stopbit, it will be cut off. > > Rene > > Ray Andraka wrote: > > Not quite. A UART typically samples the start bit at 16x clock, then from the > > estimated center of the start bit (determined by a count of 8 clocks from when > > the start goes active), the rest of the bits are simply sampled at the center of > > the bit times, ie multiples of 16 clocks from the center of the start bit. It > > can be accomplished with a 4 bit counter for the bit timing (preload with 8), a > > bit counter, and a shift register with just enough bits to hold the intended > > data bits, and parity if desired. The shift register gets enabled by the bit > > counter terminal count. A simple state machine to hold the bit counter reset > > (to 8) until the start bit is detected and again after the stop bit rounds the > > design out. Unless you have a 16x recieve clock available, you'll also need an > > accumulator to generate the 16x UART clock from your system clock. All you need > > then, is an 8 bit shift register, a mod 16 counter, a 4bit counter and a few > > extra flops for the state machine. Plus an accumulator if you need to generate > > the 16 x clock. > > [ snip ] -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### X-Abuse-Report: abuse@teranews.com Message-ID: <4b18b87f18183d5aa796a6faa497204d@news.teranews.com> Date: Tue, 15 Apr 2003 14:21:54 GMT Lines: 49 From: Rene Tschaggelar User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-us, en, de-ch MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: request for simple UART References: <3e9a865c_2@news.estpak.ee> <4b32cc45b5325cde65440af339380bee@news.teranews.com> <3E9B5930.D5C331BA@andraka.com> <5bc89dade4129a475472c171ddcbeb60@news.teranews.com> <3E9C02D6.62998066@andraka.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!newsfeed-east.nntpserver.com!nntpserver.com!news.teranews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27642 Makes sense. Usual UARTS never offered the option of not having a stopbit, AFAIR. Rene Ray Andraka wrote: > Yes, the transmission is sensitive to the timing of the start bit. The start bit > detection can be made more robust by resetting the count clock counter whenever the > input is a '1', that way it ignores false edges, but it also is not foolproof. If > there is a stop bit, the state machine has to wait for the stop bit before returning > to the idle state so that it doesn't trip the start again in the case where the last > data bit is a '0'. In cases where there is no stop bit, you still need to delay a > bit time before looking again for the start bit to avoid capturing the tail of the > last bit. > > Rene Tschaggelar wrote: > >>Thanks. >>That was interesting. >>This makes the whole byte transmission very sensitive to the >>startbit edge then. And it also illuminates the requirement >>to have he idle level at the stop level. >>There are some RS485 implementations that cut the stop bit off. >>Such as using the TxBufferEmpty to reload the data >>and using the TxShiftEmpty for the disabling of the driver. >>Unless a timer is used to add the stopbit, it will be cut off. >> >>Rene >> >>Ray Andraka wrote: >> >>>Not quite. A UART typically samples the start bit at 16x clock, then from the >>>estimated center of the start bit (determined by a count of 8 clocks from when >>>the start goes active), the rest of the bits are simply sampled at the center of >>>the bit times, ie multiples of 16 clocks from the center of the start bit. It >>>can be accomplished with a 4 bit counter for the bit timing (preload with 8), a >>>bit counter, and a shift register with just enough bits to hold the intended >>>data bits, and parity if desired. The shift register gets enabled by the bit >>>counter terminal count. A simple state machine to hold the bit counter reset >>>(to 8) until the start bit is detected and again after the stop bit rounds the >>>design out. Unless you have a 16x recieve clock available, you'll also need an >>>accumulator to generate the 16x UART clock from your system clock. All you need >>>then, is an 8 bit shift register, a mod 16 counter, a 4bit counter and a few >>>extra flops for the state machine. Plus an accumulator if you need to generate >>>the 16 x clock. >> >>[ snip ] ###### NNTP-Posting-Date: Tue, 15 Apr 2003 09:19:13 -0500 From: Newsgroups: comp.arch.fpga Subject: Re: request for simple UART Date: Tue, 15 Apr 2003 09:23:46 -0500 References: <3e9a865c_2@news.estpak.ee> <4b32cc45b5325cde65440af339380bee@news.teranews.com> <3E9B5930.D5C331BA@andraka.com> X-Newsreader: MicroPlanet Gravity v2.60 Message-ID: Lines: 20 NNTP-Posting-Host: 209.44.47.151 X-Trace: sv3-fwIqirenuWru2stqCgITUMI49NpvM4IAPL1AzsGBk3HY0wR5T1R8Ap/VOa3BsnrFoGKhfxOytIv6Zib!olfNVS5r1VTYARJuwDMBbaXF6dgTMH1v6Dao9FAUyzj9BI7JCqOewdsilMgxW9wsgB5OIUZuCrrU!NvxZx9aug2j0F31+b6gS X-Complaints-To: abuse@speakeasy.net X-DMCA-Complaints-To: abuse@speakeasy.net X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!small1.nntp.aus1.giganews.com!nntp.giganews.com!nntp3.aus1.giganews.com!nntp.speakeasy.net!news.speakeasy.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27693 Hello, In article <3E9B5930.D5C331BA@andraka>, ray@andraka says... > Not quite. A UART typically samples the start bit at 16x clock, then from the > estimated center of the start bit (determined by a count of 8 clocks from when > the start goes active), the rest of the bits are simply sampled at the center of > the bit times, ie multiples of 16 clocks from the center of the start bit. Is this the only technique used? Sorry if this seems naive, but I've frequently seen the term "vote logic" or "majority detector" used in conjunction with UARTs(even in the TI literature for the UART the OP mentioned). I was always under the impression that the bits are sampled at 16x and the bit is given the majority value. I guess this leads to another interesting question: Any easy way to do the majority detection logic, or is one forced to eat the logic needed for all the comparators? Regards, S.R. ###### X-Abuse-Report: abuse@teranews.com Message-ID: <1c61076db9fd7b1cd8382faa6f9cfe7b@news.teranews.com> Date: Tue, 15 Apr 2003 14:24:15 GMT Lines: 24 From: Rene Tschaggelar User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-us, en, de-ch MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: request for simple UART References: <3e9a865c_2@news.estpak.ee> <4b32cc45b5325cde65440af339380bee@news.teranews.com> <3E9B5930.D5C331BA@andraka.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!newsfeed-east.nntpserver.com!nntpserver.com!news.teranews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27668 invalid@invalid.com wrote: > Hello, > > In article <3E9B5930.D5C331BA@andraka>, ray@andraka says... > >>Not quite. A UART typically samples the start bit at 16x clock, then from the >>estimated center of the start bit (determined by a count of 8 clocks from when >>the start goes active), the rest of the bits are simply sampled at the center of >>the bit times, ie multiples of 16 clocks from the center of the start bit. > > > Is this the only technique used? Sorry if this seems naive, but I've > frequently seen the term "vote logic" or "majority detector" used in > conjunction with UARTs(even in the TI literature for the UART the OP > mentioned). I was always under the impression that the bits are sampled > at 16x and the bit is given the majority value. I was under the same impression (majority vote) after having read the description of the 8250 and/or 16550 about 15 years back. Rene ###### From: russelmann@hotmail.com (Rudolf Usselmann) Newsgroups: comp.arch.fpga Subject: Re: request for simple UART Date: 15 Apr 2003 10:00:02 -0700 Organization: http://groups.google.com/ Lines: 18 Message-ID: References: <3e9a865c_2@news.estpak.ee> NNTP-Posting-Host: 203.121.131.36 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1050426003 22320 127.0.0.1 (15 Apr 2003 17:00:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 15 Apr 2003 17:00:03 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27698 "valentin tihomirov" wrote in message news:<3e9a865c_2@news.estpak.ee>... > I have an idea to implement all digital logic of my circuit into a CPLD. The > only doubt is external UART. I know, additional UART is a big pain, > currently I use tl16c750. I think that a price of external uart is the same > or greater than an average CPLD chip. All IP cores suggested by google are > complex, ie with FIFOs and flow control. I would be satisfied with the > 8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, TI, > RI flags and a hardwired frecuency. Any suggestions. Try www.opencores.org, there must be half a dozen different flavors of uarts ... Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ###### Message-ID: <3E9C711E.1804@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: request for simple UART References: <3e9a865c_2@news.estpak.ee> <4b32cc45b5325cde65440af339380bee@news.teranews.com> <3E9B5930.D5C331BA@andraka.com> <1c61076db9fd7b1cd8382faa6f9cfe7b@news.teranews.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 43 Date: Wed, 16 Apr 2003 08:52:46 +1200 NNTP-Posting-Host: 203.79.102.47 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1050439954 203.79.102.47 (Wed, 16 Apr 2003 08:52:34 NZST) NNTP-Posting-Date: Wed, 16 Apr 2003 08:52:34 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!proxad.net!proxad.net!newshosting.com!news-xfer2.atl.newshosting.com!216.65.3.53.MISMATCH!news-out.spamkiller.net!propagator2-maxim!news-in.spamkiller.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27674 Rene Tschaggelar wrote: > > invalid@invalid.com wrote: > > Hello, > > > > In article <3E9B5930.D5C331BA@andraka>, ray@andraka says... > > > >>Not quite. A UART typically samples the start bit at 16x clock, then from the > >>estimated center of the start bit (determined by a count of 8 clocks from when > >>the start goes active), the rest of the bits are simply sampled at the center of > >>the bit times, ie multiples of 16 clocks from the center of the start bit. > > > > > > Is this the only technique used? Sorry if this seems naive, but I've > > frequently seen the term "vote logic" or "majority detector" used in > > conjunction with UARTs(even in the TI literature for the UART the OP > > mentioned). I was always under the impression that the bits are sampled > > at 16x and the bit is given the majority value. > > I was under the same impression (majority vote) after having read > the description of the 8250 and/or 16550 about 15 years back. The 80C51 uses 3 slot sampling, and because the dats is serial, you only need one vote block. In the simplest form, this is a gated saturating 2 bit counter. Data into the shift register is from this filtering. 16x seems mainly historical, and newer UARTS and uC allow for this to be reduced. 'Good' UART design is non trivial, you should sample the START bit at 0.5T, to confirm it is not noise, and also reset the start bit sampler NOT at the end of the stop bit, but in the centre of the stop bit. A holding buffer is also usually needed, unless your app can guarantee it only reads/writes the shift registers in their narrow valid & static time slots. Some UARTs allow fractional stop bits on TX. -jg ###### Message-ID: <3E9C7BF4.1414947@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: request for simple UART References: <3e9a865c_2@news.estpak.ee> <4b32cc45b5325cde65440af339380bee@news.teranews.com> <3E9B5930.D5C331BA@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 42 Date: Tue, 15 Apr 2003 21:36:20 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1050442580 68.15.41.165 (Tue, 15 Apr 2003 17:36:20 EDT) NNTP-Posting-Date: Tue, 15 Apr 2003 17:36:20 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:27649 Some have it, some don't. The ones I am aware of that do have it look at a 3 chip window around the sample point. That can be accomplished using a simple 3 tap boxcar filter and thresholding it (real simple filter since the input is only one bit) before the data goes into the shift register as well as the start bit detect logic. You'll need to adjust the sample point to match. If your signal is clean, this is not necessary, as it is essentially just a glitch filter. invalid@invalid.com wrote: > Hello, > > In article <3E9B5930.D5C331BA@andraka>, ray@andraka says... > > Not quite. A UART typically samples the start bit at 16x clock, then from the > > estimated center of the start bit (determined by a count of 8 clocks from when > > the start goes active), the rest of the bits are simply sampled at the center of > > the bit times, ie multiples of 16 clocks from the center of the start bit. > > Is this the only technique used? Sorry if this seems naive, but I've > frequently seen the term "vote logic" or "majority detector" used in > conjunction with UARTs(even in the TI literature for the UART the OP > mentioned). I was always under the impression that the bits are sampled > at 16x and the bit is given the majority value. > > I guess this leads to another interesting question: Any easy way to do > the majority detection logic, or is one forced to eat the logic needed > for all the comparators? > > Regards, > S.R. -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759