From: "Peter C. Wallace" Newsgroups: comp.arch.fpga Subject: Cheapest Spartan II/IIE configuration flash EEPROM! Date: Mon, 17 Mar 2003 13:09:48 -0800 Organization: Posted via Supernews, http://www.supernews.com Message-ID: User-Agent: Pan/0.11.2 (Unix) Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: ALL X-Complaints-To: abuse@supernews.com Lines: 25 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!teaser.fr!freenix!sn-xit-02!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:26770 I just tested sucessfully a very simple and inexpensive serial Flash EEPROM configuration device for SpartanII and IIE 100K gate or smaller. I was using a PIC with a serial EEPROM before but with this specific chip all thats needed is one inverter from /SYSRESET to SYSRESET needed to generate falling /CS edge for the flash. Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) Connections: FLASH DI = TIED HIGH FLASH SCLK = FPGA CCLK FLASH DO = FPGA D0 FLASH /RESET = /SYSRESET = FPGA /PROGRAM FLASH /CS = SYSRESET (note inversion) FLASH /WP = /SYSRESET FPGA configuration set for master slave mode. This works because the 45LF010 has a read command of FF (DI tied high) and supports sequential bit readout.What happens is the first config clocks shift in a FF command (read) and an 1FFFF address. Subsequent clocks read the data from 1FFFF,0,1, etc etc PCW ###### Message-ID: <3E763BDA.5E7A@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Cheapest Spartan II/IIE configuration flash EEPROM! References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 32 Date: Tue, 18 Mar 2003 09:19:22 +1200 NNTP-Posting-Host: 203.79.98.179 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1047935952 203.79.98.179 (Tue, 18 Mar 2003 09:19:12 NZST) NNTP-Posting-Date: Tue, 18 Mar 2003 09:19:12 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!out.nntp.be!propagator2-SanJose!in.nntp.be!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:26763 Peter C. Wallace wrote: > > I just tested sucessfully a very simple and inexpensive serial > Flash EEPROM configuration device for SpartanII and IIE 100K gate or > smaller. I was using a PIC with a serial EEPROM before but with this > specific chip all thats needed is one inverter from /SYSRESET to > SYSRESET needed to generate falling /CS edge for the flash. > > Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) > > Connections: > > FLASH DI = TIED HIGH > FLASH SCLK = FPGA CCLK > FLASH DO = FPGA D0 > FLASH /RESET = /SYSRESET = FPGA /PROGRAM > FLASH /CS = SYSRESET (note inversion) > FLASH /WP = /SYSRESET > > FPGA configuration set for master slave mode. This works because the > 45LF010 has a read command of FF (DI tied high) and supports sequential > bit readout.What happens is the first config clocks shift in a FF command > (read) and an 1FFFF address. Subsequent clocks read the data from > 1FFFF,0,1, etc etc Very clever - so you just need careful file alignment to go ? IIRC this family also has bigger siblings, also in SO8 Q: why is WP tied to sysreset, and not disabled ? What about ISP of the 45LF, did you try that ? -jg ###### From: "Peter C. Wallace" Newsgroups: comp.arch.fpga Subject: Re: Cheapest Spartan II/IIE configuration flash EEPROM! Date: Mon, 17 Mar 2003 13:36:02 -0800 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <3E763BDA.5E7A@designtools.co.nz> User-Agent: Pan/0.11.2 (Unix) Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: "Jim Granville" X-Complaints-To: abuse@supernews.com Lines: 46 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!cox.net!sn-xit-02!sn-xit-04!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:26769 On Mon, 17 Mar 2003 13:19:22 -0800, Jim Granville wrote: > Peter C. Wallace wrote: >> >> I just tested sucessfully a very simple and inexpensive serial Flash >> EEPROM configuration device for SpartanII and IIE 100K gate or smaller. >> I was using a PIC with a serial EEPROM before but with this specific >> chip all thats needed is one inverter from /SYSRESET to SYSRESET needed >> to generate falling /CS edge for the flash. >> >> Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) >> >> Connections: >> >> FLASH DI = TIED HIGH >> FLASH SCLK = FPGA CCLK >> FLASH DO = FPGA D0 >> FLASH /RESET = /SYSRESET = FPGA /PROGRAM FLASH /CS = SYSRESET (note >> inversion) FLASH /WP = /SYSRESET >> >> FPGA configuration set for master slave mode. This works because the >> 45LF010 has a read command of FF (DI tied high) and supports sequential >> bit readout.What happens is the first config clocks shift in a FF >> command (read) and an 1FFFF address. Subsequent clocks read the data >> from 1FFFF,0,1, etc etc > > Very clever - so you just need careful file alignment to go ? File alignment is not picky because the FPGA does nothing with the bitstream until the sync word is read > IIRC this family also has bigger siblings, also in SO8 Unfortunately they have a read command of 03 instead of FF, so they will work but need more help to get started > Q: why is WP tied to sysreset, and not disabled ? What about ISP of the WP should probably be tied to a pulldown resistor and brought out to the ISP connector. > 45LF, did you try that ? -jg Not yet but it should be easy, weve done ISP with the same chip using a PIC as a helper ###### From: "Markus Meng" Newsgroups: comp.arch.fpga References: <3E763BDA.5E7A@designtools.co.nz> Subject: Re: Cheapest Spartan II/IIE configuration flash EEPROM! Date: Tue, 18 Mar 2003 10:47:29 -0000 Lines: 51 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 NNTP-Posting-Host: 80.254.166.87 Message-ID: <3e76ebf1_4@corp.newsgroups.com> X-Trace: corp.newsgroups.com 1047981041 80.254.166.87 (18 Mar 2003 03:50:41 -0600) X-Comments: This message was posted through Newsfeeds.com X-Comments2: IMPORTANT: Newsfeeds.com does not condone, nor support, spam or any illegal or copyrighted postings. X-Comments3: IMPORTANT: Under NO circumstances will postings containing illegal or copyrighted material through this service be tolerated!! X-Report: Please report illegal or inappropriate use to X-Abuse-Info: Please be sure to forward a copy of ALL headers, INCLUDING the body (DO NOT SEND ATTACHMENTS) Organization: Newsfeeds.com http://www.newsfeeds.com 100,000+ UNCENSORED Newsgroups. Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!l-out.nntp.be!corp.newsgroups.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:26798 It's all done, allready. You can simply take the Xilinx download cable type III, write an spi driver and flash your serial data flash. That's exactly what I do in my systems. However I use the 2MBit version. You will get up to 4..8Mbit ~2US$ that hat ISP capability.... If someone is interested I can help, however the knowledge is not free, since I did invest some time to make it working ... markus "Jim Granville" schrieb im Newsbeitrag news:3E763BDA.5E7A@designtools.co.nz... > Peter C. Wallace wrote: > > > > I just tested sucessfully a very simple and inexpensive serial > > Flash EEPROM configuration device for SpartanII and IIE 100K gate or > > smaller. I was using a PIC with a serial EEPROM before but with this > > specific chip all thats needed is one inverter from /SYSRESET to > > SYSRESET needed to generate falling /CS edge for the flash. > > > > Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) > > > > Connections: > > > > FLASH DI = TIED HIGH > > FLASH SCLK = FPGA CCLK > > FLASH DO = FPGA D0 > > FLASH /RESET = /SYSRESET = FPGA /PROGRAM > > FLASH /CS = SYSRESET (note inversion) > > FLASH /WP = /SYSRESET > > > > FPGA configuration set for master slave mode. This works because the > > 45LF010 has a read command of FF (DI tied high) and supports sequential > > bit readout.What happens is the first config clocks shift in a FF command > > (read) and an 1FFFF address. Subsequent clocks read the data from > > 1FFFF,0,1, etc etc > > Very clever - so you just need careful file alignment to go ? > > IIRC this family also has bigger siblings, also in SO8 > > Q: why is WP tied to sysreset, and not disabled ? > What about ISP of the 45LF, did you try that ? > -jg -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =----- ###### From: "Tobias Stumber" Newsgroups: comp.arch.fpga Subject: Re: Cheapest Spartan II/IIE configuration flash EEPROM! Date: Wed, 19 Mar 2003 16:57:58 +0100 Organization: Robert Bosch GmbH Lines: 38 Sender: UNKNOWN@lrpc02837.lr.de.bosch.com Message-ID: References: Reply-To: "Tobias Stumber" NNTP-Posting-Host: lrpc02837.lr.de.bosch.com X-Trace: ns2.fe.internet.bosch.com 1048089479 2828 133.65.37.45 (19 Mar 2003 15:57:59 GMT) X-Complaints-To: usenet@internet.bosch.com NNTP-Posting-Date: 19 Mar 2003 15:57:59 GMT X-Priority: 3 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MSMail-Priority: Normal Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!peernews3.colt.net!news0.de.colt.net!news1.boschrexroth.de!news1.fe.internet.bosch.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:26824 Wouldn't FLASH /RESET = FPGA /INIT FLASH /CE = FPGA DONE work without an inverter (and a /sysreset) or will the FLASH CE/ falling edge ignored while FLASH /RST is asserted ? Regards, Tobias "Peter C. Wallace" wrote in message news:pan.2003.03.17.13.09.48.115606.23961@freeby.mesanet.com... > I just tested sucessfully a very simple and inexpensive serial > Flash EEPROM configuration device for SpartanII and IIE 100K gate or > smaller. I was using a PIC with a serial EEPROM before but with this > specific chip all thats needed is one inverter from /SYSRESET to > SYSRESET needed to generate falling /CS edge for the flash. > > > Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) > > Connections: > > FLASH DI = TIED HIGH > FLASH SCLK = FPGA CCLK > FLASH DO = FPGA D0 > FLASH /RESET = /SYSRESET = FPGA /PROGRAM > FLASH /CS = SYSRESET (note inversion) > FLASH /WP = /SYSRESET > > FPGA configuration set for master slave mode. This works because the > 45LF010 has a read command of FF (DI tied high) and supports sequential > bit readout.What happens is the first config clocks shift in a FF command > (read) and an 1FFFF address. Subsequent clocks read the data from > 1FFFF,0,1, etc etc > > PCW ###### From: Peter Wallace Newsgroups: comp.arch.fpga Subject: Re: Cheapest Spartan II/IIE configuration flash EEPROM! Date: Wed, 19 Mar 2003 20:15:14 -0800 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: User-Agent: Pan/0.11.4 (Unix) Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Comment-To: "Tobias Stumber" X-Complaints-To: abuse@supernews.com Lines: 19 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:26845 On Wed, 19 Mar 2003 07:57:58 -0800, Tobias Stumber wrote: > Wouldn't > FLASH /RESET = FPGA /INIT > FLASH /CE = FPGA DONE > work without an inverter (and a /sysreset) or will the FLASH CE/ falling > edge ignored while FLASH /RST is asserted ? > > Regards, Tobias Possibly but I happened to have /reset and reset available... As someone else mentioned, it is possible to use the larger (up to 8 and maybe 16 mbit) 25 series SST serial flash chips but you then need a GAL or something to generate the initial 03 read command that those chips require. The GAL could also function as the ISP interface. If you wanted the smallest helper chip, a sop8 PIC (~$.80) will do... PCW