From: "Stamatis Sotiropoulos" Newsgroups: comp.arch.fpga Subject: PCB Design for a Xilinx Spartan-II FPGA Date: Tue, 18 Feb 2003 15:54:13 +0200 Organization: National Technical University of Athens, Greece Lines: 10 Message-ID: NNTP-Posting-Host: kozani.mhl.tuc.gr X-Trace: ulysses.noc.ntua.gr 1045576433 49448 147.27.3.78 (18 Feb 2003 13:53:53 GMT) X-Complaints-To: usenet@ulysses.noc.ntua.gr NNTP-Posting-Date: Tue, 18 Feb 2003 13:53:53 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator2-SanJose!in.nntp.be!news.grnet.gr!news.ntua.gr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25915 Hi all, I am designing a PCB using an XC2S100 FPGA. Does anyone know where I can find design considerations for this PCB, such powering, bypass capasitors, etc. Is there something special I must pay attention to? Thanks you in advance, Stamatis ###### Reply-To: "John_H" From: "John_H" Newsgroups: comp.arch.fpga References: Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Lines: 36 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Message-ID: <1At4a.26$F6.6144@news-west.eli.net> Date: Tue, 18 Feb 2003 16:55:25 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1045587325 192.65.17.17 (Tue, 18 Feb 2003 09:55:25 MST) NNTP-Posting-Date: Tue, 18 Feb 2003 09:55:25 MST Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.news2me.com!newshosting.com!news-xfer1.atl.newshosting.com!news-feed01.roc.ny.frontiernet.net!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25912 At xilinx.com, do a search in "Everything" (not just the "AnswerDatabase") for "PCB" and you'll find such entries as Xilinx Design Hints: Printed Circuit Board Design Considerations (XCell Journal 28 article, Q2 98) http://www.xilinx.com/xcell/xl28/xl28_22.pdf and Xilinx Home : Products and Solutions : System Resources : Signal Integrity : PCB Checklist http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?iLanguageID=1&iCountryID= 1&title=si_pcbcheck Although the following .pdf is for the Virtex-II devices, you can probably find a lot of applicable information in the Virtex-II Platform FPGA User Guide http://www.xilinx.com/publications/products/v2/ug_pdf/ug002.pdf "Stamatis Sotiropoulos" wrote in message news:b2tdtg$1g98$1@ulysses.noc.ntua.gr... > Hi all, > I am designing a PCB using an XC2S100 FPGA. Does anyone know where I can > find design considerations for this PCB, such powering, bypass capasitors, > etc. Is there something special I must pay attention to? > > Thanks you in advance, > Stamatis > > > ###### From: kolja@bnl.gov (Kolja Sulimma) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: 18 Feb 2003 13:22:47 -0800 Organization: http://groups.google.com/ Lines: 25 Message-ID: <25c81abf.0302181322.7584e4d4@posting.google.com> References: NNTP-Posting-Host: 131.246.77.46 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1045603367 28222 127.0.0.1 (18 Feb 2003 21:22:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 18 Feb 2003 21:22:47 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!irazu.switch.ch!luth.se!nycmny1-snh1.gtei.net!news.gtei.net!bloom-beacon.mit.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25929 > Hi all, > I am designing a PCB using an XC2S100 FPGA. Does anyone know where I can > find design considerations for this PCB, such powering, bypass capasitors, > etc. Is there something special I must pay attention to? What kind of package do you use? If you do a two layer board you must be very careful with your power routing. Usually you have three power supply rails and only one layer to connect them to the FPGA. With four layers live is simple. The amount of bypass capacitors necessary varies with the amount of simultenous switching going on and the slew rates selected for the outputs. Usually you do not need one capacitors per power/ground pair. But there are people who suggest that you should, and if your application is more demanding with respect to transient power, you should folow theire advice. Surely every power and ground pin should have a very short connection to a capacitor and the capacitor should have a small SMD outline and a low ESR dielectricum. I remember seeing Xilinx application notes on PCB design. At least for the ball grid packages there are detailed guidelines. Kolja Sulimma ###### From: "Stamatis Sotiropoulos" Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: Wed, 19 Feb 2003 14:55:03 +0200 Organization: National Technical University of Athens, Greece Lines: 39 Message-ID: References: <25c81abf.0302181322.7584e4d4@posting.google.com> NNTP-Posting-Host: kozani.mhl.tuc.gr X-Trace: ulysses.noc.ntua.gr 1045659292 27209 147.27.3.78 (19 Feb 2003 12:54:52 GMT) X-Complaints-To: usenet@ulysses.noc.ntua.gr NNTP-Posting-Date: Wed, 19 Feb 2003 12:54:52 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator2-SanJose!in.nntp.be!news.grnet.gr!news.ntua.gr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25947 Hi Kolja, Thank you for your answer. I am using a TQFP-144 package and the clock frequency will be 8 Mhz. Do you think that a 2-layer PCB will work, or 4 layers are necessary for correct circuit operation? Stamatis "Kolja Sulimma" wrote in message news:25c81abf.0302181322.7584e4d4@posting.google.com... > > Hi all, > > I am designing a PCB using an XC2S100 FPGA. Does anyone know where I can > > find design considerations for this PCB, such powering, bypass capasitors, > > etc. Is there something special I must pay attention to? > > What kind of package do you use? > > If you do a two layer board you must be very careful with your power > routing. Usually you have three power supply rails and only one layer > to connect them to the FPGA. With four layers live is simple. > > The amount of bypass capacitors necessary varies with the amount of > simultenous switching going on and the slew rates selected for the > outputs. Usually you do not need one capacitors per power/ground pair. > But there are people who suggest that you should, and if your > application is more demanding with respect to transient power, you > should folow theire advice. > Surely every power and ground pin should have a very short connection > to a capacitor and the capacitor should have a small SMD outline and a > low ESR dielectricum. > > I remember seeing Xilinx application notes on PCB design. At least for > the ball grid packages there are detailed guidelines. > > Kolja Sulimma ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: Wed, 19 Feb 2003 17:59:56 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <25c81abf.0302181322.7584e4d4@posting.google.com> X-Complaints-To: abuse@supernews.com Lines: 30 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:25949 > Thank you for your answer. I am using a TQFP-144 package and the clock >frequency will be 8 Mhz. Do you think that a 2-layer PCB will work, or 4 >layers are necessary for correct circuit operation? The clock frequency isn't the critical parameter. It's the edge rate. Of course, the edge rate must be fast for a high speed clock, but it can also be fast when the clock is running slowly, and often is with modern chips. I'd expect it would be interesting/challenging to get a solid design on two layers. I'm sure it's been done. Do you have any big busses? (Lots of outputs changing at the same time.) Are all your outputs using low drive? How many long wires? I'd probably do a trial layout and start by filling the bottom layer under the chip with a ground pad. Can you get the bypass caps near the power pins? What else is on the board? Can you use most of the bottom layer as a ground plane? The other consideration is how important is it that it work the first time? Do you have a software team waiting? How much time are you willing to spend chashing obscure bugs? Are the extra layers cheap insurance? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: Wed, 19 Feb 2003 11:09:55 -0800 Organization: Xilinx,Inc Lines: 38 Message-ID: <3E53D682.FDC2F186@xilinx.com> References: <25c81abf.0302181322.7584e4d4@posting.google.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25938 I agree with Hal's comments. And let me ask: Is a 2-layer board really any cheaper than a 4-layer board? I know it was in the past century, but is there really a significant price difference nowadays ? Is your volume high enough to justify the risk? Peter Alfke ==================================== Hal Murray wrote: > > > Thank you for your answer. I am using a TQFP-144 package and the clock > >frequency will be 8 Mhz. Do you think that a 2-layer PCB will work, or 4 > >layers are necessary for correct circuit operation? > > The clock frequency isn't the critical parameter. It's the edge rate. > > Of course, the edge rate must be fast for a high speed clock, but it > can also be fast when the clock is running slowly, and often is with > modern chips. > > I'd expect it would be interesting/challenging to get a solid design > on two layers. I'm sure it's been done. Do you have any big busses? > (Lots of outputs changing at the same time.) Are all your outputs > using low drive? How many long wires? > > I'd probably do a trial layout and start by filling the bottom layer > under the chip with a ground pad. Can you get the bypass caps near > the power pins? What else is on the board? Can you use most of the > bottom layer as a ground plane? > > The other consideration is how important is it that it work the first time? > Do you have a software team waiting? How much time are you willing to > spend chashing obscure bugs? Are the extra layers cheap insurance? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: Wed, 19 Feb 2003 19:46:29 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 22 Message-ID: References: <3E53D682.FDC2F186@xilinx.com> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1045683989 70256 128.32.112.203 (19 Feb 2003 19:46:29 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Wed, 19 Feb 2003 19:46:29 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25946 In article <3E53D682.FDC2F186@xilinx.com>, Peter Alfke wrote: >I agree with Hal's comments. >And let me ask: Is a 2-layer board really any cheaper than a 4-layer >board? I know it was in the past century, but is there really a >significant price difference nowadays ? Yes. By a fair amount. A 2 layer board is really, REALLY cheap, with prototype to production techniques for 1-3 day turnaround and quick rampup to large volumes. The price difference between 2 and 4 layer is over 50% for something like PCBpro (2x3" board, 100 pieces, 1 week turnaround). Its $448 for a 2 layer board and $783 for a 4 layer board. However, given the cost of designer time and all, unless you really NEED the 1 day board-fabrication turnaround time you can get with a 2 layer board, or that the part cost on the board really REALLY matters, 4 layers seem like cheap insurance. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: Wed, 19 Feb 2003 20:00:23 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <3E53D682.FDC2F186@xilinx.com> X-Complaints-To: abuse@supernews.com Lines: 20 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!sn-xit-03!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:25950 >A 2 layer board is really, REALLY cheap, with prototype to production >techniques for 1-3 day turnaround and quick rampup to large volumes. 1 layer is even cheaper. :) > And let me ask: Is a 2-layer board really any cheaper than a 4-layer > board? I know it was in the past century, but is there really a > significant price difference nowadays ? Showing how to make things to work (well) on 2 layers might be an interesting opportunity for an FAE group. Opens up another corner of the low price market. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: Thu, 20 Feb 2003 04:44:04 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <3E53D682.FDC2F186@xilinx.com> X-Complaints-To: abuse@supernews.com Lines: 30 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-01!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:25986 [2 layer discussion] >I've done that on my FPGA board. So far I had no problems though I >haven't tested it at really high speeds. I've created a small webpage >where I've put images of the layout: >http://tantos.homelinux.org/~tantos/ >Please anyone interested, take a look and comment. Both positive and >negative feedback are extreamly welcome. Thanks. What is your FPGA doing? How many outputs switching at the same time? (Looks like a bus going off to the right on the blue layer.) Are they all low/slow drive? As far as I can see, there is only 1 bypass cap on each power rail, and one of them goes around the bottom of the chip so the end of it is a long way from the cap. I'd be nervous about using a structure like that, but that's just my quick eyeball analysis. Might be interesting to feed it to some signal integrity tools. (I tend to be conservative in this area, left over from getting burned many years ago.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: Andras Tantos Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Newsgroups: comp.arch.fpga References: <3E53D682.FDC2F186@xilinx.com> Lines: 30 User-Agent: KNode/0.7.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Message-ID: Date: Thu, 20 Feb 2003 05:21:21 GMT NNTP-Posting-Host: 4.42.93.37 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc02.gnilink.net 1045718481 4.42.93.37 (Thu, 20 Feb 2003 00:21:21 US/Eastern) NNTP-Posting-Date: Thu, 20 Feb 2003 00:21:21 US/Eastern Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!c03.atl99!chi1.webusenet.com!news.webusenet.com!cyclone1.gnilink.net!spamkiller.gnilink.net!nwrddc02.gnilink.net.POSTED!9feefe32!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25993 Hi! > What is your FPGA doing? How many outputs switching at the same time? > (Looks like a bus going off to the right on the blue layer.) Are they > all low/slow drive? > > As far as I can see, there is only 1 bypass cap on each power rail, > and one of them goes around the bottom of the chip so the end of > it is a long way from the cap. Thanks for the comments. Yes, I do have a bus comming out from this chip however it's a relatively slow asycnronous 16-bit one. Average number of switching signals in each cycle should be around 15. I have one bypass caps on each power rail but I also have one for each chip power pin also. You probably right about the core VCC: it's long. However I wanted to avoid another via let alone a loop in the layout. > I'd be nervous about using a structure like that, but that's just > my quick eyeball analysis. Might be interesting to feed it to > some signal integrity tools. (I tend to be conservative in this > area, left over from getting burned many years ago.) Yeah, I've tried to do that but my CAD pacakge kept crashing on each and every trial. :-( Andras Tantos ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: Thu, 20 Feb 2003 06:39:16 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <3E53D682.FDC2F186@xilinx.com> X-Complaints-To: abuse@supernews.com Lines: 17 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!uni-erlangen.de!newsfeed.arcor-online.net!newsfeed.freenet.de!feed.news.nacamar.de!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.frii.net!newsfeed.frii.net!news-out.newsfeeds.com!propagator2-maxim!news-in.spamkiller.net!telocity-west!DIRECTV!sn-xit-03!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:25987 >You probably right about the core VCC: it's long. However I wanted to avoid >another via let alone a loop in the layout. Ahh. I see them now that I look in the right place. That's probably (close to?) as good as you can get with only 2 layers. Another layout possibility is to put a ring on the bottom layer directly under the pads. With only 2 layers, that will block routes from vias in the inside of the pad ring. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: mrand@my-deja.com (Marc Randolph) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: 20 Feb 2003 06:39:56 -0800 Organization: http://groups.google.com/ Lines: 45 Message-ID: <15881dde.0302200639.230e6927@posting.google.com> References: <3E53D682.FDC2F186@xilinx.com> NNTP-Posting-Host: 65.192.92.132 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1045751997 1861 127.0.0.1 (20 Feb 2003 14:39:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 20 Feb 2003 14:39:57 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25996 nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:... > In article <3E53D682.FDC2F186@xilinx.com>, > Peter Alfke wrote: > >I agree with Hal's comments. > >And let me ask: Is a 2-layer board really any cheaper than a 4-layer > >board? I know it was in the past century, but is there really a > >significant price difference nowadays ? > > Yes. By a fair amount. > > A 2 layer board is really, REALLY cheap, with prototype to production > techniques for 1-3 day turnaround and quick rampup to large volumes. > > The price difference between 2 and 4 layer is over 50% for something > like PCBpro (2x3" board, 100 pieces, 1 week turnaround). Its $448 for > a 2 layer board and $783 for a 4 layer board. Holy moly that's expensive! $783 for ONE two layer board? Oh, wait - you must mean $783 for 100 of them. In that case, HOLY MOLY THAT's cheap! For comparison, I just had ~10 PCB's made on a 1 week turn. They are 6x16", 12 layers, with small vias, small line widths, and small line spacing. They were in the $600's. Each. The part with the highest pin density is a Spartan IIE in a FG456 package with most of the I/O used up - it only needed four routing layers. At the same time, we turned a different version of the same sized PCB, same rules, but with 16 layers. It was in the $800's, each. So each layer on a quick turn, in low quantity, is costing us ~$50. Obviously as the number of layers drop, the % of cost savings goes up for each additional layer. > However, given the cost of designer time and all, unless you really > NEED the 1 day board-fabrication turnaround time you can get with a 2 > layer board, or that the part cost on the board really REALLY matters, > 4 layers seem like cheap insurance. I agree. You don't want to have to be guessing that the problem is poor ground or power (and then somehow improving it on the PCB you have in your hands). Marc ###### From: kolja@bnl.gov (Kolja Sulimma) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for a Xilinx Spartan-II FPGA Date: 21 Feb 2003 02:13:03 -0800 Organization: http://groups.google.com/ Lines: 26 Message-ID: <25c81abf.0302210213.7696064c@posting.google.com> References: <3E53D682.FDC2F186@xilinx.com> NNTP-Posting-Host: 131.246.77.46 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1045822383 743 127.0.0.1 (21 Feb 2003 10:13:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 21 Feb 2003 10:13:03 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:26020 > Another layout possibility is to put a ring on the bottom layer > directly under the pads. With only 2 layers, that will block > routes from vias in the inside of the pad ring. At 8 MHz you can set the slew rates slow enough to use two layers. Especially if you only have 16 switching signals. We use loops on the bottom layer for each power supply. The loops have small capacitors between them. Each fpga pin connects from the inside to one of the loops by a via. There is a ground plane below the chip on the top layer to connect GND. This also has coupling caps to the power supply loops. Using this scheme we have PCI running reliable on two layer boards. But we probably do not meet the PCI specifiation. (We also have som 250MHz data aquistion stuff runnning on two layers, also) Peter: 4-Layer boards are not a lot more expensive than two layer boards in production, but you have to pay a couple of hundred $ upfront, which you do not have for two layers. For a hobby project it is a big difference whether the first prototype costs $40 or $300. Kolja Sulimma