From: cvmnk@yahoo.com (naveen) Newsgroups: comp.arch.fpga Subject: debounce circuit Date: 6 Feb 2003 17:27:39 -0800 Organization: http://groups.google.com/ Lines: 13 Message-ID: NNTP-Posting-Host: 130.108.129.21 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1044581259 20776 127.0.0.1 (7 Feb 2003 01:27:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 7 Feb 2003 01:27:39 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25673 hi , iam implementing a 32 ALU using vertex 2 fpga. i have to make use of pushbutton for my clock enable pin of my counter. i have to make use of 24 MHZ clock. so when i push button, ie give CE to my counter, counter should increment by only one count, i have to make use of debounce circuit for my CE input to make my counter to increment by only one when i push the button. can ne one suggest me a debounce circuit i can use. thanx regards naveen ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: debounce circuit Date: Thu, 06 Feb 2003 17:58:42 -0800 Organization: Xilinx,Inc Lines: 38 Message-ID: <3E4312D1.5A11F904@xilinx.com> References: NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: naveen Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!enews.sgi.com!newsfeed.ap.concert.net!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25623 If you have a single-pole, double-throw switch: Connect the switch arm to an I/O pin, and the other two terminals to Vcc and Grd. Configure the I/O as an input driving itself as an output. Make the output rather weak. Now you have a debouncing latch. To generate a single pulse, feed the input into a 2-stage shift register, and decode the one-zero condition of the two flip-flops. That's called a digital differentiator. If you still get double pulses, insert a shift register with low clock rate between the input and the differentiator. But I doubt this would be necessary. You can also design a more elaborate debouncer with the switch arm connected to ground, and the other two terminals driving the set and reset of a latch, but don't forget the pull-up resistors in that case. With a single-pole, single-throw switch, the circuit gets more complicated. Peter Alfke ========== naveen wrote: > hi , > iam implementing a 32 ALU using vertex 2 fpga. i have to make use > of pushbutton for my clock enable pin of my counter. i have to make > use of 24 MHZ clock. so when i push button, ie give CE to my counter, > counter should increment by only one count, i have to make use of > debounce circuit for my CE input to make my counter to increment by > only one when i push the button. > > can ne one suggest me a debounce circuit i can use. > > thanx > regards > naveen ###### From: "Theron Hicks (Terry)" Newsgroups: comp.arch.fpga Subject: Re: debounce circuit Date: Thu, 06 Feb 2003 22:09:38 -0500 Organization: Michigan State University Lines: 38 Message-ID: <3E432372.A5339EFB@egr.msu.edu> References: NNTP-Posting-Host: pm851-07.dialip.mich.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-AUTHid: hicksthe X-Mailer: Mozilla 4.51 [en] (WinNT; I) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!enews.sgi.com!torn!snoopy.risq.qc.ca!elk.ncren.net!nntp.upenn.edu!msunews!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25626 Naveen, I hope this is not homework as I have already goitten myself in enough trouble with my rants on do your own work. You can use a counter based one-shot. Start a counter running on the first edge and mask any edges until the counter reaches terminal count. Typically, bounce time is usually on the order of a few milliseconds per bounce cycle. You will need to verify your switch's bounce period. I suspect that the bounce period will vary drastically as the switch ages. By the way, the switch should be rated for dry circuit applications (as opposed to high current applications.) Check with the switch manufacturer. Of course you could look at some of the old fashioned debounce circuits using an RS flipflop but they all require more than a single pole - single throw switch and use two inputs to the FPGA. However, they are almost fool proof. For details see the CD4043B data sheet from TI. (Other manufacturers seem to not have the application detail in the data sheet for this item.) I have used both types of circuits succesfully. Alternatively, if you can get away with using a keeper circuit (specific to Xilinx's later devices, I think) you might get something like that to work. Theron naveen wrote: > hi , > iam implementing a 32 ALU using vertex 2 fpga. i have to make use > of pushbutton for my clock enable pin of my counter. i have to make > use of 24 MHZ clock. so when i push button, ie give CE to my counter, > counter should increment by only one count, i have to make use of > debounce circuit for my CE input to make my counter to increment by > only one when i push the button. > > can ne one suggest me a debounce circuit i can use. > > thanx > regards > naveen ###### From: "Bill Turnip" Newsgroups: comp.arch.fpga References: Subject: Re: debounce circuit Lines: 26 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.3018.1300 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.3018.1300 Message-ID: NNTP-Posting-Host: 12.235.21.98 X-Complaints-To: abuse@attbi.com X-Trace: sccrnsc02 1044597264 12.235.21.98 (Fri, 07 Feb 2003 05:54:24 GMT) NNTP-Posting-Date: Fri, 07 Feb 2003 05:54:24 GMT Organization: AT&T Broadband Date: Fri, 07 Feb 2003 05:54:24 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!newsfeed.mathworks.com!wn13feed!wn12feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!sccrnsc02.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25635 Naveen - If you have the Xilinx tools, under the "Synthesis Templates" you'll find the VHDL and Verilog code for a Debounce circuit. At least in WebPACK they're there... Bill "naveen" wrote in message news:b7f5eb6a.0302061727.11783405@posting.google.com... > hi , > iam implementing a 32 ALU using vertex 2 fpga. i have to make use > of pushbutton for my clock enable pin of my counter. i have to make > use of 24 MHZ clock. so when i push button, ie give CE to my counter, > counter should increment by only one count, i have to make use of > debounce circuit for my CE input to make my counter to increment by > only one when i push the button. > > can ne one suggest me a debounce circuit i can use. > > thanx > regards > naveen