From: weirdo@bbs.frc.utn.edu.ar (Mauricio Lange) Newsgroups: comp.arch.fpga Subject: PCI protocol - assigning an address to my device Date: 28 Jan 2003 08:02:31 -0800 Organization: http://groups.google.com/ Lines: 43 Message-ID: <2f938098.0301280802.2552a0ab@posting.google.com> NNTP-Posting-Host: 200.45.223.209 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1043769751 16339 127.0.0.1 (28 Jan 2003 16:02:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 28 Jan 2003 16:02:31 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25387 Hi everybody! The PCI card I started to design months ago is near completion. Thanks a lot to all the people that answered my questions in this forum! Near completion means that it provides required functionality, but many details are in the road yet. Regarding configuration, I have difficult trying to interpret what the PCI spec says about the address assignment. I recall from the spec that the computer, at power-up time, reads the configuration registers, reads the BAR0, BAR1, etc, to find if any is implemented. I implemented the BAR0 register, that means that if the host writes data to it, when it reads the data back, some of the bits are set. Then, the host decides what address to assign to my device looking for the weight of the lowest bit set, so, if when BAR0 gives back 0xfffff000, the lowest bit is the 11th, or a decoding space of 2k, right? Then, my card should end with an address multiple of 2k, in any location of the memory space, that is what I understood. So, is the base address assignment a multipass cycle? I mean, the host first writes 0xffffffff to my BAR0, the it reads the data back, then it writes the assigned base address to my BAR0? I did the following: preset my BAR0 register to 0x00000005 (the BAR0(0) bit indicates the space, memory or i/o) and get, as result, the following address assigned: 0x02000001, what could that possibly mean? A curious thing: The card is double layer, carefully laid out to minimize the lenghts (that never, never aproached to the 1.5 inches that the spec insists on using) and the number of vias thru each trace has to pass; uses a socketed PLCC84 old FPGA, that surely doesn't comply with the required 10pf per pin max. That only description could give me fever not a long time ago, thinking of the bus disasters it could cause. But, to my surprise, not even a wire 10 inches long, soldered to a via (!!!) in my card, could disrupt the normal behavior of the bus. The bus is tougher than I thought. Excuse me the lenght of the question! Mauricio Lange ###### From: "glen herrmannsfeldt" Newsgroups: comp.arch.fpga References: <2f938098.0301280802.2552a0ab@posting.google.com> Subject: Re: PCI protocol - assigning an address to my device Lines: 35 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Message-ID: NNTP-Posting-Host: 12.228.58.87 X-Complaints-To: abuse@attbi.com X-Trace: rwcrnsc52.ops.asp.att.net 1043774255 12.228.58.87 (Tue, 28 Jan 2003 17:17:35 GMT) NNTP-Posting-Date: Tue, 28 Jan 2003 17:17:35 GMT Organization: AT&T Broadband Date: Tue, 28 Jan 2003 17:17:35 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!arclight.uoregon.edu!wn13feed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi.com!rwcrnsc52.ops.asp.att.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25447 "Mauricio Lange" wrote in message news:2f938098.0301280802.2552a0ab@posting.google.com... > The PCI card I started to design months ago is near completion. Thanks > a lot to all the people that answered my questions in this forum! > Near completion means that it provides required functionality, but > many details are in the road yet. (snip) > > A curious thing: The card is double layer, carefully laid out to > minimize the lenghts (that never, never aproached to the 1.5 inches > that the spec insists on using) and the number of vias thru each trace > has to pass; uses a socketed PLCC84 old FPGA, that surely doesn't > comply with the required 10pf per pin max. > That only description could give me fever not a long time ago, > thinking of the bus disasters it could cause. But, to my surprise, not > even a wire 10 inches long, soldered to a via (!!!) in my card, could > disrupt the normal behavior of the bus. The bus is tougher than I > thought. Both the capacitance and wire length will be set for the maximum number of cards on the bus. If you have only one or two you can probably greatly exceed those. -- glen ###### From: Kevin Brace Newsgroups: comp.arch.fpga Subject: Re: PCI protocol - assigning an address to my device Date: Tue, 28 Jan 2003 11:47:32 -0600 Organization: None Lines: 113 Sender: kevinbraceusenet@hotmail.com Message-ID: References: <2f938098.0301280802.2552a0ab@posting.google.com> NNTP-Posting-Host: 1cust40.tnt75.chi5.da.uu.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: newsreader.mailgate.org 1043775890 14781 67.195.57.40 (28 Jan 2003 17:44:50 GMT) X-Complaints-To: abuse@mailgate.org NNTP-Posting-Date: Tue, 28 Jan 2003 17:44:50 +0000 (UTC) X-Mailer: Mozilla 4.79 [en] (Win98; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsreader.mailgate.org!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25366 Mauricio, See my comments below. Mauricio Lange wrote: > > Hi everybody! > The PCI card I started to design months ago is near completion. Thanks > a lot to all the people that answered my questions in this forum! > Near completion means that it provides required functionality, but > many details are in the road yet. I hope you simulate the design on a simulator well before firing up the card. That how I developed a PCI IP core without using an oscilloscope or a logic analyzer. > Regarding configuration, I have difficult trying to interpret what the > PCI spec says about the address assignment. > I recall from the spec that the computer, at power-up time, reads the > configuration registers, reads the BAR0, BAR1, etc, to find if any is > implemented. > I implemented the BAR0 register, that means that if the host writes > data to it, when it reads the data back, some of the bits are set. > Then, the host decides what address to assign to my device looking for > the weight of the lowest bit set, so, if when BAR0 gives back > 0xfffff000, the lowest bit is the 11th, or a decoding space of 2k, > right? > Then, my card should end with an address multiple of 2k, in any > location of the memory space, that is what I understood. > That's correct. > So, is the base address assignment a multipass cycle? I mean, the host > first writes 0xffffffff to my BAR0, the it reads the data back, then > it writes the assigned base address to my BAR0? > That's how the BIOS (firmware) determines the BAR size. > I did the following: preset my BAR0 register to 0x00000005 (the > BAR0(0) bit indicates the space, memory or i/o) and get, as result, > the following address assigned: 0x02000001, what could that possibly > mean? > You should be aware that the PCI specification says devices should not have I/O mapped address larger than 256 bytes per BAR. That has to do with IBM PC/AT architecture's I/O mapping limitations. If you want address space larger than 256 bytes, it has to be memory mapped. Also, if your device's BAR type is I/O BAR, bit 2 of the BAR cannot be hardwired to 1 (If you want, it can be hardwired to 0, however.), or start up as 1 after reset (PCI specification assumes that configuration registers should start up as 0, unless hardwired to a certain value.). > A curious thing: The card is double layer, carefully laid out to > minimize the lenghts (that never, never aproached to the 1.5 inches > that the spec insists on using) and the number of vias thru each trace > has to pass; uses a socketed PLCC84 old FPGA, that surely doesn't > comply with the required 10pf per pin max. > That only description could give me fever not a long time ago, > thinking of the bus disasters it could cause. But, to my surprise, not > even a wire 10 inches long, soldered to a via (!!!) in my card, could > disrupt the normal behavior of the bus. The bus is tougher than I > thought. > > Excuse me the lenght of the question! > > Mauricio Lange What FPGA are you using? Sounds like a real old one to me. Anyway, if you are using an FPGA that still supports PLCC package, your design may not meet PCI's setup time because the FPGA is likely very slow. PCI specification says, for 33MHz PCI, the PCI device needs to latch data from the bus within 7ns (setup time, Tsu), and send data within 11ns (clock-to-output valid, Tval). However, in practice, you will have some clock skew within the FPGA, so you will have additional 1ns to 2ns to latch the data. Still, 8ns to 9ns is not much time, and if you really want to meet it, you will have to resort to optimizing your design (i.e., Reducing the levels of logic) or floorplanning. But I am aware that even you violate the Tsu or Tval by several ns, the card will still likely work because the first version of the PCI IP core I developed violated Tsu and Tval by 3ns to 4ns respectively, but it worked fine at 33MHz. If you really want to stick to the specification, consider using Virtex or Spartan-II because they are so much faster, it is much easier to meet timings. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) ###### From: weirdo@bbs.frc.utn.edu.ar (Mauricio Lange) Newsgroups: comp.arch.fpga Subject: Re: PCI protocol - assigning an address to my device Date: 28 Jan 2003 22:30:19 -0800 Organization: http://groups.google.com/ Lines: 49 Message-ID: <2f938098.0301282230.2025d4e2@posting.google.com> References: <2f938098.0301280802.2552a0ab@posting.google.com> NNTP-Posting-Host: 200.80.10.81 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1043821819 23457 127.0.0.1 (29 Jan 2003 06:30:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 29 Jan 2003 06:30:19 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25377 Kevin, Glen, thanks for the replys. > I hope you simulate the design on a simulator well before firing > up the card. > That how I developed a PCI IP core without using an oscilloscope or a > logic analyzer. I didn't use a logic analyzer nor an oscilloscope. Fired it up and worked. I did the design part by part, so, the first time the card was alive, the only thing it could do was a Target I/O Write!! I used a K6 class PC, booted to DOS and used DEBUG. I connected a 7 segment display to the multi-purpose header of my card and used it as the debug output. Now, I dont have the thousand or so bucks required to get a number from the PCI Group, so, I am playing with the PCI numbers already registered. :) > What FPGA are you using? > Sounds like a real old one to me. > Anyway, if you are using an FPGA that still supports PLCC package, your > design may not meet PCI's setup time because the FPGA is likely very > slow. > PCI specification says, for 33MHz PCI, the PCI device needs to latch > data from the bus within 7ns (setup time, Tsu), and send data within > 11ns (clock-to-output valid, Tval). > However, in practice, you will have some clock skew within the FPGA, so > you will have additional 1ns to 2ns to latch the data. > Still, 8ns to 9ns is not much time, and if you really want to meet it, > you will have to resort to optimizing your design (i.e., Reducing the > levels of logic) or floorplanning. > But I am aware that even you violate the Tsu or Tval by several ns, the > card will still likely work because the first version of the PCI IP core > I developed violated Tsu and Tval by 3ns to 4ns respectively, but it > worked fine at 33MHz. > If you really want to stick to the specification, consider using Virtex > or Spartan-II because they are so much faster, it is much easier to meet > timings. > This is my first card, and I had to resort to what I had in hand. Xilinx donated a kit from XESS with an XC4010XL two years ago to my university. I am using that IC. In my next project (coming soon, I hope!), I will be using a Spartan or a Virtex, no doubt of it! Mauricio Lange ###### From: praveenkumar1979@rediffmail.com (praveen) Newsgroups: comp.arch.fpga Subject: Re: PCI protocol - assigning an address to my device Date: 28 Jan 2003 22:35:44 -0800 Organization: http://groups.google.com/ Lines: 9 Message-ID: References: <2f938098.0301280802.2552a0ab@posting.google.com> NNTP-Posting-Host: 219.65.139.9 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1043822145 23930 127.0.0.1 (29 Jan 2003 06:35:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 29 Jan 2003 06:35:45 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25418 hello, i am praveen kumar , a student doing the vhdl code of PCI bridge. can u please give the internal design detial(design document) of the PCI bridge which you have implemented. you can mail it to my email id praveenkumar1979@rediffmail.com).i will be greatful to you. waiting for ur reply thanks in advance praveen ###### From: weirdo@bbs.frc.utn.edu.ar (Mauricio Lange) Newsgroups: comp.arch.fpga Subject: Re: PCI protocol - assigning an address to my device Date: 29 Jan 2003 05:33:52 -0800 Organization: http://groups.google.com/ Lines: 14 Message-ID: <2f938098.0301290533.29ea74bd@posting.google.com> References: <2f938098.0301280802.2552a0ab@posting.google.com> NNTP-Posting-Host: 200.45.219.226 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1043847233 27258 127.0.0.1 (29 Jan 2003 13:33:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 29 Jan 2003 13:33:53 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25410 praveenkumar1979@rediffmail.com (praveen) wrote in message news:... > hello, > i am praveen kumar , a student doing the vhdl code of PCI bridge. can > u please give the internal design detial(design document) of the PCI > bridge which you have implemented. you can mail it to my email id > praveenkumar1979@rediffmail.com).i will be greatful to you. > > waiting for ur reply > thanks in advance > praveen Praveen, it is not a PCI bridge what I am designing. I sent you an email. Mauricio Lange ###### From: "Austin Franklin" Newsgroups: comp.arch.fpga Subject: Re: PCI protocol - assigning an address to my device Date: Fri, 31 Jan 2003 20:45:48 -0500 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <2f938098.0301280802.2552a0ab@posting.google.com> X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 X-Complaints-To: abuse@supernews.com Lines: 42 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshosting.com!news-xfer1.atl.newshosting.com!140.99.99.194.MISMATCH!newsfeed1.easynews.com!easynews.com!easynews!sn-xit-02!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25355 > Then, the host decides what address to assign to my device looking for > the weight of the lowest bit set, so, if when BAR0 gives back > 0xfffff000, the lowest bit is the 11th, or a decoding space of 2k, > right? 0xFFFF_F000 is 12 bits (bits 11-0), or a 4k space. > Then, my card should end with an address multiple of 2k, 4k. in any > location of the memory space, that is what I understood. After the configuration WRITES all 1's to the BAR, and reads back 0xFFFF_F000 it then WRITES a new address to the board that will be the start address of your 4k memory. > So, is the base address assignment a multipass cycle? I mean, the host > first writes 0xffffffff to my BAR0, the it reads the data back, then > it writes the assigned base address to my BAR0? Correct. > I did the following: preset my BAR0 register to 0x00000005 (the > BAR0(0) bit indicates the space, memory or i/o) and get, as result, > the following address assigned: 0x02000001, what could that possibly > mean? You get a 4k space starting at 0x0200_0xxx. BUT, why are you setting bit 0 to 1 for? You are asking for 4k of I/O space...and you probably really want memory space. Why are you setting bit 2? Setting bit 2 and 1 to 10b asks the system to locate you in 64 bit address space... I'd suggest presetting bit 0 to 0 and bit 2 to 0 as well. These should not be presets, but hard bits...that can't be written. No need to implement them as a register, just use an enablable buffers and tie the inputs to ground for the lower 12 bits of the BAR. Austin ###### From: weirdo@bbs.frc.utn.edu.ar (Mauricio Lange) Newsgroups: comp.arch.fpga Subject: Re: PCI protocol - assigning an address to my device Date: 3 Feb 2003 20:34:55 -0800 Organization: http://groups.google.com/ Lines: 24 Message-ID: <2f938098.0302032034.6bf487a7@posting.google.com> References: <2f938098.0301280802.2552a0ab@posting.google.com> NNTP-Posting-Host: 200.82.10.219 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1044333295 2022 127.0.0.1 (4 Feb 2003 04:34:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 4 Feb 2003 04:34:55 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25520 Austin, thanks for the reply! I will work on that! Mauricio Lange > > > I did the following: preset my BAR0 register to 0x00000005 (the > > BAR0(0) bit indicates the space, memory or i/o) and get, as result, > > the following address assigned: 0x02000001, what could that possibly > > mean? > > You get a 4k space starting at 0x0200_0xxx. BUT, why are you setting bit 0 > to 1 for? You are asking for 4k of I/O space...and you probably really want > memory space. Why are you setting bit 2? Setting bit 2 and 1 to 10b asks > the system to locate you in 64 bit address space... > > I'd suggest presetting bit 0 to 0 and bit 2 to 0 as well. These should not > be presets, but hard bits...that can't be written. No need to implement > them as a register, just use an enablable buffers and tie the inputs to > ground for the lower 12 bits of the BAR. > > Austin ###### From: Kevin Brace Newsgroups: comp.arch.fpga Subject: Re: PCI protocol - assigning an address to my device Date: Tue, 04 Feb 2003 15:07:41 -0600 Organization: None Lines: 22 Sender: kevinbraceusenet@hotmail.com Message-ID: References: <2f938098.0301280802.2552a0ab@posting.google.com> NNTP-Posting-Host: 1cust108.tnt75.chi5.da.uu.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: newsreader.mailgate.org 1044392791 7586 67.195.57.108 (4 Feb 2003 21:06:31 GMT) X-Complaints-To: abuse@mailgate.org NNTP-Posting-Date: Tue, 4 Feb 2003 21:06:31 +0000 (UTC) X-Mailer: Mozilla 4.76 [en] (Win98; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsreader.mailgate.org!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25534 Austin, To make a correction of what you said, if bit 0 of a BAR is 1, that will indicate that BAR is for IO space, and if so, bit 2 and 1 will not indicate 64 bit addressing. For IO space, bit 2 can only be a register or hardwired to 0, and bit 1 is currently reserved (Has to be hardwired to 0.). Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) Austin Franklin wrote: > > > You get a 4k space starting at 0x0200_0xxx. BUT, why are you setting bit 0 > to 1 for? You are asking for 4k of I/O space...and you probably really want > memory space. Why are you setting bit 2? Setting bit 2 and 1 to 10b asks > the system to locate you in 64 bit address space... > ###### From: "Austin Franklin" Newsgroups: comp.arch.fpga Subject: Re: PCI protocol - assigning an address to my device Date: Wed, 5 Feb 2003 14:15:23 -0500 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <2f938098.0301280802.2552a0ab@posting.google.com> X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 X-Complaints-To: abuse@supernews.com Lines: 38 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-06!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25582 Hi Kevin, You're right, but my assumption was that the poster really wanted memory space (as I believe I said), not I/O space...so I believe he meant to set memory and 64 bit addressing, and I wondered why. Austin "Kevin Brace" wrote in message news:b1pa0m$7d2$1@newsreader.mailgate.org... > Austin, > > To make a correction of what you said, if bit 0 of a BAR is 1, that will > indicate that BAR is for IO space, and if so, bit 2 and 1 will not > indicate 64 bit addressing. > For IO space, bit 2 can only be a register or hardwired to 0, and bit 1 > is currently reserved (Has to be hardwired to 0.). > > > Kevin Brace (If someone wants to respond to what I wrote, I prefer if > you will do so within the newsgroup.) > > > > Austin Franklin wrote: > > > > > > You get a 4k space starting at 0x0200_0xxx. BUT, why are you setting bit 0 > > to 1 for? You are asking for 4k of I/O space...and you probably really want > > memory space. Why are you setting bit 2? Setting bit 2 and 1 to 10b asks > > the system to locate you in 64 bit address space... > >