From: "Florian" Newsgroups: comp.arch.fpga Subject: Clock Feedback for DDR-SDRAM (XApp200) Date: Tue, 28 Jan 2003 00:02:26 +0100 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4910.0300 Lines: 24 Message-ID: <3e362717$0$3025$9b622d9e@news.freenet.de> NNTP-Posting-Host: 213.7.174.150 X-Trace: 1043736344 news.freenet.de 3025 213.7.174.150:1032 X-Complaints-To: abuse@freenet.de Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!newsfeed.freenet.de!news.freenet.de!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25337 Hello, i'm designing a board with a VirtexII that takes masses of data from several inputs and stores it in 2 DDR-RAM channels. For the ram-controller i'm orientating on xapp200. It says to feed the ddr_clk and possibly ddr_clkb back into the fpga. My question is how to route this feedback on the pcb? I see several possibilities: - shortest way from pad to pad - from the series termination resitor - from the ram-socket - from the parallel termination resitor And how do i terminate this feedback? (DCI is not an option) Any help welcome Thank You in advance Florian ###### From: "John_H" Newsgroups: comp.arch.fpga References: <3e362717$0$3025$9b622d9e@news.freenet.de> Subject: Re: Clock Feedback for DDR-SDRAM (XApp200) Lines: 66 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2720.3000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: <4yyZ9.7$Xb7.4289@news-west.eli.net> Date: Tue, 28 Jan 2003 16:51:12 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1043772672 192.65.17.17 (Tue, 28 Jan 2003 09:51:12 MST) NNTP-Posting-Date: Tue, 28 Jan 2003 09:51:12 MST Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!enews.sgi.com!logbridge.uoregon.edu!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25331 You need to get your overall timing margins so that your feedback gives you sampling in the very center of your data window. The Xilinx app notes do a good job of detailing the timing margin calculations. The SSTL signals used for data, address, and control are what feed the DDRs and what they deliver back to the FPGA. The feedback clock should be the same IO standard. In the app note timing margin calculations, there is an explicit mention of the overall routed length required to achieve the margin in the example (unless I'm getting my Xilinx DDR app notes mixed up and the one you're looking at missed that detail). Based on the propagation delay of the signals in your layout (internal layer signal speed is slightly slower than the delay on an outer layer), you can figure out just how much length to put in. Look at the timing budget numbers. Understand where they come from. You'll be able to get some very good timing if you pay attention to those numbers. As with any SSTL signal, you have a series resistor near the source (look at all the other SSTL signals) and a resistor to VTT at the end. That's how the signal for the feedback has to be routed for proper delay matching. Ah, yes. Virtex-II. I almost forgot about the phase shifting in the DCM. I prototyped a DDR with a Virtex-II and used the phase shift feature but the feedback is still external SSTL-II. Rather than adding the extra length, I compensated with the phase shift. In the Spartan-IIE for production I didn't have that "luxury" but by matching the lengths externally I got a tighter timing window (more margin) than the Virtex-II thanks to propagation delay matching and internal Xilinx component delay tracking. Virtex-II still needs the resistors to look like an SSTL-II even if you choose no to run the extra signal length. So take my initial rambling as an approach without the phase shift or use the last paragraph for a short external route. But do go external. "Florian" wrote in message news:3e362717$0$3025$9b622d9e@news.freenet.de... > Hello, > i'm designing a board with a VirtexII that takes masses of data from several > inputs and stores it in 2 DDR-RAM channels. For the ram-controller i'm > orientating on xapp200. It says to feed the ddr_clk and possibly ddr_clkb > back into the fpga. My question is how to route this feedback on the pcb? I > see several possibilities: > - shortest way from pad to pad > - from the series termination resitor > - from the ram-socket > - from the parallel termination resitor > And how do i terminate this feedback? (DCI is not an option) > > Any help welcome > > Thank You in advance > Florian > > > > > > > > ###### From: b_foelsch@hotmail.com (Boris Foelsch) Newsgroups: comp.arch.fpga Subject: Re: Clock Feedback for DDR-SDRAM (XApp200) Date: 1 Feb 2003 14:41:23 -0800 Organization: http://groups.google.com/ Lines: 34 Message-ID: <105d1b62.0302011441.155f3df8@posting.google.com> References: <3e362717$0$3025$9b622d9e@news.freenet.de> NNTP-Posting-Host: 69.3.147.19 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1044139283 2322 127.0.0.1 (1 Feb 2003 22:41:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 1 Feb 2003 22:41:23 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25398 "Florian" wrote in message news:<3e362717$0$3025$9b622d9e@news.freenet.de>... > Hello, > i'm designing a board with a VirtexII that takes masses of data from several > inputs and stores it in 2 DDR-RAM channels. For the ram-controller i'm > orientating on xapp200. It says to feed the ddr_clk and possibly ddr_clkb > back into the fpga. My question is how to route this feedback on the pcb? I > see several possibilities: > - shortest way from pad to pad > - from the series termination resitor > - from the ram-socket > - from the parallel termination resitor > And how do i terminate this feedback? (DCI is not an option) > > Any help welcome > > Thank You in advance > Florian Your objective should be to make the DDR socket get as close as possible to the same (phase) clock as the controller. That usually means matching trace lengths from the point of clock distribution to the SDRAM with the length to the controller, which is either a feedback clock or an input clock, depending on your distribution scheme. Where you pick it up is a signal integrity issue, which somewhat separate from the trace length matching issue. Note that the clock inputs to the DDR SDRAM are not (single-ended) SSTL-2, but are differential. You need both parts of the differential signal. -Boris ###### From: b_foelsch@hotmail.com (Boris Foelsch) Newsgroups: comp.arch.fpga Subject: Re: Clock Feedback for DDR-SDRAM (XApp200) Date: 3 Feb 2003 20:19:49 -0800 Organization: http://groups.google.com/ Lines: 8 Message-ID: <105d1b62.0302032019.6b1ee4b7@posting.google.com> References: <3e362717$0$3025$9b622d9e@news.freenet.de> NNTP-Posting-Host: 69.3.145.191 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1044332389 732 127.0.0.1 (4 Feb 2003 04:19:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 4 Feb 2003 04:19:49 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25525 "B. Joshua Rosen" wrote in message news:... > > XAPP200 is dated, you want XAPP609. It's so new that it's not listed in > the normal place. To get it goto the support page and use the search > engine to search the app notes. http://support.xilinx.com/xapp/xapp609.pdf ###### From: b_foelsch@hotmail.com (Boris Foelsch) Newsgroups: comp.arch.fpga Subject: Re: Clock Feedback for DDR-SDRAM (XApp200) Date: 3 Feb 2003 20:24:50 -0800 Organization: http://groups.google.com/ Lines: 29 Message-ID: <105d1b62.0302032024.521349d1@posting.google.com> References: <3e362717$0$3025$9b622d9e@news.freenet.de> NNTP-Posting-Host: 69.3.145.191 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1044332690 1242 127.0.0.1 (4 Feb 2003 04:24:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 4 Feb 2003 04:24:50 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:25518 "B. Joshua Rosen" wrote in message news:... > On Mon, 27 Jan 2003 18:02:26 -0500, Florian wrote: > > > Hello, > > i'm designing a board with a VirtexII that takes masses of data from > > several inputs and stores it in 2 DDR-RAM channels. For the > > ram-controller i'm orientating on xapp200. It says to feed the ddr_clk > > and possibly ddr_clkb back into the fpga. My question is how to route > > this feedback on the pcb? I see several possibilities: - shortest way > > from pad to pad > > - from the series termination resitor - from the ram-socket - from the > > parallel termination resitor And how do i terminate this feedback? (DCI > > is not an option) > > > > Any help welcome > > > > Thank You in advance > > Florian > > XAPP200 is dated, you want XAPP609. It's so new that it's not listed in > the normal place. To get it goto the support page and use the search > engine to search the app notes. This is an interesting app note, but really has very little directly to do with the question being put to the group. Anyhow, thanks for letting us know it exists. -Boris