From: "fb" Newsgroups: comp.arch.fpga Subject: USB OPENCORE IP usage Date: Wed, 8 Jan 2003 00:21:03 +0100 Organization: Wanadoo, l'internet avec France Telecom Lines: 16 Message-ID: NNTP-Posting-Host: alille-107-1-13-193.abo.wanadoo.fr X-Trace: news-reader12.wanadoo.fr 1041981674 20980 80.14.15.193 (7 Jan 2003 23:21:14 GMT) X-Complaints-To: abuse@wanadoo.fr NNTP-Posting-Date: 7 Jan 2003 23:21:14 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.usenet-edu.net!usenet-edu.net!wanadoo.fr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24641 Hello, I wonder if any of you ever used the USB described in the fantastic OPENCORE site by Mr Rudolf Usselmann (a Verilog project). I would like to implement it on a Spartan II system (Trenz Electronics kit) that has a built in Philips PDIUSBP11A chip... but the I do not know how to interface to the transcever pins mentioned in the design (txdp, txdn, txoe, rxd, rxdp, rxdn). Could anyone explain me how to do this? Thank you in advance, FB (fba@free.fr) ###### From: Muzaffer Kal Newsgroups: comp.arch.fpga Subject: Re: USB OPENCORE IP usage Organization: DSPIA Inc. Message-ID: References: X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 27 NNTP-Posting-Host: 66.124.254.5 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr17.news.prodigy.com 1041989417 ST000 66.124.254.5 (Tue, 07 Jan 2003 20:30:17 EST) NNTP-Posting-Date: Tue, 07 Jan 2003 20:30:17 EST X-UserInfo1: O@Z[S\OG[JVWCFD[LZKJOPHAWB\^PBQLGPQRZQ]KEYUNDQUCCNSUAACY@L[ZX__HGFD]JBJNSFXTOOGA_VWY^_HG@FW_HUTHOH]TBPGCO\P^PLP^@[GLHUK@WLECKFVL^TYG[@RMWQXIWM[SDDYWNLG_G[_BWUCHFY_Y@AS@Q[B\APPF@DCZM_PG_VSCPQZM Date: Wed, 08 Jan 2003 01:30:17 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!opentransit.net!news-out.cwix.com!newsfeed.cwix.com!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr17.news.prodigy.com.POSTED!857c7983!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24652 On Wed, 8 Jan 2003 00:21:03 +0100, "fb" wrote: >Hello, > >I wonder if any of you ever used the USB described in the fantastic OPENCORE >site by Mr Rudolf Usselmann (a Verilog project). > I would like to implement it on a Spartan II system (Trenz Electronics kit) >that has a built in Philips PDIUSBP11A chip... but the I do not know > how to interface to the transcever pins mentioned in the design (txdp, >txdn, txoe, rxd, rxdp, rxdn). Could anyone explain me how to do this? > >Thank you in advance, > > >FB (fba@free.fr) > > The transceiver has vpo, vmo, oe#, rcv, vp, vm pins. These map to the pins you list in the respective order. You may have to invert the oe (output enable) signal because it is not clear whether the IP's signal is active low or not. The transceiver has active low enable. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations ###### From: fba@free.fr (Frederic Bastenaire) Newsgroups: comp.arch.fpga Subject: Re: USB OPENCORE IP usage Date: 8 Jan 2003 00:43:00 -0800 Organization: http://groups.google.com/ Lines: 56 Message-ID: References: NNTP-Posting-Host: 57.67.17.3 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1042015380 17097 127.0.0.1 (8 Jan 2003 08:43:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 8 Jan 2003 08:43:00 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24646 > >I wonder if any of you ever used the USB described in the fantastic OPENCORE > >site by Mr Rudolf Usselmann (a Verilog project). > > I would like to implement it on a Spartan II system (Trenz Electronics kit) > >that has a built in Philips PDIUSBP11A chip... but the I do not know > > how to interface to the transcever pins mentioned in the design (txdp, > >txdn, txoe, rxd, rxdp, rxdn). Could anyone explain me how to do this? > > > >Thank you in advance, > > > > > >FB (fba@free.fr) > > > > > > The transceiver has vpo, vmo, oe#, rcv, vp, vm pins. These map to the > pins you list in the respective order. You may have to invert the oe > (output enable) signal because it is not clear whether the IP's signal > is active low or not. The transceiver has active low enable. > > Muzaffer Kal > > http://www.dspia.com > ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations Thank you very much for your help. So actually the inferface with the transceiver is really simple... OE# is active low, so no inversion is required. The only little problem is that on my FPGA board, the RCV signal is not routed to the Spartan II. I can easily regenerate it as is is the difference between both USB signals (i.e. (USB+) and not (USB-)), I just hope that it will not introduce subtle timing problems since there will be a small delay with this extra level of logic compared to the other signals that are fed through direcly. I suppose that an extra level of "empty" (buffer or the like) logic could be added to the other "receive" signals to correct the timings if necessary. There are certainly cleaner methods but I am just a newbie and I am not yet 100% familiar with the synchronous design methods so any advice is welcome... Yours, FB Yours, Frederic Bastenaire ###### From: hess@cs.indiana.edu (Caleb Hess) Newsgroups: comp.arch.fpga Subject: Re: USB OPENCORE IP usage Date: Wed, 8 Jan 2003 16:11:32 +0000 (UTC) Organization: Computer Science, Indiana University Lines: 47 Message-ID: References: NNTP-Posting-Host: megamouth.cs.indiana.edu X-Trace: rainier.uits.indiana.edu 1042042292 28532 129.79.246.28 (8 Jan 2003 16:11:32 GMT) X-Complaints-To: news-admin@indiana.edu NNTP-Posting-Date: Wed, 8 Jan 2003 16:11:32 +0000 (UTC) X-Newsreader: trn 4.0-test72 (19 April 1999) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!news.indiana.edu!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24647 In article , Frederic Bastenaire wrote: >> >I wonder if any of you ever used the USB described in the fantastic OPENCORE >> >site by Mr Rudolf Usselmann (a Verilog project). >> > I would like to implement it on a Spartan II system (Trenz Electronics kit) >> >that has a built in Philips PDIUSBP11A chip... but the I do not know >> > how to interface to the transcever pins mentioned in the design (txdp, >> >txdn, txoe, rxd, rxdp, rxdn). Could anyone explain me how to do this? >> > >> >Thank you in advance, >> > >> > >> >FB (fba@free.fr) >> > >> > >> >> The transceiver has vpo, vmo, oe#, rcv, vp, vm pins. These map to the >> pins you list in the respective order. You may have to invert the oe >> (output enable) signal because it is not clear whether the IP's signal >> is active low or not. The transceiver has active low enable. >> >> Muzaffer Kal >> >> http://www.dspia.com >> ASIC/FPGA design/verification consulting specializing in DSP algorithm >implementations > >Thank you very much for your help. > >So actually the inferface with the transceiver is really simple... >OE# is active low, so no inversion is required. The only >little problem is that on my FPGA board, the RCV signal is not routed >to the >Spartan II. You mentioned above that you have a Trenz board. The specs for their TE-XC2SE board show rcv connected to pin B9, vm on C9, and vp on D9. I think your problem will be that the Trenz board has the transceiver mode pin unconnected (mode 1, for differential input on VPO/VMO) while Usselmann's design produces single-ended output requiring mode 0. You should be able to fix this by adding a kludge wire to ground from pin 1 of the PDIUSBP11A chip. -- Caleb Hess hess@cs.indiana.edu