Sender: Andreas Schweizer From: Andreas Schweizer Subject: Unused FPGA I/O Pins? Newsgroups: comp.arch.fpga Organization: ETH Zurich Summary: User-Agent: tin/pre-1.4-980618 (UNIX) (SunOS/5.8 (sun4u)) X-Original-NNTP-Posting-Host: raf6.iiic.ethz.ch Message-ID: <3e119670@core.inf.ethz.ch> Date: 31 Dec 2002 14:06:56 +0100 Lines: 11 NNTP-Posting-Host: core.inf.ethz.ch X-Trace: pfaff.ethz.ch 1041340018 core.inf.ethz.ch (31 Dec 2002 14:06:58 +0200) Path: chonsp.franklin.ch!pfaff.ethz.ch!core.inf.ethz.ch!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24489 Hi everyone, in the design I'm working at, we're using a Virtex-II FPGA in the FG 676 package. Many of the I/O pins are however unused. Is it a good idea to connect these to GND? or leave them unconnected or connect some to GND and some to Vcco? Thank you for reading and a happy 2003 to all! Andy ###### Message-ID: <3E11BEC4.1080500@yahoo.com> From: Kumaran Selvaratnam User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:0.9.4.1) Gecko/20020314 Netscape6/6.2.2 X-Accept-Language: en-us MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Unused FPGA I/O Pins? References: <3e119670@core.inf.ethz.ch> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Lines: 27 Date: Tue, 31 Dec 2002 10:59:00 -0500 NNTP-Posting-Host: 65.95.164.27 X-Complaints-To: abuse@sympatico.ca X-Trace: news20.bellglobal.com 1041350340 65.95.164.27 (Tue, 31 Dec 2002 10:59:00 EST) NNTP-Posting-Date: Tue, 31 Dec 2002 10:59:00 EST Organization: Bell Sympatico Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.cwix.com!torn!webster!nf1.bellglobal.com!nf2.bellglobal.com!news20.bellglobal.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24512 Hi Andreas, I am not familiar with FG 676 but in general, you have to drive the inputs and leave the outputs unconnected. However, for specific information consult the datasheets of the particular FPGA you are planning to use. This is what chip companies suggest. Some of the chips provide I/O Configuration setup that can be done internally through software means. Good Luck Kumaran Andreas Schweizer wrote: > Hi everyone, > > in the design I'm working at, we're using a Virtex-II > FPGA in the FG 676 package. Many of the I/O pins are > however unused. Is it a good idea to connect these > to GND? or leave them unconnected or connect some to > GND and some to Vcco? > > Thank you for reading and a happy 2003 to all! > Andy > > ###### From: Spam Hater Newsgroups: comp.arch.fpga Subject: Re: Unused FPGA I/O Pins? Message-ID: <79o61v4rulgf8ovile10oh1hsa9v8ehcjf@4ax.com> References: <3e119670@core.inf.ethz.ch> <3E11E669.25556022@xilinx.com> X-Newsreader: Forte Free Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 17 NNTP-Posting-Host: 216.103.91.29 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr14.news.prodigy.com 1041458237 ST000 216.103.91.29 (Wed, 01 Jan 2003 16:57:17 EST) NNTP-Posting-Date: Wed, 01 Jan 2003 16:57:17 EST Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: [[O]BZSEYRVARUH]^JKBOW@@YJ_ZTB\MV@BNMRQIMASJETAANVW[AKWZE\]^XQWIGNE_[EBL@^_\^JOCQ^RSNVLGTFTKHTXHHP[NB\_C@\SD@EP_[KCXX__AGDDEKGFNB\ZOKLRNCY_CGG[RHT_UN@C_BSY\G__IJIX_PLSA[CCFAULEY\FL\VLGANTQQ]FN Date: Wed, 01 Jan 2003 21:57:17 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.stealth.net!news.stealth.net!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr14.news.prodigy.com.POSTED!d8e5a829!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24540 Hi Peter, Just so you know, the published (Xilinx) documentation recommends otherwise. I forget where I saw it; it was either in an App Note, or in an ISE output file (PAR? MAP?), but it said to tie the unused pins to ground with a 10K resistor. $.02, SH On Tue, 31 Dec 2002 10:48:10 -0800, Peter Alfke wrote: >If they are unused, just leave them unconnected. ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Unused FPGA I/O Pins? Date: Wed, 01 Jan 2003 15:35:06 -0800 Organization: Xilinx,Inc Lines: 35 Message-ID: <3E137B29.FCDE46E4@xilinx.com> References: <3e119670@core.inf.ethz.ch> <3E11E669.25556022@xilinx.com> <79o61v4rulgf8ovile10oh1hsa9v8ehcjf@4ax.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Spam Hater Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.wirehub.nl!news2.euro.net!news.stealth.net!news.stealth.net!204.127.161.156.MISMATCH!wn12feed!worldnet.att.net!12.120.4.37!attcg2!attdv2!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24523 Nothing wrong with that recommendation, but overly cautious, in my optinion. The resistor (instead of a short) protects against accidental misconfiguration, the resistor ( instead of open, with internal pull-up or -down) protects against crosstalk, which would not do any harm anyhow since the input signal is not used. My suggestion is more constructive, since it achieves lower ground bounce. There are many ways to "skin a cat" Happy New Year Peter Alfke ============ Spam Hater wrote: > Hi Peter, > > Just so you know, the published (Xilinx) documentation recommends > otherwise. > > I forget where I saw it; it was either in an App Note, or in an ISE > output file (PAR? MAP?), but it said to tie the unused pins to ground > with a 10K resistor. > > $.02, > SH > > On Tue, 31 Dec 2002 10:48:10 -0800, Peter Alfke > wrote: > > >If they are unused, just leave them unconnected. ###### Sender: Andreas Schweizer From: Andreas Schweizer Subject: Re: Unused FPGA I/O Pins? Newsgroups: comp.arch.fpga References: <3e119670@core.inf.ethz.ch> <3E11E669.25556022@xilinx.com> Organization: ETH Zurich User-Agent: tin/pre-1.4-980618 (UNIX) (SunOS/5.8 (sun4u)) X-Original-NNTP-Posting-Host: raf6.iiic.ethz.ch Message-ID: <3e140da7@core.inf.ethz.ch> Date: 2 Jan 2003 11:00:07 +0100 Lines: 26 NNTP-Posting-Host: core.inf.ethz.ch X-Trace: pfaff.ethz.ch 1041501609 core.inf.ethz.ch (2 Jan 2003 11:00:09 +0200) Path: chonsp.franklin.ch!pfaff.ethz.ch!core.inf.ethz.ch!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24524 Peter Alfke wrote: > That way you have additional ground connections from the inside to the > ground plane, and although the resistive part may be not perfect, all > the lead inductances are in parallel, and thus reduce the inductive > kick. Thank you for your help and also "es guets Neu's", as we say in Switzerland ;-) > Happy New Year und ein Gutes Neues Jahr, hoffentlich besser als 2002. > Peter Alfke, Xilinx Applications > ============================= > Andreas Schweizer wrote: >> Hi everyone, >> >> in the design I'm working at, we're using a Virtex-II >> FPGA in the FG 676 package. Many of the I/O pins are >> however unused. Is it a good idea to connect these >> to GND? or leave them unconnected or connect some to >> GND and some to Vcco? >> >> Thank you for reading and a happy 2003 to all! >> Andy ###### From: Thomas Kurth Newsgroups: comp.arch.fpga Subject: Re: Unused FPGA I/O Pins? Date: Fri, 3 Jan 2003 09:51:20 +0100 Lines: 24 Message-ID: References: <3e119670@core.inf.ethz.ch> NNTP-Posting-Host: p3e9b9c15.dip.t-dialin.net (62.155.156.21) X-Trace: fu-berlin.de 1041583798 12331863 62.155.156.21 (16 [165338]) X-Newsreader: MicroPlanet Gravity v2.50 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fu-berlin.de!uni-berlin.de!p3e9b9c15.dip.t-dialin.NET!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24556 Heyho Andy, I've read all the thread (since now) and think it is a good option to tie them to GND. But it maybe useful to tie some of them via a resistor (might even be 0 Ohm) to GND. Like that you have the possibility to connect easily any testsignals or signals that you forgot in your layout. Just take the resistor of and you get another accessible IOO of your FPGA. I always do this, it makes debugging more easy. Just think about putting an internal signal on the pin in order to analyze it... It helped me often... I wish you all a happy, successful and healthy new year! ("Happy new year, Miss Sophy" for those who know "Dinner for one" :o) ) Be readin' ya, Thomas -- No matter if you are going on-piste or off-piste just hit the slope and stay healthy! For email-reply replace "nospam" with "kurth". ###### From: "svhb" Newsgroups: comp.arch.fpga References: <3e119670@core.inf.ethz.ch> Subject: Re: Unused FPGA I/O Pins? Date: Mon, 6 Jan 2003 12:49:46 +0100 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Lines: 36 Message-ID: <3e196cb5$0$212$4d4efb8e@news.be.uu.net> NNTP-Posting-Host: uu194-7-153-18.unknown.uunet.be X-Trace: 1041853621 news.be.uu.net 212 194.7.153.18 X-Complaints-To: abuse@be.uu.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!newsfeed.freenet.de!195.129.110.18.MISMATCH!bnewspeer00.bru.ops.eu.uu.net!bnewspost00.bru.ops.eu.uu.net!emea.uu.net!news.be.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:24594 "Thomas Kurth" wrote in message news:MPG.187f6d7072fbd7d5989683@news.cis.dfn.de... > Heyho Andy, > > I've read all the thread (since now) and think it is a good option to tie > them to GND. But it maybe useful to tie some of them via a resistor > (might even be 0 Ohm) to GND. Like that you have the possibility to > connect easily any testsignals or signals that you forgot in your layout. > Just take the resistor of and you get another accessible IOO of your > FPGA. I always do this, it makes debugging more easy. Just think about > putting an internal signal on the pin in order to analyze it... It helped > me often... The good point is a testpoint. You can leave them open, and if you don't need them anymore, use them as output to ground or Vcc so they will not float. > > I wish you all a happy, successful and healthy new year! ("Happy new > year, Miss Sophy" for those who know "Dinner for one" :o) ) > > Be readin' ya, > > Thomas > > -- > > No matter if you are going on-piste or off-piste just hit the slope and > stay healthy! > > For email-reply replace "nospam" with "kurth".