Message-ID: <3df47975@pfaff.ethz.ch> From: Matthias Dyer Subject: virtex output pin voltage Newsgroups: comp.arch.fpga Date: Mon, 09 Dec 2002 12:07:33 +0100 Lines: 17 Organization: ETH Zurich User-Agent: KNode/0.6.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit NNTP-Posting-Host: tec32.ethz.ch X-Trace: pfaff.ethz.ch 1039432053 tec32.ethz.ch (9 Dec 2002 12:07:33 +0200) Path: chonsp.franklin.ch!pfaff.ethz.ch Xref: chonsp.franklin.ch comp.arch.fpga:23836 On a Virtex FPGA, if I shut down vccint but keep vcco, what level do the pads have? High impedance? Same as when vcco is down? Thanks, Matthias -- ------------------------------------------------------------- Matthias Dyer phone: +41-1-6327061 Gloriastr. 35, ETZ G-63, fax: +41-1-6321035 CH-8092 Zurich, Switzerland email: dyer@tik.ee.ethz.ch Computer Engineering and Networks Lab (TIK) Swiss Federal Institute of Technology (ETH) Zuerich ------------------------------------------------------------- ###### Message-ID: <3df47975@pfaff.ethz.ch> From: Matthias Dyer Subject: virtex output pin voltage Newsgroups: comp.arch.fpga Date: Mon, 09 Dec 2002 12:07:33 +0100 Lines: 17 Organization: ETH Zurich User-Agent: KNode/0.6.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit NNTP-Posting-Host: tec32.ethz.ch X-Trace: pfaff.ethz.ch 1039432053 tec32.ethz.ch (9 Dec 2002 12:07:33 +0200) Path: chonsp.franklin.ch!pfaff.ethz.ch Xref: chonsp.franklin.ch comp.arch.fpga:23836 On a Virtex FPGA, if I shut down vccint but keep vcco, what level do the pads have? High impedance? Same as when vcco is down? Thanks, Matthias -- ------------------------------------------------------------- Matthias Dyer phone: +41-1-6327061 Gloriastr. 35, ETZ G-63, fax: +41-1-6321035 CH-8092 Zurich, Switzerland email: dyer@tik.ee.ethz.ch Computer Engineering and Networks Lab (TIK) Swiss Federal Institute of Technology (ETH) Zuerich ------------------------------------------------------------- ###### From: mrand@my-deja.com (Marc Randolph) Newsgroups: comp.arch.fpga Subject: Re: virtex output pin voltage Date: 9 Dec 2002 12:53:13 -0800 Organization: http://groups.google.com/ Lines: 29 Message-ID: <15881dde.0212091253.574b0c5@posting.google.com> References: <3df47975@pfaff.ethz.ch> <3DF4B833.CE84362C@xilinx.com> NNTP-Posting-Host: 65.192.92.132 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1039467193 8262 127.0.0.1 (9 Dec 2002 20:53:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 9 Dec 2002 20:53:13 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:23824 Austin Lesea wrote in message news:<3DF4B833.CE84362C@xilinx.com>... > On the Virtex Family (E, II, II Pro), the IO assumes the tristate condtion, > as an internal power down signal is sensed, which sets the IOs to the high > impedance state. > > When Vcco is lost, on II and II Pro, there are intrinsic diodes as part of > the IO structure that go into forward conduction as Vcco falls to 0V, and > the IO pins are above ground. About 2 mA (total) is sufficient to bias up a > bank through all of the IOs (through the diodes). As long as a number of > IOs are high, the FPGA IOs will appear to be tristate. > > Austin Austin, Can you describe the power-up sequence in the same fashion? I just discovered that it appears as if, during power-up (as the voltage rails are coming online), the Virtex II brings the I/O voltage up at the same time the power rail is coming up. I'm not saying that the FPGA is necessarily driving it ... maybe this is before the I/O goes tri-state during configuration - or maybe since the bus isn't being driven, the power-up voltage is "leaking" through? A particular vendor memory I have hanging off the FPGA appears to be sensitive to transitions on control lines during power-up. Thank you, Marc