From: "alla" Newsgroups: comp.arch.fpga Subject: FPGA convert to ASIC Date: Thu, 31 Oct 2002 15:15:32 -0600 Organization: Texas Instruments Lines: 6 Message-ID: NNTP-Posting-Host: cna0212289.dhcp.itg.ti.com X-Trace: tilde.itg.ti.com 1036098569 12717 172.25.36.49 (31 Oct 2002 21:09:29 GMT) X-Complaints-To: usenet@news.ti.com NNTP-Posting-Date: 31 Oct 2002 21:09:29 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!triton.net!smallfeed.triton.net!nntp1.hal-pc.org!attdl1!ip.att.net!news.ti.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22731 Just want see anyone here has any experience of converting a Xilinx FPGA design into an ASIC implementation. If so, which vendor did you use? What's the cost? Are you happy with the result? We are using the Virtex series and considering this option. Thanks ###### From: "Bezamat James" Newsgroups: comp.arch.fpga Subject: Re: FPGA convert to ASIC Date: Fri, 1 Nov 2002 08:43:50 +0100 Organization: Wanadoo, l'internet avec France Telecom Lines: 26 Message-ID: References: Reply-To: "Bezamat James" NNTP-Posting-Host: atoulon-103-1-4-254.abo.wanadoo.fr X-Trace: news-reader11.wanadoo.fr 1036136870 8314 80.15.109.254 (1 Nov 2002 07:47:50 GMT) X-Complaints-To: abuse@wanadoo.fr NNTP-Posting-Date: 1 Nov 2002 07:47:50 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!teaser.fr!freenix!wanadoo.fr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22768 Hello, Every thing is possible, and retargetting FPGA to ASIC, or ASIC to FPGA is a common activitie for design centers. The main factors are technicals and financials : - A digital design, with very small limitations in term of gate number, memory size, use of IPs, macro blocks, frequency and so on (FPGA capabilities are, today, not so far from ASIC-pure digital- capabilities). Regards James -- James BEZAMAT bezamat.james@wanadoo.fr "alla" a écrit dans le message de news: aps669$cdd$1@tilde.itg.ti.com... > Just want see anyone here has any experience of converting a Xilinx FPGA > design into an ASIC implementation. If so, which vendor did you use? What's > the cost? Are you happy with the result? We are using the Virtex series and > considering this option. Thanks > > ###### From: kayrock66@yahoo.com (Jay) Newsgroups: comp.arch.fpga Subject: Re: FPGA convert to ASIC Date: 1 Nov 2002 15:22:49 -0800 Organization: http://groups.google.com/ Lines: 29 Message-ID: References: NNTP-Posting-Host: 66.81.26.104 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1036192970 17770 127.0.0.1 (1 Nov 2002 23:22:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 1 Nov 2002 23:22:50 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22777 I've done a few FPGA prototypes of designs that we knew in advance were going to be ASICs. We used TSMC and IBM. I never heard the price on the TSMC and I think IBM was charging something like $400k for chip #1. However, expect foundries to be very agreeable these days on account of the surplus capacity. The results went fine, because usually, by the time you've worked out all the bugs to get the FPGA to work in the lab, you've solved most of your problems. Also FPGA use sort of forces a certain level of simplicity with repect to clocking. A BIG FPGA turns into a small ASIC because of the difference in area efficiency. Also, expect about a 4X speed-up going to ASIC. And of course, yes you can hand place, super pipeline, embedded multiplier, etc your FPGA to get a faster design, but I'm speaking in general for random logic writen by your average ASIC designer, not spending all the time to get so deep into the implimentation details. President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- "alla" wrote in message news:... > Just want see anyone here has any experience of converting a Xilinx FPGA > design into an ASIC implementation. If so, which vendor did you use? What's > the cost? Are you happy with the result? We are using the Virtex series and > considering this option. Thanks ###### From: prashantj@usa.net (Prashant) Newsgroups: comp.arch.fpga Subject: Re: FPGA convert to ASIC Date: 4 Nov 2002 08:43:53 -0800 Organization: http://groups.google.com/ Lines: 48 Message-ID: References: NNTP-Posting-Host: 64.207.24.62 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1036428233 30540 127.0.0.1 (4 Nov 2002 16:43:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 4 Nov 2002 16:43:53 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22807 Jay, That was very informative and I had a question for you. When you say "a large FPGA design into a small ASIC and 4x speedup", are there any constraints to it OR will all designs of FPGA result into such a speedup and area reduction. I understand why the area reduction and speedup occur. Its just the factor by which they occur that I'm not sure about. What would you say for a design that uses 20,000 LEs in an Altera Apex20K1500E device and about 40,000 bits of internal RAM working @ 40 MHz ? Would such a design speed up 4 times when converted to ASIC ? I understand that the speed up numbers would vary from design to design. But there must be a minimum and maximum possible numbers ? Interested in your comments. Thanks, Prashant kayrock66@yahoo.com (Jay) wrote in message news:... > I've done a few FPGA prototypes of designs that we knew in advance > were going to be ASICs. We used TSMC and IBM. I never heard the > price on the TSMC and I think IBM was charging something like $400k > for chip #1. However, expect foundries to be very agreeable these > days on account of the surplus capacity. The results went fine, > because usually, by the time you've worked out all the bugs to get the > FPGA to work in the lab, you've solved most of your problems. Also > FPGA use sort of forces a certain level of simplicity with repect to > clocking. A BIG FPGA turns into a small ASIC because of the > difference in area efficiency. Also, expect about a 4X speed-up going > to ASIC. And of course, yes you can hand place, super pipeline, > embedded multiplier, etc your FPGA to get a faster design, but I'm > speaking in general for random logic writen by your average ASIC > designer, not spending all the time to get so deep into the > implimentation details. > > President, Quadrature Peripherals > Altera, Xilinx and Digital Design Consulting > email: kayrock66@yahoo.com > http://fpga.tripod.com > ----------------------------------------------------------------------------- > > > > "alla" wrote in message news:... > > Just want see anyone here has any experience of converting a Xilinx FPGA > > design into an ASIC implementation. If so, which vendor did you use? What's > > the cost? Are you happy with the result? We are using the Virtex series and > > considering this option. Thanks ###### From: johnjakson@yahoo.com (john jakson) Newsgroups: comp.arch.fpga Subject: Re: FPGA convert to ASIC Date: 5 Nov 2002 03:04:17 -0800 Organization: http://groups.google.com/ Lines: 26 Message-ID: References: NNTP-Posting-Host: 24.60.58.247 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1036494257 13026 127.0.0.1 (5 Nov 2002 11:04:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 5 Nov 2002 11:04:17 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22838 I would tend to aggree with Jay, but with the caveats, If the design is hardly pipelined at all, you are replacing every LUT with an actual std cell gate, the speed difference is easily 10x since ASICs use small srams too & they are generally 10x slower than gates. If the design is super pipelined, then the flops are the same and only the switched wires remain. I would hazard a 2x speed difference. So top of the line FPGA design with real logic in the paths may go from 100-200MHz but most ASICs can be designed upto say 400-500MHz depending on tools, manpower & budget. Now any ASIC running at at say 400MHz could likely run at 2GHz if you have a couple of hundred EEs and use schematic entry & spice for everything, but those projects are few & far between (AMD/Intel). I had the reverse project, a mixed signal ASIC easily ran at 30MHz limited by analog blocks. The digital probably could have run 50MHz no sweat (AMI 0.6u mixed cmos). When the digital was extracted and dumped into a X4085 it ran barely 1MHz. The digital design was trashed and a more pipelined design eventually was able to get back to the system clock. The ASIC had some paths that might have been 100 levels of logic. BTW AMI is in the FPGA to ASIC conversion business, but our project never reached escape velocity. ###### From: Muzaffer Kal Newsgroups: comp.arch.fpga Subject: Re: FPGA convert to ASIC Organization: DSPIA Inc. Message-ID: References: X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 37 NNTP-Posting-Host: 64.171.254.53 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr13.news.prodigy.com 1036995620 ST000 64.171.254.53 (Mon, 11 Nov 2002 01:20:20 EST) NNTP-Posting-Date: Mon, 11 Nov 2002 01:20:20 EST X-UserInfo1: SCSYASRDAJWWCQLY\BCBNWX@RJ_XPDLMN@GZ_GYO^BTBTSUBYFWEAE[YJLYPIWKHTFCMZKVMB^[Z^DOBRVVMOSPFHNSYXVDIE@X\BUC@GTSX@DL^GKFFHQCCE\G[JJBMYDYIJCZM@AY]GNGPJD]YNNW\GSX^GSCKHA[]@CCB\[@LATPD\L@J\\PF]VR[QPJN Date: Mon, 11 Nov 2002 06:20:20 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!rip!news.webusenet.com!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr13.news.prodigy.com.POSTED!857c7983!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22986 On 4 Nov 2002 08:43:53 -0800, prashantj@usa.net (Prashant) wrote: >Jay, >That was very informative and I had a question for you. When you say >"a large FPGA design into a small ASIC and 4x speedup", are there any >constraints to it OR will all designs of FPGA result into such a >speedup and area reduction. I understand why the area reduction and >speedup occur. Its just the factor by which they occur that I'm not >sure about. What would you say for a design that uses 20,000 LEs in an >Altera Apex20K1500E device and about 40,000 bits of internal RAM >working @ 40 MHz ? Would such a design speed up 4 times when converted >to ASIC ? I understand that the speed up numbers would vary from >design to design. But there must be a minimum and maximum possible >numbers ? Interested in your comments. In my experience the scale is from 3 to 5 times speed increase and it depends on what you can get from the fpga. With Apex20 and 40 MHz, it is very likely that you can get at least 150MHz with a .25u process and 200 MHz from a .18u process. It also is limited by the maximum speed one can get from a SC (standard cell) methodology. With .25u that's more or less limited to 300MHz unless you do very small blocks and do manual placement etc etc so it is very difficult to get a 4x improvement for any fpga design above 80 MHz. With .18u the maximum is around 400 MHz. These are again assuming designs done by "regular" designers. If design is RLOC'ed to the limit with only one close LUT between two flops then probably you can't make it more than 2x faster. It also depends on what process the fpga is running. Virtex II is done with a .13u copper process so any SC flow above .25u won't be too competitive. If you do full custom with dynamic circuit design, of course, all bets are off. Intel and AMD had designs running at 1GHz on their .25u processes. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations ###### From: kayrock66@yahoo.com (Jay) Newsgroups: comp.arch.fpga Subject: Re: FPGA convert to ASIC Date: 11 Nov 2002 00:01:40 -0800 Organization: http://groups.google.com/ Lines: 61 Message-ID: References: NNTP-Posting-Host: 66.81.17.142 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1037001701 31746 127.0.0.1 (11 Nov 2002 08:01:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 11 Nov 2002 08:01:41 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22973 Those are rule of thumb numbers so people can get some idea of what reality is instead of saying something nebulous like "speeds and densities in conversions will vary so I'm not going to tell you anything specific". That always drives me nuts when I get that kind of smoke blowing. President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- prashantj@usa.net (Prashant) wrote in message news:... > Jay, > That was very informative and I had a question for you. When you say > "a large FPGA design into a small ASIC and 4x speedup", are there any > constraints to it OR will all designs of FPGA result into such a > speedup and area reduction. I understand why the area reduction and > speedup occur. Its just the factor by which they occur that I'm not > sure about. What would you say for a design that uses 20,000 LEs in an > Altera Apex20K1500E device and about 40,000 bits of internal RAM > working @ 40 MHz ? Would such a design speed up 4 times when converted > to ASIC ? I understand that the speed up numbers would vary from > design to design. But there must be a minimum and maximum possible > numbers ? Interested in your comments. > > Thanks, > Prashant > > > > kayrock66@yahoo.com (Jay) wrote in message news:... > > I've done a few FPGA prototypes of designs that we knew in advance > > were going to be ASICs. We used TSMC and IBM. I never heard the > > price on the TSMC and I think IBM was charging something like $400k > > for chip #1. However, expect foundries to be very agreeable these > > days on account of the surplus capacity. The results went fine, > > because usually, by the time you've worked out all the bugs to get the > > FPGA to work in the lab, you've solved most of your problems. Also > > FPGA use sort of forces a certain level of simplicity with repect to > > clocking. A BIG FPGA turns into a small ASIC because of the > > difference in area efficiency. Also, expect about a 4X speed-up going > > to ASIC. And of course, yes you can hand place, super pipeline, > > embedded multiplier, etc your FPGA to get a faster design, but I'm > > speaking in general for random logic writen by your average ASIC > > designer, not spending all the time to get so deep into the > > implimentation details. > > > > President, Quadrature Peripherals > > Altera, Xilinx and Digital Design Consulting > > email: kayrock66@yahoo.com > > http://fpga.tripod.com > > ----------------------------------------------------------------------------- > > > > > > > > "alla" wrote in message news:... > > > Just want see anyone here has any experience of converting a Xilinx FPGA > > > design into an ASIC implementation. If so, which vendor did you use? What's > > > the cost? Are you happy with the result? We are using the Virtex series and > > > considering this option. Thanks