From: Bob W Newsgroups: comp.arch.fpga Subject: Why can Xilinx sw be as good as Altera's sw? Message-ID: X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 111 NNTP-Posting-Host: 24.91.219.183 X-Complaints-To: abuse@attbi.com X-Trace: sccrnsc03 1034101898 24.91.219.183 (Tue, 08 Oct 2002 18:31:38 GMT) NNTP-Posting-Date: Tue, 08 Oct 2002 18:31:38 GMT Organization: AT&T Broadband Date: Tue, 08 Oct 2002 18:31:38 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!proxad.net!news-hub.cableinet.net!blueyonder!nntp2.aus1.giganews.com!nntp.giganews.com!wn12feed!wn14feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!sccrnsc03.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21760 Why can’t Xilinx Software be as good as Altera Software? I am an independent consultant developing FPGAs and PLDs using both Xilinx and Altera development software. My clients usually have a preference between Altera and Xilinx. From a hardware perspective, I can do most designs just as well with either part. I just wish that Xilinx could produce development tools that are as a good as those provided by Altera. The Altera tools are such a pleasure to use. The tools are very well integrated into a single Windows program. They have a consistent user across the toolset. Any time an error occurs, a single click brings you to the source of the error. The help files provide useful information. The Xilinx toolset is a hodgepodge of command line tools with a lousy user interface on top of it. The tools don’t talk to each other, the error handling is terrible and the help files are useless. An analogy comes to mind. I would compare the Altera software to a sports car and the Xilinx to a donkey. Both modes of transportation will get you where you want to go. The sports car has an enjoyable ride. The donkey gets you there eventually, but the ride stinks. Here are a few (there are many more) of the typical problems I see when using Xilinx ISE: 1) When an error comes up, it usually has a non-descriptive name. If I double click on the error, most of the time it does not show the source of the error. 2) If it does show me the error, it is usually at some intermediate code, not at the source. For example, if there is a section of the design done in schematic capture, the program will show a VHDL file with an error, rather than pulling up the schematic and showing the source of the error. 3) Sometimes the error message will say that something is off grid (Error point not on primary grid) on the schematic at x=1608 y=1504 and expect me to open the schematic and hunt for the X,Y location. If the program knows the location, it should be able to open the schematic and highlight the error for me. 4) The schematic program has an error checker (Tool| Check Schematic) to help find errors in the schematic. After it you correct them you can run the tool again. Many times it will still show at least one error after all of them have been fixed. If you exit the schematic program, then reopen the schematic, and run the error checker it will show no errors. 5) Since the Xilinx Project Navigator is just a collection of separate programs and third party utilities, they each have a different user interface. Each program requires different keystrokes to do the same thing. For example, in the Schematic program, Zoom-in is F8, in the State Cad program it is CTL+PgUp, in ChipView (F7). 6) Options have to be set within many different separate programs. To set some options you may have to click on the Synthesizer, than the Fitter, then the Program file generator. 7) Sometimes when you edit the pins assignments, save them in Chipview, and then try to recompile the design nothing happens. You have to remember that as long as Chipview is open, the Project Navigator will ignore you and not show any reason why. (Oh yeah, I have to close that program before it will respond). 8) Once you close the program (and you have a file viewed in the main Navigator pane) it still fails to respond. This is because there is a “NOTICE” dialog box asking you if want use the changes you just made. However, this dialog box is not visible on the screen. It is hidden behind the other windows because the programmers failed to make it a global modal dialog box. The only indication (other than Navigator stops responding) is A Notice window on the Windows taskbar at the bottom of the screen. 9) I try to run the included ModelSim simulator. The ModelSim splash screen comes up but nothing happens. The program doesn’t start. The Project Navigator shows no error. After much wasted time, I find that the license for the simulator is tied to the IP address of the computer it is used on. Since I was using a laptop, its IP address depends on where it is plugged in. So I need a license for each IP address my laptop uses. There was no error message (How about “Invalid License!”) from Navigator or ModelSim. This is poor software integration. There are just a few examples of the types of problems that users have to live with. The Xilinx software is certainly usable and I have done many designs with it. It just makes things much harder than they should be. As a consultant, I appreciate well written tools save me time and my clients money. The Xilinx tools are poorly written and integrated. It has been like this for years. The new release (5.1) is not much better. Maybe if you have the major market share like Xilinx does, you don’t have to care about the developers. Many Xilinx users have never tried the Altera software and don’t know what they are missing. The Altera tools have a consistent interface and were written to run in a Windows environment. They have an intuitive feel. The utilities are so well written that you never leave the main program to run them. They all look like part of the same program. There are no programs to open and close in the right sequence. The errors codes give meaningful descriptions. More detailed descriptions can be found be clicking on the help button. Double clicking on an error brings you back to the actual source of the error! All of the options are set within the one main program. I have no interest in encouraging people to use Altera over Xilinx. I want Xilinx to write software that is as good as Altera’s. Since I use both packages, I would rather see Xilinx take the challenge and improve their tools. Bob ###### From: "Ken Mac" Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Tue, 8 Oct 2002 19:26:48 +0000 (UTC) Organization: BT Openworld Lines: 58 Message-ID: References: NNTP-Posting-Host: host217-36-22-212.in-addr.btopenworld.com X-Trace: paris.btinternet.com 1034105208 12483 217.36.22.212 (8 Oct 2002 19:26:48 GMT) X-Complaints-To: news-complaints@lists.btinternet.com NNTP-Posting-Date: Tue, 8 Oct 2002 19:26:48 +0000 (UTC) X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MSMail-Priority: Normal X-Priority: 3 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!newsr1.ipcore.viaginterkom.de!btnet-peer1!btnet-peer0!btnet-feed5!btnet!news.btopenworld.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21751 Bob, I am a Xilinx user and I haven't tried Altera software (due to the fact that I only have Xilinx devices!). Why do you think Xilinx does have the major market share? If hardware implementations on FPGA continue to start being developed from a software perspective (Handel-C, System-C etc.), do you think Xilinx will retain their dominance given that software developers (who will apparently eventually being writing software that ends up directly on hardware (!) -) ) are used to advanced, slick GUIs such as Microsoft Visual Studio etc.? Won't they prefer Alteras software then and if designs can be done on either Xilinx or Altera - why not choose the tool they feel most comfortable with? Or will hardware advantages still be the most important factor? I think I remmber Ray Andraka (http://www.andraka.com/) saying (apologies if I am wrong) that he puts Xilinx slightly over Altera for DSP designs due to the so useful SRL16 elements - DSP on FPGA is very much going to explode over the next decade I believe - will DSP related features determine who gets the biggest market share? I don't have your frame of reference to compare the Xilinx tools with their Altera equivalents but I know that I sometimes feel that the tools don't really want to talk to me that much and would rather just be left alone rather than be made to produce bitstreams and provide a pleasant development experience - sort of like a grumpy old man that lives in a cave. Thanks for the post - good to hear real experiences. Cheers, Ken > Maybe if you have the major market share like Xilinx > does, you don't have to care about the developers. Many Xilinx users > have never tried the Altera software and don't know what they are > missing. > > I have no interest in encouraging people to use Altera over Xilinx. I > want Xilinx to write software that is as good as Altera's. Since I use > both packages, I would rather see Xilinx take the challenge and > improve their tools. --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.394 / Virus Database: 224 - Release Date: 03/10/2002 ###### From: "Mike R." Newsgroups: comp.arch.fpga References: Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Tue, 8 Oct 2002 21:55:41 +0200 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Lines: 136 Message-ID: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> NNTP-Posting-Host: 1Cust115.tnt1.muc2.deu.da.uu.net X-Trace: 1034106522 read.news.de.uu.net 194 149.225.4.115 X-Complaints-To: abuse@de.uu.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!newsfeed.online.be!bnewspeer00.bru.ops.eu.uu.net!bnewsifeed00.bru.ops.eu.uu.net!bnewspost00.bru.ops.eu.uu.net!emea.uu.net!read.news.de.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21757 I agree with all of your statements. The new ISE IDE is also worse than the old Foundation IDE. As a special gift, xilinx doesn' t support the synopsys fpga compiler which is a rocket compared to the xilinx synthesis tool. Of course we can use Synplify, but each compiler has its own life. I liked to work with fpga express. The xilinx compiler also has lots of bugs and is not able to handle large projects. And the spartan (4000 architecture) devices aren' t supported any more. I use them in lots of boards with flash size limited microcontrollers for configuration. Furthermore a xilinx FAE told me that the fpga editor also died because of a canceled contract with the manufacturer. This is a core tool which is a must for fast verification of correct synthesis etc. XILINX your chips are the best, but the SW needs lots of improvements ! MIKE "Bob W" schrieb im Newsbeitrag news:n096qu88m768a2n6eb5u30b7n8oq1ratkr@4ax.com... > Why can't Xilinx Software be as good as Altera Software? > > I am an independent consultant developing FPGAs and PLDs using both > Xilinx and Altera development software. My clients usually have a > preference between Altera and Xilinx. From a hardware perspective, I > can do most designs just as well with either part. I just wish that > Xilinx could produce development tools that are as a good as those > provided by Altera. > > The Altera tools are such a pleasure to use. The tools are very well > integrated into a single Windows program. They have a consistent user > across the toolset. Any time an error occurs, a single click brings > you to the source of the error. The help files provide useful > information. > > The Xilinx toolset is a hodgepodge of command line tools with a lousy > user interface on top of it. The tools don't talk to each other, the > error handling is terrible and the help files are useless. An analogy > comes to mind. I would compare the Altera software to a sports car and > the Xilinx to a donkey. Both modes of transportation will get you > where you want to go. The sports car has an enjoyable ride. The donkey > gets you there eventually, but the ride stinks. > > Here are a few (there are many more) of the typical problems I see > when using Xilinx ISE: > > 1) When an error comes up, it usually has a non-descriptive name. If I > double click on the error, most of the time it does not show the > source of the error. > > 2) If it does show me the error, it is usually at some intermediate > code, not at the source. For example, if there is a section of the > design done in schematic capture, the program will show a VHDL file > with an error, rather than pulling up the schematic and showing the > source of the error. > > 3) Sometimes the error message will say that something is off grid > (Error point not on primary grid) on the schematic at x=1608 y=1504 > and expect me to open the schematic and hunt for the X,Y location. If > the program knows the location, it should be able to open the > schematic and highlight the error for me. > > 4) The schematic program has an error checker (Tool| Check Schematic) > to help find errors in the schematic. After it you correct them you > can run the tool again. Many times it will still show at least one > error after all of them have been fixed. If you exit the schematic > program, then reopen the schematic, and run the error checker it will > show no errors. > > 5) Since the Xilinx Project Navigator is just a collection of separate > programs and third party utilities, they each have a different user > interface. Each program requires different keystrokes to do the same > thing. For example, in the Schematic program, Zoom-in is F8, in the > State Cad program it is CTL+PgUp, in ChipView (F7). > > 6) Options have to be set within many different separate programs. To > set some options you may have to click on the Synthesizer, than the > Fitter, then the Program file generator. > > 7) Sometimes when you edit the pins assignments, save them in > Chipview, and then try to recompile the design nothing happens. You > have to remember that as long as Chipview is open, the Project > Navigator will ignore you and not show any reason why. (Oh yeah, I > have to close that program before it will respond). > > 8) Once you close the program (and you have a file viewed in the main > Navigator pane) it still fails to respond. This is because there is a > "NOTICE" dialog box asking you if want use the changes you just made. > However, this dialog box is not visible on the screen. It is hidden > behind the other windows because the programmers failed to make it a > global modal dialog box. The only indication (other than Navigator > stops responding) is A Notice window on the Windows taskbar at the > bottom of the screen. > > 9) I try to run the included ModelSim simulator. The ModelSim splash > screen comes up but nothing happens. The program doesn't start. The > Project Navigator shows no error. After much wasted time, I find that > the license for the simulator is tied to the IP address of the > computer it is used on. Since I was using a laptop, its IP address > depends on where it is plugged in. So I need a license for each IP > address my laptop uses. There was no error message (How about "Invalid > License!") from Navigator or ModelSim. This is poor software > integration. > > There are just a few examples of the types of problems that users have > to live with. The Xilinx software is certainly usable and I have done > many designs with it. It just makes things much harder than they > should be. As a consultant, I appreciate well written tools save me > time and my clients money. The Xilinx tools are poorly written and > integrated. It has been like this for years. The new release (5.1) is > not much better. Maybe if you have the major market share like Xilinx > does, you don't have to care about the developers. Many Xilinx users > have never tried the Altera software and don't know what they are > missing. > > The Altera tools have a consistent interface and were written to run > in a Windows environment. They have an intuitive feel. The utilities > are so well written that you never leave the main program to run them. > They all look like part of the same program. There are no programs to > open and close in the right sequence. The errors codes give meaningful > descriptions. More detailed descriptions can be found be clicking on > the help button. Double clicking on an error brings you back to the > actual source of the error! All of the options are set within the one > main program. > > I have no interest in encouraging people to use Altera over Xilinx. I > want Xilinx to write software that is as good as Altera's. Since I use > both packages, I would rather see Xilinx take the challenge and > improve their tools. > > Bob ###### From: "Speedy Zero Two" Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Tue, 8 Oct 2002 21:11:06 +0100 Lines: 46 Message-ID: References: NNTP-Posting-Host: 217.134.91.161 X-Trace: news6.svr.pol.co.uk 1034107621 9701 217.134.91.161 (8 Oct 2002 20:07:01 GMT) NNTP-Posting-Date: 8 Oct 2002 20:07:01 GMT X-Complaints-To: abuse@theplanet.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6600 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6600 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!zen.net.uk!nntp.theplanet.net!inewsm1.nntp.theplanet.net!news.theplanet.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21744 Hi Bob, I use Xilinx Webpack and also use a laptop and have never had any problem with modelsim. The licence is hard drive locked but is free so is not a problem. Regarding the "bugs" you have also mentioned, I am a relative novice with programmable logic but the benefits greatly outweigh using discrete logic. I have had a reasonable response from the apps engineers at Xilinx when I have encountered problems. Having been a schematic user with Lattice and now Verilog with Xilinx, the software transition was painless. What advantages are there in using Altera hardware over Xilinx? What are the comparative costs of Silicon? In my department, the cost of the software outweighs the value of the silicon. Unfortunately, time wasted is sometimes ignored in this equation!! Regards Dave "Bob W" wrote in message news:n096qu88m768a2n6eb5u30b7n8oq1ratkr@4ax.com... > Why can't Xilinx Software be as good as Altera Software? > > > 9) I try to run the included ModelSim simulator. The ModelSim splash > screen comes up but nothing happens. The program doesn't start. The > Project Navigator shows no error. After much wasted time, I find that > the license for the simulator is tied to the IP address of the > computer it is used on. Since I was using a laptop, its IP address > depends on where it is plugged in. So I need a license for each IP > address my laptop uses. There was no error message (How about "Invalid > License!") from Navigator or ModelSim. This is poor software > integration. > > > Bob ###### Message-ID: <3DA33E16.1070308@dplanet.ch> Date: Tue, 08 Oct 2002 22:20:39 +0200 From: Rene Tschaggelar User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-us, en, de-ch MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Lines: 42 NNTP-Posting-Host: 62.167.182.46 X-Trace: 1034108515 news.sunrise.ch 702 62.167.182.46 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed.sunrise.ch!news.sunrise.ch!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21772 I'm user of Altera by chance. After having spent 3 weeks or so with MaxPlus2 and countless calls to the support line plus a multiday course I'was somewhat comfortable with their tools, MaxPlus2 and now Quartus. From a developpers point of view they're lacking the last edge of intuitivity. They could be made much simpler to operate. I was never tempted to spend another 3 weeks to become comfortable with Xilinx or Cypress. Their silicon appears to be too similar. Plus, the next time I have a look at these technologies, there is a whealth of new families and devices. To me, the ease of use is paramount. I may not have a look at that stuff for months, and then have to do a project immediately. I cannot read manuals to become comfortable again. It has to be sufficiently intuitive to be used. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net Bob W wrote: > Why can’t Xilinx Software be as good as Altera Software? > > I am an independent consultant developing FPGAs and PLDs using both > Xilinx and Altera development software. My clients usually have a > preference between Altera and Xilinx. From a hardware perspective, I > can do most designs just as well with either part. I just wish that > Xilinx could produce development tools that are as a good as those > provided by Altera. > > The Altera tools are such a pleasure to use. The tools are very well > integrated into a single Windows program. They have a consistent user > across the toolset. Any time an error occurs, a single click brings > you to the source of the error. The help files provide useful > information. < snip > ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Tue, 08 Oct 2002 17:04:53 -0400 Organization: Arius, Inc Lines: 39 Message-ID: <3DA34875.45071ABB@yahoo.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: UmFuZG9tSVYvkKWnKtQeUy1VBhFBG4STD+PSsqlK7Ihegqi/MufkEG1eC4t13krG X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 8 Oct 2002 21:04:38 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21773 Bob W wrote: > > Why can’t Xilinx Software be as good as Altera Software? Interesting discussion and I am surprised at some of the responses. I had a 6 month adventure with Altera MAX Plus and based on that I am surprised that anyone would ever use an Altera tool if they could avoid it. We were adding new features to an existing design in a 10K100A part on a board that had many units in the field. When we tried to implement a design that used 90% of the resources, the software could not handle the job. Even when we reduced the logic to 80% it would not route and meet timing. So we made lots of changes to the code to "optimize" it in ways that the P&R software could not screw up. In the end we got designs that met our timing specs, but would fail on the bench at room temperature. After tons of effort and wasted time we eventually found that the MAX Plus software was not analyzing timning correctly. We had some enable signals that fanned out widely and we suspected that this was the cause. But even after we duplicated logic to reduce fan out, we still had timing related failures on designs that were passing in static analysis. The tool just did not work. I can't say that the Xilinx tools are perfect. But when you do tough designs I find it a lot easier to see what is going on with the P&R and to find ways to deal with any problems. The pushbutton Altera approach seems to get in the way of seeing what is actually happening under the hood of your design. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Wed, 9 Oct 2002 00:55:03 +0100 Lines: 17 Message-ID: References: NNTP-Posting-Host: tile.demon.co.uk X-Trace: news.demon.co.uk 1034121703 949 158.152.50.250 (9 Oct 2002 00:01:43 GMT) X-Complaints-To: abuse@demon.net NNTP-Posting-Date: Wed, 9 Oct 2002 00:01:43 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 X-Priority: 3 X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MSMail-Priority: Normal Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!opentransit.net!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!kibo.news.demon.net!news.demon.co.uk!demon!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21794 Bob W wrote > Why can't Xilinx Software be as good as Altera Software? I am not much of an expert on Altera stuff, but the X product seems to be up the industry standard :-) My biggest Xilinx gripe is that lots of their error messages are plainly generated by 'assert' failures, and nobody has taken the trouble to scan the source for the asserts and document them. Then tech support treat you as a nutcase when you report the error... Just in case someone from X is reading this thread. ###### From: Bob W Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Message-ID: <4027qu8c300tboq2levt57s9t1sc51q2k7@4ax.com> References: X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 10 NNTP-Posting-Host: 24.91.219.183 X-Complaints-To: abuse@attbi.com X-Trace: sccrnsc02 1034127432 24.91.219.183 (Wed, 09 Oct 2002 01:37:12 GMT) NNTP-Posting-Date: Wed, 09 Oct 2002 01:37:12 GMT Organization: AT&T Broadband Date: Wed, 09 Oct 2002 01:37:12 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!144.212.100.101!newsfeed.mathworks.com!wn11feed!wn14feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!sccrnsc02.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21800 On Tue, 08 Oct 2002 18:31:38 GMT, Bob W wrote: >Why can’t Xilinx Software be as good as Altera Software? > P.S. I failed to mention that I am using (and comparing) the Altera MaxPlus II software to the Xilinx ISE. Interesting discussion going on this topic. ###### From: Bob W Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Message-ID: References: <3DA34875.45071ABB@yahoo.com> X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 39 NNTP-Posting-Host: 24.91.219.183 X-Complaints-To: abuse@attbi.com X-Trace: sccrnsc01 1034128645 24.91.219.183 (Wed, 09 Oct 2002 01:57:25 GMT) NNTP-Posting-Date: Wed, 09 Oct 2002 01:57:25 GMT Organization: AT&T Broadband Date: Wed, 09 Oct 2002 01:57:25 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!nntp2.aus1.giganews.com!nntp.giganews.com!wn12feed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi_feed3!attbi.com!sccrnsc01.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21811 On Tue, 08 Oct 2002 17:04:53 -0400, rickman wrote: >Bob W wrote: >> >> Why can’t Xilinx Software be as good as Altera Software? > >Interesting discussion and I am surprised at some of the responses. I >had a 6 month adventure with Altera MAX Plus and based on that I am >surprised that anyone would ever use an Altera tool if they could avoid >it. We were adding new features to an existing design in a 10K100A part >on a board that had many units in the field. When we tried to implement >a design that used 90% of the resources, the software could not handle >the job. Even when we reduced the logic to 80% it would not route and >meet timing. I have had a different experience with MaxPlus.I have used the MaxPlus on many 10K50 designs. I have been able to fit with high utilizations (up top 90%) . The simulator showed me results that agreed with my logic analyzer and the scope on the final product. I have a Xilinx design in a Coolrunner CPLD. It is only using 55% of the resouces. However, I find that adding or deleting a few gates causes the design to fail on routing. Then if have to try rearranging the design until I can get a fit. I took the fitted design, done in ISE 4.2 and converted it to the new ISE 5.1 and it wouldn't fit. I put the fitter into "Exhaustive fit" mode. This is supposed to try all of the combinations of fitter parameters in a sequential fashion to determine the best fit. I let it run for 2 hours and it crashed when it finally consumed all of virtual memory on a Win2K 512Mb system. There must be a memory leak through each iteration of the fitter. >I can't say that the Xilinx tools are perfect. But when you do tough >designs I find it a lot easier to see what is going on with the P&R and >to find ways to deal with any problems. The pushbutton Altera approach >seems to get in the way of seeing what is actually happening under the >hood of your design. ###### From: Bob W Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Message-ID: References: <3DA33E16.1070308@dplanet.ch> X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 13 NNTP-Posting-Host: 24.91.219.183 X-Complaints-To: abuse@attbi.com X-Trace: sccrnsc01 1034128764 24.91.219.183 (Wed, 09 Oct 2002 01:59:24 GMT) NNTP-Posting-Date: Wed, 09 Oct 2002 01:59:24 GMT Organization: AT&T Broadband Date: Wed, 09 Oct 2002 01:59:24 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!arclight.uoregon.edu!wn12feed!wn11feed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi.com!sccrnsc01.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21804 On Tue, 08 Oct 2002 22:20:39 +0200, Rene Tschaggelar wrote: >To me, the ease of use is paramount. I may not have a look at >that stuff for months, and then have to do a project >immediately. I cannot read manuals to become comfortable again. >It has to be sufficiently intuitive to be used. > >Rene I agree totally. As a consultant I might not touch the tools for a year while I am working on other projects. The Altera tools are easy to pick up again. The Xilinx tools are a pain. ###### From: Bob W Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Message-ID: References: X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 17 NNTP-Posting-Host: 24.91.219.183 X-Complaints-To: abuse@attbi.com X-Trace: sccrnsc01 1034128925 24.91.219.183 (Wed, 09 Oct 2002 02:02:05 GMT) NNTP-Posting-Date: Wed, 09 Oct 2002 02:02:05 GMT Organization: AT&T Broadband Date: Wed, 09 Oct 2002 02:02:06 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!solnet.ch!solnet.ch!newsfeed.stueberl.de!cox.net!nntp2.aus1.giganews.com!nntp.giganews.com!wn12feed!wn14feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi_feed4!attbi.com!sccrnsc01.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21808 On Wed, 9 Oct 2002 00:55:03 +0100, "Tim" wrote: be up the industry standard :-) > >My biggest Xilinx gripe is that lots of their error messages are >plainly generated by 'assert' failures, and nobody has taken >the trouble to scan the source for the asserts and document >them. Then tech support treat you as a nutcase when you report >the error... > I was at a design seminar for the Xilinx MicroBlaze embedded processor. Some asked what all of those warning messages are that are scrolling through the screen. The instructor says, "Oh those are the normal Xilinx warnings. Just ignore them". How come it generates so many warnings even when its working? ###### From: Bob W Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Message-ID: <9h37qu0icbk1cl1252jb33hpti4kra22ae@4ax.com> References: X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 41 NNTP-Posting-Host: 24.91.219.183 X-Complaints-To: abuse@attbi.com X-Trace: sccrnsc02 1034128943 24.91.219.183 (Wed, 09 Oct 2002 02:02:23 GMT) NNTP-Posting-Date: Wed, 09 Oct 2002 02:02:23 GMT Organization: AT&T Broadband Date: Wed, 09 Oct 2002 02:02:23 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!arclight.uoregon.edu!wn12feed!wn14feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!sccrnsc02.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21802 On Tue, 8 Oct 2002 19:26:48 +0000 (UTC), "Ken Mac" wrote: > >Bob, > > > >I am a Xilinx user and I haven't tried Altera software (due to the fact that >I only have Xilinx devices!). > >Why do you think Xilinx does have the major market share? > I think they make good chips (as does Altera). I think Xilinx has better marketing. Most developers have only used one toolset or the other, not both. People want to stick with the first tools they learn. >If hardware implementations on FPGA continue to start being developed from a >software perspective (Handel-C, System-C etc.), do you think Xilinx will >retain their dominance given that software developers (who will apparently >eventually being writing software that ends up directly on hardware (!) >-) ) are used to advanced, slick GUIs such as Microsoft Visual Studio etc.? >Won't they prefer Alteras software then and if designs can be done on either >Xilinx or Altera - why not choose the tool they feel most comfortable with? > I think that C level design will be the wave of the future for some types of designs. As gates become cheap and speeds get faster, it is easier to fit a C type design into silicon. Who cares how efficent it is if it meets timing? There will always be some designs that require the most efficient design and these will be harder to achieve in C. It analagous to the Assembly language versus C code argument in software. Most of the time C does the trick. Here and there Assembly is a necessity . >Or will hardware advantages still be the most important factor? > My experience is that the hardware designers are not always the ones who actually write the FPGA code. The hardware designer doesn't necessarily know (or care) how good the development tools are. ###### From: Petter Gustad Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 09 Oct 2002 12:17:20 +0200 Organization: 502 You are not allowed to talk Lines: 15 Message-ID: References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> NNTP-Posting-Host: 195.0.185.86 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: oslo-nntp.eunet.no 1034158900 15348 195.0.185.86 (9 Oct 2002 10:21:40 GMT) X-Complaints-To: abuse@KPNQwest.no NNTP-Posting-Date: 9 Oct 2002 10:21:40 GMT User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!129.240.148.23!uio.no!Norway.EU.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21798 "Mike R." writes: > As a special gift, xilinx doesn' t support the synopsys fpga compiler which > is a rocket compared to the xilinx synthesis tool. Are you saying that ngdbuild in ISE 5.x can't read EDIF files generated by Synopsys FPGA Compiler II (FC2)? I've been using FC2 with ISE 3.x and 4.x without any problems. I find it hard to believe that they don't support FC2 anymore. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter ###### Message-ID: <3da42e14$0$12760$afc38c87@news.optusnet.com.au> From: hamish@cloud.net.au Subject: Re: Why can Xilinx sw be as good as Altera's sw? Newsgroups: comp.arch.fpga References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> User-Agent: tin/1.5.14-20020917 ("Chop Suey!") (UNIX) (Linux/2.2.18 (i586)) Date: 09 Oct 2002 13:24:36 GMT Lines: 18 NNTP-Posting-Host: 211.28.158.161 X-Trace: 1034169876 12760 211.28.158.161 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news-mue1.dfn.de!newsfeed.vmunix.org!news1.optus.net.au!optus!spool01.syd.optusnet.com.au!spool.optusnet.com.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21809 Mike R. wrote: > The new ISE IDE is also worse than the old Foundation IDE. Use the command line. Simple, powerful and consistent between versions. > Furthermore a xilinx FAE told me that the fpga editor also died because of a > canceled contract with the manufacturer. This is a core tool which is a must > for fast verification of correct synthesis etc. ?? Do you mean that 5.1 has no FPGA editor? Or are you referring to Webpack? Still waiting for v5.1 to arrive. Upgrading all machines to Win2000 in anticipation. Hamish -- Hamish Moffatt VK3SB ###### From: "valentin tihomirov" Newsgroups: comp.arch.fpga References: Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Wed, 9 Oct 2002 16:29:07 +0300 Lines: 8 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 NNTP-Posting-Host: 80.235.26.218 Message-ID: <3da42f23$1_1@news.estpak.ee> X-Trace: news.estpak.ee 1034170147 80.235.26.218 (9 Oct 2002 16:29:07 +0300) X-Complaints-To: usenet@estpak.ee Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news.tele.dk!small.news.tele.dk!195.54.122.107!newsfeed1.bredband.com!bredband!uio.no!newsfeed1.funet.fi!newsfeeds.funet.fi!newsfeed.uninet.ee!news.ut.ee!news.estpak.ee!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21780 I'm not a proffesional, CPLDs are just a jobby for me. All the sw tools I downloaded from configurable logic manufacturers are awkward. I use Aldec's Active-HDL tool to desing VHDL files and then refer to these files from Xilinx WebPack. Everything is integrated perfectly including simulator and schematic editor (directly saves circuits as vhdl netlists), error messages are comprehensive. ###### Message-ID: <3DA42F90.D0EAC930@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3DA34875.45071ABB@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 71 Date: Wed, 09 Oct 2002 13:31:33 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034170293 68.15.41.165 (Wed, 09 Oct 2002 09:31:33 EDT) NNTP-Posting-Date: Wed, 09 Oct 2002 09:31:33 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21779 The 10K series routability is highly design dependent. For a heavily arithmetic design, you hit a brick wall at slightly over 50% utilization with reasonably high clock rates. It is not a function of the tool so much as the routing structure of the device. That said, max plus's hide all the nasties from the user is great if you aren't trying to push the part, but severely gets in the way when you are. I've looked at the latest Quartus, but haven't used it in a design yet. It looks like it is an improvement, but I can't say how much. As for the Xilinx SW, I have been very disappointed with the regression in the last few releases. As far as I am concerned, 3.3sp8 was the last decent software release Xilinx had, and unfortunately it doesn't handle virtexII designs well (no sync multiply support, for example). 4.x has numerous bugs that are show stoppers on big designs as well as on designs that push the performance (floorplanner is seriously broken, mapper does a lousy job packing, router no longer finds anywhere near as good a route given a floorplanned placement as earlier versions did, and so on). 4.2 also has a serious memory conflict problem under windows2K that causes it to fail on larger designs. The official "fix" for many of the problems in the 4.2 software is to 'upgrade' to Version 5.1. Unfortunately, that software introduces a whole new set of bugs, one of which increases map execution time over 10 fold for designs with large or many RPMs, despite the patch in sp1. I haven't gotten far enough through 5.1 to tell how badly it mangles the result compared with previous versions....it takes way too long to get through a carefully placed design. The point is both manufacturers are merrily chasing the big green pushbutton flow mirage, and the usability of the software for challenging designs is suffering as a result. We don't need gratuitous changes to the user interface, new bells and whistles, or even faster compile time at the expense of quality of results. What we need is solid tools that don't barf with every curve ball thrown at them. Let's get the bugs fixed in the current features before going off and adding new stuff, then when you do add new stuff don't leave the regression testing to the field. Bob W wrote: > I have had a different experience with MaxPlus.I have used the MaxPlus > on many 10K50 designs. I have been able to fit with high utilizations > (up top 90%) . The simulator showed me results that agreed with my > logic analyzer and the scope on the final product. > > I have a Xilinx design in a Coolrunner CPLD. It is only using 55% of > the resouces. However, I find that adding or deleting a few gates > causes the design to fail on routing. Then if have to try rearranging > the design until I can get a fit. I took the fitted design, done in > ISE 4.2 and converted it to the new ISE 5.1 and it wouldn't fit. I put > the fitter into "Exhaustive fit" mode. This is supposed to try all of > the combinations of fitter parameters in a sequential fashion to > determine the best fit. I let it run for 2 hours and it crashed when > it finally consumed all of virtual memory on a Win2K 512Mb system. > There must be a memory leak through each iteration of the fitter. > > >I can't say that the Xilinx tools are perfect. But when you do tough > >designs I find it a lot easier to see what is going on with the P&R and > >to find ways to deal with any problems. The pushbutton Altera approach > >seems to get in the way of seeing what is actually happening under the > >hood of your design. -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Wed, 9 Oct 2002 15:14:40 +0100 Lines: 10 Message-ID: References: <3da42f23$1_1@news.estpak.ee> NNTP-Posting-Host: tile.demon.co.uk X-Trace: news.demon.co.uk 1034177537 2935 158.152.50.250 (9 Oct 2002 15:32:17 GMT) X-Complaints-To: abuse@demon.net NNTP-Posting-Date: Wed, 9 Oct 2002 15:32:17 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 X-Priority: 3 X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MSMail-Priority: Normal Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!solnet.ch!solnet.ch!newsfeed.stueberl.de!kibo.news.demon.net!news.demon.co.uk!demon!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21791 valentin tihomirov wrote > I use Aldec's Active-HDL tool to desing VHDL files and then refer to these > files from Xilinx WebPack. It is a great shame that Aldec and Xilinx do not love each other any more. ###### Message-ID: <3DA45599.E098230E@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> <3da42e14$0$12760$afc38c87@news.optusnet.com.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 40 Date: Wed, 09 Oct 2002 16:13:50 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034180030 68.15.41.165 (Wed, 09 Oct 2002 12:13:50 EDT) NNTP-Posting-Date: Wed, 09 Oct 2002 12:13:50 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21775 Hamish, be careful with that. 4.2 has a bug where designs with large ncds gets a memory conflict under win2K. We made that mistake, and had to run under NT4 in order to continue on with the design. That 2v6000 design gets through map in an hour and 40 minutes on an old 800 MHz P3 with 1GB (paging like crazy) under 4.2i on NT, won't run on 4.2i under win2K, and takes over 25 hrs under 5.1 running on a 2GHz K7 with 2GB memory . hamish@cloud.net.au wrote: > Mike R. wrote: > > The new ISE IDE is also worse than the old Foundation IDE. > > Use the command line. Simple, powerful and consistent between versions. > > > Furthermore a xilinx FAE told me that the fpga editor also died because of a > > canceled contract with the manufacturer. This is a core tool which is a must > > for fast verification of correct synthesis etc. > > ?? Do you mean that 5.1 has no FPGA editor? Or are you referring to > Webpack? > > Still waiting for v5.1 to arrive. Upgrading all machines to Win2000 in > anticipation. > > Hamish > -- > Hamish Moffatt VK3SB -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: ccon67@netscape.net (Marlboro) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 9 Oct 2002 09:31:46 -0700 Organization: http://groups.google.com/ Lines: 23 Message-ID: References: <4027qu8c300tboq2levt57s9t1sc51q2k7@4ax.com> NNTP-Posting-Host: 66.88.186.242 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1034181107 23111 127.0.0.1 (9 Oct 2002 16:31:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 9 Oct 2002 16:31:47 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21803 Bob W wrote in message news:<4027qu8c300tboq2levt57s9t1sc51q2k7@4ax.com>... > On Tue, 08 Oct 2002 18:31:38 GMT, Bob W > wrote: > > >Why can't Xilinx Software be as good as Altera Software? > > > P.S. I failed to mention that I am using (and comparing) the Altera > MaxPlus II software to the Xilinx ISE. > > Interesting discussion going on this topic. Howdy all, Frankly Im not Altera's fan, may be I'm bias, but this is my opinion: 1) Neither Altera or Xilinx SW is perfect. Both have some week points 2) Do not blame only on FPGA tools when tons of ugly thing still in your Windows 4) A normal sword in a good hand is always dangerous 5) Live and learn 6) No free lunch in USA 7) Expensive lunch is not always delicious 8) Let your wife choose her own flavor 9) Have a nice day... :) ###### From: "MikeJ" Newsgroups: comp.arch.fpga References: <3da42f23$1_1@news.estpak.ee> Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 01:16:59 +0100 Lines: 36 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 1430212497ee12843ad230302260e60127133313835e224b313e13f53da4c33f NNTP-Posting-Date: Thu, 10 Oct 2002 01:01:03 +0100 Message-ID: <1034208063.92802.0@dyke.uk.clara.net> Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!psinet-eu-nl!news-x2.support.nl!newspeer.clara.net!news.clara.net!dyke.uk.clara.net Xref: chonsp.franklin.ch comp.arch.fpga:21837 On a serious note at a professional (!) designer. I used maxplus2 extensively in the past, but was forced to move onto devices Xilinx when they introduced the 4000xl chips as I really needed to use the distributed rams. (However, since Virtex have never look back) This forced a move from AHDL to VHDL, and lots of pain. I had to move from the nice 'cosy' gui to a set of tools that were not so polished. However, whereas simulating a single chip was a pain in maxplus, I now simulate whole cards, indeed systems. I can take data, for example a picture, run it through the simulator using complex test benches and produce a real output (perhaps another image). My point is that I spend most of my time in simulation. When I come to build a chip I run (under win2k) a batch file that runs the sythesis tool, then the xilinx place and route tools. I am not really interested in the xilinx sw - they produce me a bit file for the device, a timing report file telling me how much extra time I have to spend over the weekend meeting constraints, and perhaps a list of errors. The point is I type 'build_chip' (perhaps on a seperate machine) and carry on with the simulation / coding. Xilinx tools are not interesting, they don't need to be. Many designers never even run up the gui. The simulator is where the action is. Cheers, MikeJ b.t.w. never, ever, ever phone xilinx tech support. just my gripe for the day. ###### Message-ID: <3DA4DFF0.EFDF32D4@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.10.117 Lines: 30 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Thu, 10 Oct 2002 12:03:28 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034215065 203.134.67.67 (Wed, 09 Oct 2002 21:57:45 EDT) NNTP-Posting-Date: Wed, 09 Oct 2002 21:57:45 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed-east.nntpserver.com!nntpserver.com!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21835 MikeJ wrote: > > On a serious note at a professional (!) designer. > > I used maxplus2 extensively in the past, but was forced to move onto devices > Xilinx when they introduced the 4000xl chips as I really needed to use the > distributed rams. > (However, since Virtex have never look back) > > This forced a move from AHDL to VHDL, and lots of pain. > I had to move from the nice 'cosy' gui to a set of tools that were not so > polished. > > However, whereas simulating a single chip was a pain in maxplus, I now > simulate whole cards, indeed systems. > I can take data, for example a picture, run it through the simulator using > complex test benches and produce a real output (perhaps another image). > > My point is that I spend most of my time in simulation. When I come to build > a chip I run (under win2k) a batch file that runs the sythesis tool, then > the xilinx place and route tools. I am not really interested in the xilinx > sw - they produce me a bit file for the device, a timing report file telling > me how much extra time I have to spend over the weekend meeting constraints, > and perhaps a list of errors. The point is I type 'build_chip' (perhaps on a > seperate machine) and carry on with the simulation / coding. > > Xilinx tools are not interesting, they don't need to be. Many designers > never even run up the gui. The simulator is where the action is. How do you floor-plan without a gui? ###### Message-ID: <3DA4F385.BC767D4B@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 20 Date: Thu, 10 Oct 2002 03:27:37 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034220457 68.15.41.165 (Wed, 09 Oct 2002 23:27:37 EDT) NNTP-Posting-Date: Wed, 09 Oct 2002 23:27:37 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21824 Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How do you floorplan with the broken floorplanner GUI in 4.2i? Russell wrote: > > How do you floor-plan without a gui? -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3DA501C5.DE008F33@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.10.117 Lines: 18 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Thu, 10 Oct 2002 14:27:49 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034223728 203.134.67.67 (Thu, 10 Oct 2002 00:22:08 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 00:22:08 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!eusc.inter.net!news.tele.dk!small.news.tele.dk!24.226.1.12!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21829 I gave up on doing any fpga design after wasting weeks on discovering how broken floor planning with RPMs in 4.2i was, and there's no way i can do without manual floorplanning. Altera had even less options and the devices had no SRL16 equivalent. If 5.1i is no good, i'll start investigating the cyclone devices. It would be good having a tool that runs on linux too (wonder if i still need that leonardo with the crappy gui bugs?). I was hoping 5.1i would fix everything, but i haven't tried it yet. Ray Andraka wrote: > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > do you floorplan with the broken floorplanner GUI in 4.2i? > > Russell wrote: > > > > > How do you floor-plan without a gui? ###### Message-ID: <3DA504D9.D1CCB4A0@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 46 Date: Thu, 10 Oct 2002 04:41:31 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034224891 68.15.41.165 (Thu, 10 Oct 2002 00:41:31 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 00:41:31 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21823 Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my previous post. I haven't tried the floorplanner in 5.1 yet. 4.2i's floorplanner has a workaround if your design will go through PAR without a floorplan, you can then go into the floorplanner do a constrain from placement on your RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it does no good if your design won't make it through PAR without a floorplan, and it doesn't leave much room to move things around if youve got a dense device. I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds me too much of the days before the introduction of the floorplanner in XACT. Russell wrote: > I gave up on doing any fpga design after wasting weeks on discovering > how broken floor planning with RPMs in 4.2i was, and there's no way i > can do without manual floorplanning. Altera had even less options and > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start > investigating the cyclone devices. It would be good having a tool > that runs on linux too (wonder if i still need that leonardo with > the crappy gui bugs?). I was hoping 5.1i would fix everything, but > i haven't tried it yet. > > Ray Andraka wrote: > > > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > > do you floorplan with the broken floorplanner GUI in 4.2i? > > > > Russell wrote: > > > > > > > > How do you floor-plan without a gui? -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3DA5091E.84202951@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 71 Date: Thu, 10 Oct 2002 04:59:45 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034225985 68.15.41.165 (Thu, 10 Oct 2002 00:59:45 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 00:59:45 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21819 Some qualification to my rants here: The Xilinx silicon is still good stuff, very capable. I have some beefs with the software and its spiralling quality. The fact of the matter though is that many users will not encounter the problems I have with the software, simply because we typically are pushing the corners of the tools where most users never stray. For example, if you are not floorplanning, you won't hit about 90% of the show stopper bugs we've run into. My frustration is that for these designs where we are pushing the limits, the tools have steadily lost capability from version to version, to the point the 4.2 has enough problems that it is leaving us very little options for work arounds on a couple of designs. Ray Andraka wrote: > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my > previous post. I haven't tried the floorplanner in 5.1 yet. > > 4.2i's floorplanner has a workaround if your design will go through PAR without a > floorplan, you can then go into the floorplanner do a constrain from placement on your > RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it > does no good if your design won't make it through PAR without a floorplan, and it > doesn't leave much room to move things around if youve got a dense device. > > I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of > floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds > me too much of the days before the introduction of the floorplanner in XACT. > > Russell wrote: > > > I gave up on doing any fpga design after wasting weeks on discovering > > how broken floor planning with RPMs in 4.2i was, and there's no way i > > can do without manual floorplanning. Altera had even less options and > > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start > > investigating the cyclone devices. It would be good having a tool > > that runs on linux too (wonder if i still need that leonardo with > > the crappy gui bugs?). I was hoping 5.1i would fix everything, but > > i haven't tried it yet. > > > > Ray Andraka wrote: > > > > > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > > > do you floorplan with the broken floorplanner GUI in 4.2i? > > > > > > Russell wrote: > > > > > > > > > > > How do you floor-plan without a gui? > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3DA50A3C.9E1FC1D@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.10.117 Lines: 43 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Thu, 10 Oct 2002 15:03:56 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034225895 203.134.67.67 (Thu, 10 Oct 2002 00:58:15 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 00:58:15 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!diablo.netcom.net.uk!netcom.net.uk!colt.net!news.maxwell.syr.edu!newsfeed-east.nntpserver.com!nntpserver.com!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21828 My designs just use cascades of fairly repetitive filter and delay blocks which is well suited to macro methods, and they're controlled with some state-machine random logic. It should fit in the larger spartan devices. I heard that 4.2i fpga editor had bugs where vcc-gnd shorts happened. Is the 5.1i fpga editor much better? Are hard macros relatively bug-free to generate and use in 5.1i? Ray Andraka wrote: > > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my > previous post. I haven't tried the floorplanner in 5.1 yet. > > 4.2i's floorplanner has a workaround if your design will go through PAR without a > floorplan, you can then go into the floorplanner do a constrain from placement on your > RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it > does no good if your design won't make it through PAR without a floorplan, and it > doesn't leave much room to move things around if youve got a dense device. > > I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of > floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds > me too much of the days before the introduction of the floorplanner in XACT. > > Russell wrote: > > > I gave up on doing any fpga design after wasting weeks on discovering > > how broken floor planning with RPMs in 4.2i was, and there's no way i > > can do without manual floorplanning. Altera had even less options and > > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start > > investigating the cyclone devices. It would be good having a tool > > that runs on linux too (wonder if i still need that leonardo with > > the crappy gui bugs?). I was hoping 5.1i would fix everything, but > > i haven't tried it yet. > > > > Ray Andraka wrote: > > > > > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > > > do you floorplan with the broken floorplanner GUI in 4.2i? > > > > > > Russell wrote: > > > > > > > > > > > How do you floor-plan without a gui? ###### Message-ID: <3DA50F51.39CD1D0C@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.10.117 Lines: 26 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Thu, 10 Oct 2002 15:25:37 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034227199 203.134.67.67 (Thu, 10 Oct 2002 01:19:59 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 01:19:59 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed-east.nntpserver.com!nntpserver.com!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21830 I think the fpga world would benefit greatly if the fpga vendors would just write an api library for each device to control all the low level logic primitives, and let open-source on linux take care of building state of the art routing and layout tools and decent hdl languages and compilers. It would improve the industry no end. How excellent would it be to be able to locate and fix a router bug your self, or get it fixed in less than a week? Ray Andraka wrote: > > Some qualification to my rants here: > > The Xilinx silicon is still good stuff, very capable. I have some beefs with the software > and its spiralling quality. The fact of the matter though is that many users will not > encounter the problems I have with the software, simply because we typically are pushing > the corners of the tools where most users never stray. For example, if you are not > floorplanning, you won't hit about 90% of the show stopper bugs we've run into. My > frustration is that for these designs where we are pushing the limits, the tools have > steadily lost capability from version to version, to the point the 4.2 has enough problems > that it is leaving us very little options for work arounds on a couple of designs. > > Ray Andraka wrote: > > > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my > > previous post. I haven't tried the floorplanner in 5.1 yet... ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 02:24:17 -0400 Organization: Arius, Inc Lines: 40 Message-ID: <3DA51D11.D69E5E9C@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVabhOSupAHGkzfUZeb1DuE6GHbUb4gUcYFOUNafwPEgi4ec9oKKVim3 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 10 Oct 2002 06:24:08 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.abs.net!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21815 Russell wrote: > > I think the fpga world would benefit greatly if the fpga vendors > would just write an api library for each device to control all > the low level logic primitives, and let open-source on linux > take care of building state of the art routing and layout tools > and decent hdl languages and compilers. It would improve the > industry no end. How excellent would it be to be able to locate > and fix a router bug your self, or get it fixed in less than > a week? That may sound great in theory, but the software is vitally important to an FPGA vendor. An FPGA vendor can't depend on outside factors to control their destiny. An FPGA company can literally be made or broken on the tools. So you will never see them abandon their in house tools for open source tools. In fact, because the user community is so small, they can't afford to develop the tools without the finance support of the user base. If even just 50% of them go to open source tools the FPGA vendor will lose tons of money. They can't raise the price of the silcon to make up for it since the price of silicon is set by competitive pressures. It would be a very tough sell to show that it would provide a superior market position to have open source tools. Of course when I say they "can't afford" to self fund the tools, that is a relative term. The point is that the tools cost a lot of money to maintain and update. The economics are not there to allow open source tools to compete. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3DA51F9B.782B@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 27 Date: Thu, 10 Oct 2002 19:35:07 +1300 NNTP-Posting-Host: 203.79.98.18 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1034231753 203.79.98.18 (Thu, 10 Oct 2002 19:35:53 NZDT) NNTP-Posting-Date: Thu, 10 Oct 2002 19:35:53 NZDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.media.kyoto-u.ac.jp!news-out.spamkiller.net!propagator2-maxim!news-in.spamkiller.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21836 Ray Andraka wrote: > > Some qualification to my rants here: > > The Xilinx silicon is still good stuff, very capable. I have some beefs with the software > and its spiralling quality. The fact of the matter though is that many users will not > encounter the problems I have with the software, simply because we typically are pushing > the corners of the tools where most users never stray. For example, if you are not > floorplanning, you won't hit about 90% of the show stopper bugs we've run into. My > frustration is that for these designs where we are pushing the limits, the tools have > steadily lost capability from version to version, to the point the 4.2 has enough problems > that it is leaving us very little options for work arounds on a couple of designs. I think more users may be affected than you realise. The cynical amongst us could say they have a vested interest in NOT fixing the software, if the effect is to simply bump users up a FPGA size. We routinely push CPLD right to the corners, and the critical metric for tools here, is quality of reports, esp the fitters. ( and the ability to control / floor plan ) Tools where you cannot guide, nor analyse the results, are not tools at all. -jg ###### Message-ID: <3DA54C95.FFE0D5BA@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.118.170 Lines: 40 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Thu, 10 Oct 2002 19:47:01 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034242879 203.134.67.67 (Thu, 10 Oct 2002 05:41:19 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 05:41:19 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21834 rickman wrote: > > Russell wrote: > > > > I think the fpga world would benefit greatly if the fpga vendors > > would just write an api library for each device to control all > > the low level logic primitives, and let open-source on linux > > take care of building state of the art routing and layout tools > > and decent hdl languages and compilers. It would improve the > > industry no end. How excellent would it be to be able to locate > > and fix a router bug your self, or get it fixed in less than > > a week? > > That may sound great in theory, but the software is vitally important to > an FPGA vendor. An FPGA vendor can't depend on outside factors to > control their destiny. An FPGA company can literally be made or broken > on the tools. So you will never see them abandon their in house tools > for open source tools. In fact, because the user community is so small, > they can't afford to develop the tools without the finance support of > the user base. If even just 50% of them go to open source tools the > FPGA vendor will lose tons of money. They can't raise the price of the > silcon to make up for it since the price of silicon is set by > competitive pressures. It would be a very tough sell to show that it > would provide a superior market position to have open source tools. > > Of course when I say they "can't afford" to self fund the tools, that is > a relative term. The point is that the tools cost a lot of money to > maintain and update. The economics are not there to allow open source > tools to compete. All the fpga vendors need to do is make a publicly available API for the devices, and keep doing whatever tools they have now. Private and public projects will start up for various reasons such as profit, academic purposes, or just to improve on what's available. Eventually the GPL tools will be better than those done by nine-to-fivers that couldn't give a stuff about fixing bugs. The fpga vendors can then either support the GPL tools and keep frozen releases for safety, or just keep doing their own tools but get useful ideas from the GPL tools. There'd be less problems for everyone if there was a choice of tools, and savings for the fpga vendors. ###### Message-ID: <3DA577F6.5B85EEA6@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA50A3C.9E1FC1D@iprimus.com.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 66 Date: Thu, 10 Oct 2002 12:52:44 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034254364 68.15.41.165 (Thu, 10 Oct 2002 08:52:44 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 08:52:44 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!central.cox.net!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21826 I try to avoid doing hard macros, rather I stick to RPMs because they work better with the conventional tool flow. In the past, the router has done a pretty good job in most cases if the placement was good, so I rarely found the need to do hard macros other than as a work-around. 4.2i does not do as good a job of finding a good routing solution given a good placement, which means that there is more to gain from doing hard macros. I haven't had a chance to evaluate 5.1's routing yet, but I suspect the finish sooner mentality has only made the routing less optimal. Russell wrote: > My designs just use cascades of fairly repetitive filter and delay blocks > which is well suited to macro methods, and they're controlled with some > state-machine random logic. It should fit in the larger spartan devices. > > I heard that 4.2i fpga editor had bugs where vcc-gnd shorts happened. > Is the 5.1i fpga editor much better? Are hard macros relatively bug-free > to generate and use in 5.1i? > > Ray Andraka wrote: > > > > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my > > previous post. I haven't tried the floorplanner in 5.1 yet. > > > > 4.2i's floorplanner has a workaround if your design will go through PAR without a > > floorplan, you can then go into the floorplanner do a constrain from placement on your > > RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it > > does no good if your design won't make it through PAR without a floorplan, and it > > doesn't leave much room to move things around if youve got a dense device. > > > > I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of > > floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds > > me too much of the days before the introduction of the floorplanner in XACT. > > > > Russell wrote: > > > > > I gave up on doing any fpga design after wasting weeks on discovering > > > how broken floor planning with RPMs in 4.2i was, and there's no way i > > > can do without manual floorplanning. Altera had even less options and > > > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start > > > investigating the cyclone devices. It would be good having a tool > > > that runs on linux too (wonder if i still need that leonardo with > > > the crappy gui bugs?). I was hoping 5.1i would fix everything, but > > > i haven't tried it yet. > > > > > > Ray Andraka wrote: > > > > > > > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > > > > do you floorplan with the broken floorplanner GUI in 4.2i? > > > > > > > > Russell wrote: > > > > > > > > > > > > > > How do you floor-plan without a gui? -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3DA57BF6.9E2352BB@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA50A3C.9E1FC1D@iprimus.com.au> <3DA577F6.5B85EEA6@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 92 Date: Thu, 10 Oct 2002 13:09:47 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034255387 68.15.41.165 (Thu, 10 Oct 2002 09:09:47 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 09:09:47 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21822 some clarification: The hard macros don't exactly guarantee much more than an RPM does, as they also do not lock down the routing. What it does do is lock down the pins of the LUTs, which will serve to bias the router to use similar routing. However, if you have additional routes through the area, it can make routing harder and can actually degrade the timing when compared to a regular RPM. We used to be able to assign the pins to the lut back in the XACT days, but that capability dissappeared with the M.1 tools. You can still trick it into using specific pins with some limitations by replacing the LUTs with SRL16's and holding the WE input inactive for those cases where you want to lock down LUT pins. Again, I try to avoid this low level, especially since it obfuscates the code and can hamstring the router. Ray Andraka wrote: > I try to avoid doing hard macros, rather I stick to RPMs because they work better with the > conventional tool flow. In the past, the router has done a pretty good job in most cases if > the placement was good, so I rarely found the need to do hard macros other than as a > work-around. 4.2i does not do as good a job of finding a good routing solution given a good > placement, which means that there is more to gain from doing hard macros. I haven't had a > chance to evaluate 5.1's routing yet, but I suspect the finish sooner mentality has only > made the routing less optimal. > > Russell wrote: > > > My designs just use cascades of fairly repetitive filter and delay blocks > > which is well suited to macro methods, and they're controlled with some > > state-machine random logic. It should fit in the larger spartan devices. > > > > I heard that 4.2i fpga editor had bugs where vcc-gnd shorts happened. > > Is the 5.1i fpga editor much better? Are hard macros relatively bug-free > > to generate and use in 5.1i? > > > > Ray Andraka wrote: > > > > > > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my > > > previous post. I haven't tried the floorplanner in 5.1 yet. > > > > > > 4.2i's floorplanner has a workaround if your design will go through PAR without a > > > floorplan, you can then go into the floorplanner do a constrain from placement on your > > > RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it > > > does no good if your design won't make it through PAR without a floorplan, and it > > > doesn't leave much room to move things around if youve got a dense device. > > > > > > I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of > > > floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds > > > me too much of the days before the introduction of the floorplanner in XACT. > > > > > > Russell wrote: > > > > > > > I gave up on doing any fpga design after wasting weeks on discovering > > > > how broken floor planning with RPMs in 4.2i was, and there's no way i > > > > can do without manual floorplanning. Altera had even less options and > > > > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start > > > > investigating the cyclone devices. It would be good having a tool > > > > that runs on linux too (wonder if i still need that leonardo with > > > > the crappy gui bugs?). I was hoping 5.1i would fix everything, but > > > > i haven't tried it yet. > > > > > > > > Ray Andraka wrote: > > > > > > > > > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > > > > > do you floorplan with the broken floorplanner GUI in 4.2i? > > > > > > > > > > Russell wrote: > > > > > > > > > > > > > > > > > How do you floor-plan without a gui? > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: mrand@my-deja.com (Marc Randolph) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 10 Oct 2002 08:37:57 -0700 Organization: http://groups.google.com/ Lines: 35 Message-ID: <15881dde.0210100737.1320539@posting.google.com> References: NNTP-Posting-Host: 65.192.92.132 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1034264278 29329 127.0.0.1 (10 Oct 2002 15:37:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 10 Oct 2002 15:37:58 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21853 Bob W wrote in message news:... > On Wed, 9 Oct 2002 00:55:03 +0100, "Tim" > wrote: > > be up the industry standard :-) > > > >My biggest Xilinx gripe is that lots of their error messages are > >plainly generated by 'assert' failures, and nobody has taken > >the trouble to scan the source for the asserts and document > >them. Then tech support treat you as a nutcase when you report > >the error... > > > > I was at a design seminar for the Xilinx MicroBlaze embedded > processor. Some asked what all of those warning messages are that are > scrolling through the screen. The instructor says, "Oh those are the > normal Xilinx warnings. Just ignore them". How come it generates so > many warnings even when its working? I asked the same thing of our FAE. He said that some of the warnings are things that Xilinx may eventually turn into error messages - especially case sensitivity disagreements between the ucf and edf. It's really too bad they don't provide you a way to enable/disable the minor warnings... that would actually make it usable. As it is right now, all warnings get ignored. As for Xilinx vs. Altera SW, the Xilinx software appears to be slightly more powerful (in terms of most features), but Altera's is much nicer to use. But as nice as Altera's software is, and as affordable as the 20KE parts are, it doesn't seem to be able to handle (successfully map and meet timing) one of our XC2V3000 designs, so we have no choice but to stick with Xilinx. Marc ###### From: Bret Wade Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 09:50:57 -0600 Organization: Xilinx, Inc. Lines: 114 Message-ID: <3DA5A1E1.8183DE29@xilinx.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA50A3C.9E1FC1D@iprimus.com.au> <3DA577F6.5B85EEA6@andraka.com> <3DA57BF6.9E2352BB@andraka.com> NNTP-Posting-Host: 149.199.172.86 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.74 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!psinet-eu-nl!syros.belnet.be!news.belnet.be!newsfeed.media.kyoto-u.ac.jp!spring.edu.tw!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!xbc-news.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21818 Hello Ray, Hard macros (.nmc) can indeed contain routing information, but this is functionality is not often used. Here's a brief description of hard macro use cases: 1. Unplaced and unrouted hard macros - The macro is used to define only the component configuration and PAR is free to place and route as needed. 2. Placed and unrouted hard macros - The macro defines the component configuration and relative placement of the components. The router is free to route the macro as needed. 3. Placed and routed hard macros - The macro defines the component configuration, relative placement and routing of the macro. The problem with hard macros is that they exist only as a black box in the logical design so they complicate timing analysis and simulation. A combination of RPMs with Directed Routing contains the same functionality without this limitation. For that reason, hard macros tend to be used only as work arounds to force implementations that map/par can't handle. Regards, Bret Ray Andraka wrote: > some clarification: > > The hard macros don't exactly guarantee much more than an RPM does, as they also do not lock > down the routing. What it does do is lock down the pins of the LUTs, which will serve to bias > the router to use similar routing. However, if you have additional routes through the area, it > can make routing harder and can actually degrade the timing when compared to a regular RPM. We > used to be able to assign the pins to the lut back in the XACT days, but that capability > dissappeared with the M.1 tools. You can still trick it into using specific pins with some > limitations by replacing the LUTs with SRL16's and holding the WE input inactive for those cases > where you want to lock down LUT pins. Again, I try to avoid this low level, especially since it > obfuscates the code and can hamstring the router. > > Ray Andraka wrote: > > > I try to avoid doing hard macros, rather I stick to RPMs because they work better with the > > conventional tool flow. In the past, the router has done a pretty good job in most cases if > > the placement was good, so I rarely found the need to do hard macros other than as a > > work-around. 4.2i does not do as good a job of finding a good routing solution given a good > > placement, which means that there is more to gain from doing hard macros. I haven't had a > > chance to evaluate 5.1's routing yet, but I suspect the finish sooner mentality has only > > made the routing less optimal. > > > > Russell wrote: > > > > > My designs just use cascades of fairly repetitive filter and delay blocks > > > which is well suited to macro methods, and they're controlled with some > > > state-machine random logic. It should fit in the larger spartan devices. > > > > > > I heard that 4.2i fpga editor had bugs where vcc-gnd shorts happened. > > > Is the 5.1i fpga editor much better? Are hard macros relatively bug-free > > > to generate and use in 5.1i? > > > > > > Ray Andraka wrote: > > > > > > > > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my > > > > previous post. I haven't tried the floorplanner in 5.1 yet. > > > > > > > > 4.2i's floorplanner has a workaround if your design will go through PAR without a > > > > floorplan, you can then go into the floorplanner do a constrain from placement on your > > > > RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it > > > > does no good if your design won't make it through PAR without a floorplan, and it > > > > doesn't leave much room to move things around if youve got a dense device. > > > > > > > > I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of > > > > floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds > > > > me too much of the days before the introduction of the floorplanner in XACT. > > > > > > > > Russell wrote: > > > > > > > > > I gave up on doing any fpga design after wasting weeks on discovering > > > > > how broken floor planning with RPMs in 4.2i was, and there's no way i > > > > > can do without manual floorplanning. Altera had even less options and > > > > > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start > > > > > investigating the cyclone devices. It would be good having a tool > > > > > that runs on linux too (wonder if i still need that leonardo with > > > > > the crappy gui bugs?). I was hoping 5.1i would fix everything, but > > > > > i haven't tried it yet. > > > > > > > > > > Ray Andraka wrote: > > > > > > > > > > > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > > > > > > do you floorplan with the broken floorplanner GUI in 4.2i? > > > > > > > > > > > > Russell wrote: > > > > > > > > > > > > > > > > > > > > How do you floor-plan without a gui? > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 ###### Message-ID: <3DA5B1A7.46207315@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA50A3C.9E1FC1D@iprimus.com.au> <3DA577F6.5B85EEA6@andraka.com> <3DA57BF6.9E2352BB@andraka.com> <3DA5A1E1.8183DE29@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 135 Date: Thu, 10 Oct 2002 16:58:52 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034269132 68.15.41.165 (Thu, 10 Oct 2002 12:58:52 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 12:58:52 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.wirehub.nl!news-hub.cableinet.net!blueyonder!nntp2.aus1.giganews.com!nntp.giganews.com!central.cox.net!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21820 Bret, I am aware of the routing with hard macros, but I thought that routed hard macros got pinned to a particular location. Anyway, the fact that it is outside of the normal flow makes design verification a bear to deal with, as you point out. Is there some documentation on this 'directed routing' for RPMs? I wasn't aware of any way of directing the routing other than with the FPGA editor-> hard macro route. Bret Wade wrote: > Hello Ray, > > Hard macros (.nmc) can indeed contain routing information, but this is functionality is not often > used. Here's a brief description of hard macro use cases: > > 1. Unplaced and unrouted hard macros - The macro is used to define only the component configuration > and PAR is free to place and route as needed. > > 2. Placed and unrouted hard macros - The macro defines the component configuration and relative > placement of the components. The router is free to route the macro as needed. > > 3. Placed and routed hard macros - The macro defines the component configuration, relative placement > and routing of the macro. > > The problem with hard macros is that they exist only as a black box in the logical design so they > complicate timing analysis and simulation. A combination of RPMs with Directed Routing contains the > same functionality without this limitation. For that reason, hard macros tend to be used only as > work arounds to force implementations that map/par can't handle. > > Regards, > Bret > > Ray Andraka wrote: > > > some clarification: > > > > The hard macros don't exactly guarantee much more than an RPM does, as they also do not lock > > down the routing. What it does do is lock down the pins of the LUTs, which will serve to bias > > the router to use similar routing. However, if you have additional routes through the area, it > > can make routing harder and can actually degrade the timing when compared to a regular RPM. We > > used to be able to assign the pins to the lut back in the XACT days, but that capability > > dissappeared with the M.1 tools. You can still trick it into using specific pins with some > > limitations by replacing the LUTs with SRL16's and holding the WE input inactive for those cases > > where you want to lock down LUT pins. Again, I try to avoid this low level, especially since it > > obfuscates the code and can hamstring the router. > > > > Ray Andraka wrote: > > > > > I try to avoid doing hard macros, rather I stick to RPMs because they work better with the > > > conventional tool flow. In the past, the router has done a pretty good job in most cases if > > > the placement was good, so I rarely found the need to do hard macros other than as a > > > work-around. 4.2i does not do as good a job of finding a good routing solution given a good > > > placement, which means that there is more to gain from doing hard macros. I haven't had a > > > chance to evaluate 5.1's routing yet, but I suspect the finish sooner mentality has only > > > made the routing less optimal. > > > > > > Russell wrote: > > > > > > > My designs just use cascades of fairly repetitive filter and delay blocks > > > > which is well suited to macro methods, and they're controlled with some > > > > state-machine random logic. It should fit in the larger spartan devices. > > > > > > > > I heard that 4.2i fpga editor had bugs where vcc-gnd shorts happened. > > > > Is the 5.1i fpga editor much better? Are hard macros relatively bug-free > > > > to generate and use in 5.1i? > > > > > > > > Ray Andraka wrote: > > > > > > > > > > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. See my > > > > > previous post. I haven't tried the floorplanner in 5.1 yet. > > > > > > > > > > 4.2i's floorplanner has a workaround if your design will go through PAR without a > > > > > floorplan, you can then go into the floorplanner do a constrain from placement on your > > > > > RPMs, then unbind, then rebind each RPM, then you can move them around. Of course, it > > > > > does no good if your design won't make it through PAR without a floorplan, and it > > > > > doesn't leave much room to move things around if youve got a dense device. > > > > > > > > > > I've more or less had to use RLOC_ORIGIN constraints in the UCF to take care of > > > > > floorplanning RPMs under 4.2. I don't like it, but at least it is possible (reminds > > > > > me too much of the days before the introduction of the floorplanner in XACT. > > > > > > > > > > Russell wrote: > > > > > > > > > > > I gave up on doing any fpga design after wasting weeks on discovering > > > > > > how broken floor planning with RPMs in 4.2i was, and there's no way i > > > > > > can do without manual floorplanning. Altera had even less options and > > > > > > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start > > > > > > investigating the cyclone devices. It would be good having a tool > > > > > > that runs on linux too (wonder if i still need that leonardo with > > > > > > the crappy gui bugs?). I was hoping 5.1i would fix everything, but > > > > > > i haven't tried it yet. > > > > > > > > > > > > Ray Andraka wrote: > > > > > > > > > > > > > > Same way we did before there was a floorplanner GUI: RLOCs and graph paper. How > > > > > > > do you floorplan with the broken floorplanner GUI in 4.2i? > > > > > > > > > > > > > > Russell wrote: > > > > > > > > > > > > > > > > > > > > > > > How do you floor-plan without a gui? > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3DA5B364.F95F9D0C@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 56 Date: Thu, 10 Oct 2002 17:06:17 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034269577 68.15.41.165 (Thu, 10 Oct 2002 13:06:17 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 13:06:17 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!proxad.net!easynet-quince!easynet.net!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21825 Falk, I'd be happy to stick with the 'old' tools, unfortunately we get pulled along by both the customer and Xilinx. I still use 3.3sp8 for virtex and virtexE designs because it works. In order to do so,however, I had to upgrade to the timing files for virtexE that were released after 4.1 was. Xilinx doesn't see fit to make the timing for 3.3sp8 available on the website, so you need to beg your FAE for them (this, as far as I am concerned is a sin, especially since those timing files are less optimistic than previous ones which means designs done with the old files may not meet timing in real life...Xilinx, you listening? The latest speed files should be made readily available for 3.3 at a minimum because of the functional problems with later software releases). We've hit some bugs in 4.2 that are show stoppers, and which are apparently going to force us into 5.1 for the virtexII (3.3 doesn't support several virtexII features, so you are forced to use 4.x or later). Of course 5.1 introduces new bugs, so we are in limp mode until we get a suitable combination of tools working. Falk Brunner wrote: > "Russell" schrieb im Newsbeitrag > news:3DA501C5.DE008F33@iprimus.com.au... > > I gave up on doing any fpga design after wasting weeks on discovering > > how broken floor planning with RPMs in 4.2i was, and there's no way i > > can do without manual floorplanning. Altera had even less options and > > the devices had no SRL16 equivalent. If 5.1i is no good, i'll start > > investigating the cyclone devices. It would be good having a tool > > that runs on linux too (wonder if i still need that leonardo with > > the crappy gui bugs?). I was hoping 5.1i would fix everything, but > > i haven't tried it yet. > > I think in many cases it is better to stay with the "old" software and > handle the KNOWN bugs, instead of switching to new software with UNKOWN > bugs. Yes, we all are unpaid BETA testers, but if you can avoid this, you > better should do so. How many people REALLY need the new features (what are > they?) of 5.1?? > Up to now, I dont. So I will not change, especially not while a project is > running. > > -- > MfG > Falk -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: Mike Treseler Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 11:04:56 -0700 Organization: Fluke Networks Message-ID: <3DA5C148.4010502@flukenetworks.com> User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:0.9.4.1) Gecko/20020508 Netscape6/6.2.3 X-Accept-Language: en-us MIME-Version: 1.0 References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@supernews.com Lines: 15 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!solnet.ch!solnet.ch!newsfeed.freenet.de!newsfeed.news2me.com!newsfeed-west.nntpserver.com!hub1.meganetnews.com!nntpserver.com!telocity-west!TELOCITY!sn-xit-03!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21841 Falk Brunner wrote: >>Xilinx tools are not interesting, they don't need to be. Many designers >>never even run up the gui. The simulator is where the action is. > From which planet are you from? I think I live nearby. Time is more limited than gates. 90% sim, 5% synth, 5% p+r -- Mike Treseler ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 15:40:04 -0400 Organization: Arius, Inc Lines: 57 Message-ID: <3DA5D794.F75DB6F9@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVaNCnsbU5muZomR0mpIQQP5bM0WkHsAez7lyUn9i6f3FddMYNAUM7JJ X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 10 Oct 2002 19:39:53 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21816 Russell wrote: > > > Of course when I say they "can't afford" to self fund the tools, that is > > a relative term. The point is that the tools cost a lot of money to > > maintain and update. The economics are not there to allow open source > > tools to compete. > > All the fpga vendors need to do is make a publicly available API for > the devices, and keep doing whatever tools they have now. Private and > public projects will start up for various reasons such as profit, > academic purposes, or just to improve on what's available. Eventually > the GPL tools will be better than those done by nine-to-fivers that > couldn't give a stuff about fixing bugs. The fpga vendors can then > either support the GPL tools and keep frozen releases for safety, > or just keep doing their own tools but get useful ideas from the > GPL tools. There'd be less problems for everyone if there was a > choice of tools, and savings for the fpga vendors. I don't think you read anything I wrote. First, every copy of open source tools that is used in place of a vendor supplied tool takes away revenue for vendor tool development. Second, no vendor is going to consider any plan that takes the "family jewels" and trusts them to an outside, free ranging band of developers. The tools are a competitive edge for the FPGA vendors. They can not introduce new parts without in house tool support. So they can't afford to lose the revenue that pays for tool development. You only seeing the local picture of "we can do a better job than the FPGA vendors". I am not at all convinced that this is true. FPGA tools are a moving target and very different from software development tools. Every new generation of FPGAs require very different software. No FPGA vendor can sell parts in an environment where the tools are not up to speed with the parts. We can complain about the state of the tools (and I am often in the front row for that!) but this is most likely the best way to "get the job done". Before anyone starts asking the FPGA vendors to hand over the inside info on their parts, how about we get some *good* open source *front end tools*??? That is the easy part and I don't see anything out there that is anywhere near as good or even usable as the commercial tools. Trust me, if there were decent open source tools for FPGA work, there would be a lot of people working with them. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 11 Oct 2002 00:10:33 +0200 Organization: My own Private Self Lines: 177 Message-ID: <6u4rbundwm.fsf@chonsp.franklin.ch> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1034287833 662 10.0.3.2 (10 Oct 2002 22:10:33 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 10 Oct 2002 22:10:33 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:21860 rickman writes: > Russell wrote: > > > > > Of course when I say they "can't afford" to self fund the tools, that is > > > a relative term. The point is that the tools cost a lot of money to > > > maintain and update. The economics are not there to allow open source > > > tools to compete. Given that they can not[1] stop open source tools, they are going to have to learn to live with them when they arrive (which is just a question of time, nothing else). They can only delay them by not helping (which they will not help, also for liability and support cost reasons, which I fully agree with them). [1] no one less than Peter Alfke said that Xilinx can not, and does not want to. > > All the fpga vendors need to do is make a publicly available API for > > the devices, and keep doing whatever tools they have now. Private and Xilinx has already done that. I have though not heard of any other vendor copying this move. (Thanks Xilinx!) It is called JBits. Mail to jbits@xilinx.com to get an FTP URL and password to download it (its free as in free beer). I presently use Version 2.8 (install Nov 2001), started with 2.4 (late 1999). > > public projects will start up for various reasons such as profit, > > academic purposes, or just to improve on what's available. Or just for the fun of doing it. Or to avoid the frustration which closed source software unavoidably brings with it. > > Eventually > > the GPL tools will be better than those done by nine-to-fivers that > > couldn't give a stuff about fixing bugs. Does not need GPL. Any open source, simply by being open, will get better. Just like science (with all results fully public, no license) with time had to get better then church dogma. > > The fpga vendors can then > > either support the GPL tools and keep frozen releases for safety, > > or just keep doing their own tools but get useful ideas from the That is most likely. They can do their game, and open source does its game. See gcc vs Intel C compiler. > I don't think you read anything I wrote. First, every copy of open > source tools that is used in place of a vendor supplied tool takes away > revenue for vendor tool development. C'est la vie. Every competitor (other chip maker) also does. The best that can happen to an vendor is that when open source arrives, it happens on their chip (and so at cost of their competitors chip sales, both will lose the low-cost end software sales). When my tools arrive, it is going to be Xilinx that profits (because I started from JBits out). And any extra chip they sell because of them will be the best "thanks" (dollars, not words) I can give them for enabling my stuff. > Second, no vendor is going to > consider any plan that takes the "family jewels" and trusts them to an > outside, free ranging band of developers. The tools are a competitive > edge for the FPGA vendors. They can not introduce new parts without in > house tool support. Seems that CPU manufacturers also thought that decades ago. No one expected to sell computers without having the most important compilers (first Assembler. then Fortran and Cobol, later possibly Algol or Basic) for them. Dito also having an own operating system (now that was a costly feature war). Today most CPU makers just cooperate with compiler and operating system makers (see AMD supporting the gcc port to x86-64 and the Linux/x86-64 port). And in the embedded market (more similar to FPGAs than desktop PCs are) we see 8051s from various cloners (with different feature sets) and official Intel tools vs open source ones. > So they can't afford to lose the revenue that pays > for tool development. Unless they change their business model. Adapt or die is the name of the game in business. > You only seeing the local picture of "we can do a better job than the > FPGA vendors". I am not at all convinced that this is true. gcc currently under-perfoms Intels C compiler by about 20%. It is used by way over 10 (or 100 or 1000) times as many users. Because it is a lot easier to use, easier available, more software for it because one can expect it everywhere, no licencing trouble/faillures ... I expect an similar open/wide/basic vs vendor/power/complex split in FPGA tools. And yes, at the prices of top end FPGA tools (5-digit-$), and the cost structure of their paying customers, they should be able to do this. > FPGA tools > are a moving target and very different from software development tools. > Every new generation of FPGAs require very different software. So did every generation of CPUs in the days when every generation had an new instruction set. Today it is less work, because we have binary compatibility and improvement goes into making the existing "bitfiles" (read: binary applications) move faster. I expect FPGAs will have to go the same route: mass market with binary compatibility, cloners[2], etc and an more diversifed "specialist" market where everything goes, for max performance, at high price. The Virtex vs Spartan split already points in that direction. Think of an non-compatible max-power series of Virtex-II, -III, -IV, -V and an Virtex(-I) compatible staying low cost line of Spartan-II, -IIE, -IIEM, -IIX, -II? as an possible future. [2] Think of the next Clearpath with the same size relationship to Altera or Xilinx that AMD has to Intel. And aiming for full pin and bit compatible SRAM based chips (not mask based specials). Drop in replacement, like an AMD K6 (what I am typing this on) fitting an Pentium I socket. And an power/price race ensuing, fought on process technology and feature. > Before anyone starts asking the FPGA vendors to hand over the inside > info on their parts, how about we get some *good* open source *front end > tools*??? They are simply not interesting to program (an important prerequisite for open source programmers, entertainment value), so long the missing back end makes an full-open path impossible. If you are going to do something that requires you to get closed P&R to work, then just use the VHDL/Verilog compiler that comes with it. The "magnet" is a running bitstream, and the shortest path to that is interesting. So the action starts at the back end. > Trust > me, if there were decent open source tools for FPGA work, there would be > a lot of people working with them. They will happen, they are happening. You may remember that 1 year ago said I was planning on doing something, as soon as I get time? I have now got time. I am doing something[3]. I started coding 2.5 months ago. I expect to arrive at 2nd milestone this weekend. About 5th or 6th milestone (these will take longer, and have to share time with other projects that were dormant last 2.5 months) should see bitstreams generated from scratch. Look again in 1 year. [3] http://neil.franklin.ch/Projects/VirtexTools/ -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### From: ldoolitt@recycle.lbl.gov (Larry Doolittle) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 22:54:26 +0000 (UTC) Organization: LBNL News Server Lines: 39 Message-ID: References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> NNTP-Posting-Host: recycle.lbl.gov X-Trace: overload.lbl.gov 1034290466 16756 131.243.169.124 (10 Oct 2002 22:54:26 GMT) X-Complaints-To: "newsmaster@lbl.gov" NNTP-Posting-Date: Thu, 10 Oct 2002 22:54:26 +0000 (UTC) X-Newsreader: slrn (0.9.4.3 UNIX) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!news.lbl.gov!ldoolitt Xref: chonsp.franklin.ch comp.arch.fpga:21926 On 11 Oct 2002 00:10:33 +0200, Neil Franklin wrote: >Xilinx has already [made a publicly available API for their devices]. >It is called JBits. Mail to jbits@xilinx.com to get an FTP URL and >password to download it (its free as in free beer). Free beer doesn't normally come with an NDA. >[2] Think of the next Clearpath with the same size relationship to Altera >or Xilinx that AMD has to Intel. And aiming for full pin and bit compatible >SRAM based chips (not mask based specials). Drop in replacement, like an >AMD K6 (what I am typing this on) fitting an Pentium I socket. And an >power/price race ensuing, fought on process technology and feature. I think you underestimate the maze of interlocking FPGA patents that Altera and Xilinx have, that could quickly shut down anyone who did not approach them on hands and knees with a wad of cash. >> Before anyone starts asking the FPGA vendors to hand over the inside >> info on their parts, how about we get some *good* open source *front end >> tools*??? > >They are simply not interesting to program (an important prerequisite >for open source programmers, entertainment value), so long the missing >back end makes an full-open path impossible. If you are going to do >something that requires you to get closed P&R to work, then just use >the VHDL/Verilog compiler that comes with it. > >The "magnet" is a running bitstream, and the shortest path to that is >interesting. So the action starts at the back end. The newest snapshots of Icarus Verilog have greatly expanded synthesis capabilities. It needs more debugging before it can be truly useful as a front end. I happen to believe that bitstream generation is not interesting to program, so long as the missing front end makes a full-open path impossible. ;-) - Larry ###### From: lass Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 16:58:27 -0600 Organization: Xilinx Lines: 305 Message-ID: <3DA60613.11828B38@xilinx.com> References: Reply-To: lass@xilinx.com NNTP-Posting-Host: 149.199.186.86 Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------D5A17F20A5C5B2EF921988ED" X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!telocity-west!TELOCITY!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21866 --------------D5A17F20A5C5B2EF921988ED Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Yes, Xilinx is listening. We treat comments like this very seriously and have great pride in our software. Feedback like this does have an impact on future software releases if it is specific and/or we have a test case to replicate the problem. Let me try to answer some of the comments and questions. Sorry for the length. > If it does show me the error, it is usually at some intermediate > code, not at the source. For example, if there is a section of the > design done in schematic capture, the program will show a VHDL file > with an error, rather than pulling up the schematic and showing the > source of the error. I believe this is only an issue for schematic flows and is planned to be fixed in a future release. > Sometimes the error message will say that something is off grid > (Error point not on primary grid) on the schematic at x=1608 y=1504 > and expect me to open the schematic and hunt for the X,Y location. If > the program knows the location, it should be able to open the > schematic and highlight the error for me. This is fixed in 5.1i. > The schematic program has an error checker (Tool| Check Schematic) > to help find errors in the schematic. After it you correct them you > can run the tool again. Many times it will still show at least one > error after all of them have been fixed. If you exit the schematic > program, then reopen the schematic, and run the error checker it will > show no errors. This is caused by the same off grid problem and should be fixed in 5.1i. > Since the Xilinx Project Navigator is just a collection of separate > programs and third party utilities, they each have a different user > interface. Each program requires different keystrokes to do the same > thing. For example, in the Schematic program, Zoom-in is F8, in the > State Cad program it is CTL+PgUp, in ChipView (F7). We do have plans to make this more consistent. Much of this is due to tool aquisitions. ECS was aquired from MINC and StateCAD was aquired from VSS. Rewriting these applications has been a lower priority than general ease of use and timing closure. > Sometimes when you edit the pins assignments, save them in > Chipview, and then try to recompile the design nothing happens. You > have to remember that as long as Chipview is open, the Project > Navigator will ignore you and not show any reason why. (Oh yeah, I > have to close that program before it will respond). This is planned to be fixed for the Verilog flow in 5.2i. The VHDL flow should already be working (assuming that you save the file in Chipviewer). > As a special gift, xilinx doesn' t support the synopsys fpga compiler > Xilinx does support FPGA Compiler II and has since it's introduction. > And the spartan (4000 architecture) devices aren' t supported any more. > The Spartan and XC4000 devices are supported with 4.2i and with a free web downloadable package that will be available later this month. > Furthermore a xilinx FAE told me that the fpga editor also died because of a > canceled contract with the manufacturer. > FPGA Editor was written by Xilinx and we have no plans to ever discontinue it. You must be talking about FPGA Express which was discontinued when the contract expired and Synopsys discontinued the product. > I can't say that the Xilinx tools are perfect. But when you do tough > designs I find it a lot easier to see what is going on with the P&R and > to find ways to deal with any problems. > Yes, this is a major focus for our tools. > Where is Xilinx's floorplanner for CPLD designs? > Chipviewer allows you to floorplan your pins. Internal CPLD floorplanning has been somewhat lower on our priority list, but is on our roadmap. > The instructor says, "Oh those are the > normal Xilinx warnings. Just ignore them". How come it generates so > many warnings even when its working? > Most warnings are there because the tool encountered something unexpected and it wants to tell the user about it. Over the past year or 2, we have significantly reduced the number of warnings produced and plan to continue, especially with duplicate warnings. > It's really too bad they don't provide you a way to enable/disable the > minor warnings > Minor warnings on one design can be major warnings on another. How about letting you mark the ones you don't want to see again? > Bad news on 5.1. RPMs slow the mapping waaay down, at least big RPMs do. > Yes, on Ray's design with big RPMs, the mapper slowed down. We have 3 people looking into this. > The latest speed files should be made readily available for 3.3 at > a minimum because of the functional problems with later software releases). > Often, speed file changes require changes to the software, so this would not be possible. > Xilinx, do you have a quality assurance problem with your software? > With tens of thousand of active customers, there will always be edge cases which slip through our verification process. We have over 50 engineers testing the software and spend the last few months of our release cycle doing nothing but testing and fixing bugs. Thanks for the feedback and feel free to email me directly with enhancement requests for the Xilinx software. Steve Lass Director, Software Product Marketing Xilinx, Inc. ###### Message-ID: <3DA60E6F.6778@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3DA60613.11828B38@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 18 Date: Fri, 11 Oct 2002 12:34:07 +1300 NNTP-Posting-Host: 203.79.99.142 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1034292899 203.79.99.142 (Fri, 11 Oct 2002 12:34:59 NZDT) NNTP-Posting-Date: Fri, 11 Oct 2002 12:34:59 NZDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!enews.sgi.com!news.xtra.co.nz!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21883 lass wrote: > It's really too bad they don't provide you a way to enable/disable the > minor warnings > > Minor warnings on one design can be major warnings on another. True. > How about letting you mark the ones you don't want to see again? That's a good idea, and other EDA tools are starting to offer this. A log file should record _all_ warnings, but a scheme to tag ones as 'read and accepted : do not display' is very good. - it means 'clean compile runs' can be possible, and makes new warnings much easier to spot. -jg ###### Message-ID: <3DA61977.A2D1D576@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA5B364.F95F9D0C@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 31 Date: Fri, 11 Oct 2002 00:21:47 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034295707 68.15.41.165 (Thu, 10 Oct 2002 20:21:47 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 20:21:47 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!proxad.net!news-hub.cableinet.net!blueyonder!newspeer1-gui.server.ntli.net!ntli.net!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21871 If you want to get the low power, you are in more or less the same boat. Careful floorplanning can reduce power 20-30% easily. Also, pipelining reduces power in an FPGA. Turns out a substantial amount of power is due to combinatorial settling. The deeper the pipelining, the less the glitches can propagate and the lower the power. A paper at FPGA/2002 discussed this in detail and attributed some 30+% of the power to that phenomenon, and showed that pipelining decreased power. Falk Brunner wrote: > n performance!! > > So Iam a lucky (??) guy who works only on medium and low power stuff and > can get away with the bug. > > -- > MfG > Falk -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3DA61C2B.FD9D0F86@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3DA60613.11828B38@xilinx.com> Content-Type: multipart/alternative; boundary="------------959DEA7D148B5DDE11E14EC3" Lines: 144 Date: Fri, 11 Oct 2002 00:33:19 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034296399 68.15.41.165 (Thu, 10 Oct 2002 20:33:19 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 20:33:19 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21876 --------------959DEA7D148B5DDE11E14EC3 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit In the case of the VIrtexE speed files that got slower with the release of 4.1, the speed files were produced also for 3.3sp8 and distributed to the FAEs. I have a full set of them (and had to recall several designs because of the degraded numbers). I can understand if the speed files aren't available because it is for an older version that is no longer supported, but in the case where they have been produced, what is the reason for not making them available. Instead, I have to step in and help past customers because they don't have access to the speed files. My enhancement request is to get the stuff that is in there working before adding new stuff or making gratuitous changes to the GUIs. lass wrote: > Often, speed file changes require changes to the software, > so this would > not be possible. > >> Xilinx, do you have a quality assurance problem with your software? >> > With tens of thousand of active customers, there will > always be edge cases > which slip through our verification process. We have over > 50 engineers testing > the software and spend the last few months of our release > cycle doing nothing > but testing and fixing bugs. > > Thanks for the feedback and feel free to email me directly > with enhancement > requests for the Xilinx software. > > Steve Lass > Director, Software Product Marketing > Xilinx, Inc. > > > > > > > > > > > > > > > > > > > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 --------------959DEA7D148B5DDE11E14EC3 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit In the case of the VIrtexE speed files that got slower with the release of 4.1, the speed files were produced also for 3.3sp8 and distributed to the FAEs.  I have a full set of them (and had to recall several designs because of the degraded numbers).  I can understand if the speed files aren't available because it is for an older version that is no longer supported, but in the case where they have been produced, what is the reason for not making them available.  Instead, I have to step in and help past customers because they don't have access to the speed files.

My enhancement request is to get the stuff that is in there working before adding new stuff or making gratuitous changes to the GUIs.

lass wrote:

Often, speed file changes require changes to the software, so this would
not be possible. 
Xilinx, do you have a quality assurance problem with your software?
With tens of thousand of active customers, there will always be edge cases
which slip through our verification process.  We have over 50 engineers testing
the software and spend the last few months of our release cycle doing nothing
but testing and fixing bugs.

Thanks for the feedback and feel free to email me directly with enhancement
requests for the Xilinx software.

Steve Lass
Director, Software Product Marketing
Xilinx, Inc.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759
  --------------959DEA7D148B5DDE11E14EC3-- ###### Reply-To: "Steve Casselman" From: "Steve Casselman" Newsgroups: comp.arch.fpga References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> Subject: Re: Why can Xilinx sw be as good as Altera's sw? Lines: 42 Organization: Virtual Computer Corporation X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: NNTP-Posting-Host: 64.164.173.118 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr21.news.prodigy.com 1034296583 ST000 64.164.173.118 (Thu, 10 Oct 2002 20:36:23 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 20:36:23 EDT X-UserInfo1: FKPO@MONWJWYB_XYGRNFOFTBTR\B@GXLN@GZ_GYO^RR@ETUCCNSKQFCY@TXDX_WHSVB]ZEJLSNY\^J[CUVSA_QLFC^RQHUPH[P[NRWCCMLSNPOD_ESALHUK@TDFUZHBLJ\XGKL^NXA\EVHSP[D_C^B_^JCX^W]CHBAX]POG@SSAZQ\LE[DCNMUPG_VSC@VJM Date: Fri, 11 Oct 2002 00:36:23 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.usenet-edu.net!usenet-edu.net!proxad.net!news.stealth.net!news.stealth.net!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr21.news.prodigy.com.POSTED!2ac7f5fa!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21867 > I think you underestimate the maze of interlocking FPGA patents > that Altera and Xilinx have, that could quickly shut down anyone > who did not approach them on hands and knees with a wad of cash. > Your telling me. At one time Xilinx want me to give up all my patent rights forever to get a copy of JBits. Of course I have the patent on run time generation so no one is going to stop me from what I'm doing. Also there is no guarantee that they will continue the program now that Steve Guccione doesn't work there any more. A small group of hackers could reverse engineer the bitstream. Use xdl to get the info go into the FPGA editor and start turning on pips. You only have to do about 10 or 12 tiles and the whole thing should fall out. Even without the bitstrean you could use xdl and translate that into the U of Toronto place and route tool and you'd be happening. > I happen to believe that bitstream generation is not interesting > to program, so long as the missing front end makes a full-open path > impossible. ;-) This is not a clear picture of what it is all about. By understanding the bit level you can do some very interesting things. You can an algorithm and design it so that when given the data you produce a design just for that data. This is the way to be ASICs. For example there is a DES paper done in JBits where you take the key and generate a DES design just for that key. Sure an ASIC could use the same techniques but who wants to buy a chip that can only encode/decode with one key? If you load constants at the bit level then you save the area you would have to use to mux in the constants so you can put more logic in the same area and thus have a high through-put. The only reason we are still using (say it with me) sucky simulated annealing is everyone treats FPGAs like ASICs and not like CPUs. Imagine have your C code chopped up with no regard for your subroutines and then randomly moved around till its "pretty close to what you want." It is historically hysterical. Some day it will be different. I'm also working on tools that let you manipulate the bit stream and they work with the V1 and V2 parts. You should be able to give a name to some LUT or flop and change it from a command line and have the software generate a partial packet and down load the change live. I'll have that working in a few weeks. Steve ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 21:25:58 -0400 Organization: Arius, Inc Lines: 214 Message-ID: <3DA628A6.A32FE4@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVaB3iTH0oo05mawpVu75vGsfFBdBD9MkLkoxQ0N1VlLahGNRQowZ4vc X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 11 Oct 2002 01:25:59 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed1.cidera.com!Cidera!dca6-feed2.news.algx.net!allegiance!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21933 Neil Franklin wrote: > > rickman writes: > > > Russell wrote: > > > > > > > Of course when I say they "can't afford" to self fund the tools, that is > > > > a relative term. The point is that the tools cost a lot of money to > > > > maintain and update. The economics are not there to allow open source > > > > tools to compete. > > Given that they can not[1] stop open source tools, they are going to have > to learn to live with them when they arrive (which is just a question > of time, nothing else). They can only delay them by not helping (which > they will not help, also for liability and support cost reasons, which > I fully agree with them). > > [1] no one less than Peter Alfke said that Xilinx can not, and does > not want to. They can not in the sense of copyright infringement or patent issues perhaps. But if they don't have the inside scoop on the chips, they will have a long row to hoe. That brings us back to one of my points. The open source tools will *never* be up to date. The chip cycle is just too short for a bunch of freeware guys to keep up with. This point has been discussed here several times before. It always comes down to a few designers who say it won't happen and a few others who say it is inevitable. But we never see the tools... > When my tools arrive, it is going to be Xilinx that profits (because I > started from JBits out). And any extra chip they sell because of them > will be the best "thanks" (dollars, not words) I can give them for > enabling my stuff. And when can we expect this tool? What devices will it support? What will be *better* about it than the tools already in use? > > Second, no vendor is going to > > consider any plan that takes the "family jewels" and trusts them to an > > outside, free ranging band of developers. The tools are a competitive > > edge for the FPGA vendors. They can not introduce new parts without in > > house tool support. > > Seems that CPU manufacturers also thought that decades ago. No one > expected to sell computers without having the most important compilers > (first Assembler. then Fortran and Cobol, later possibly Algol or > Basic) for them. Dito also having an own operating system (now that > was a costly feature war). > > Today most CPU makers just cooperate with compiler and operating system > makers (see AMD supporting the gcc port to x86-64 and the Linux/x86-64 > port). > > And in the embedded market (more similar to FPGAs than desktop PCs > are) we see 8051s from various cloners (with different feature sets) > and official Intel tools vs open source ones. This has also been discussed before. Compilers have become commodity items where one is about as good as another for 99% of the work done with them. FPGA software is still in the stage of being very highly tuned to the chip else it is of little value. If you are doing simple designs in uncrowded chips then you don't care what tools you use, but most FPGA users push their designs if not initially, they do when being upgraded in the field. They need tools that work very well with their chip. > > So they can't afford to lose the revenue that pays > > for tool development. > > Unless they change their business model. Adapt or die is the name of > the game in business. However there is *nothing* to adapt to. There are *no* open source tools that can be used on a production design. > > You only seeing the local picture of "we can do a better job than the > > FPGA vendors". I am not at all convinced that this is true. > > gcc currently under-perfoms Intels C compiler by about 20%. It is used > by way over 10 (or 100 or 1000) times as many users. Because it is a lot > easier to use, easier available, more software for it because one can > expect it everywhere, no licencing trouble/faillures ... > > I expect an similar open/wide/basic vs vendor/power/complex split in > FPGA tools. And yes, at the prices of top end FPGA tools (5-digit-$), > and the cost structure of their paying customers, they should be able > to do this. You can expect what you want, but that won't make it happen. There are very few engineers that are going to start a significant project with open source FPGA tools when their company will pay for the commercial tools. You make a lot of predictions that won't be tested for 10 years or more. Someone correct me if I am wrong, but Xilinx and Altera have NO $5-digit tools (unless you are counting the pennies). The expensive tools are the synthesis and simulation tools. These are third party and they charge so much because they are so good. But this is the first place that open-source tools should show up. All the interfaces are defined in public standards, the functionality is known, all that is needed is the open source code. So where is it??? Where are the open source synthesizers and simulators? I believe there are one or two out there and they *stink*. Hopefully they will improve with time. Certainly they are much more like the gcc target. But the back end tools are very different. *That* is why there are no third party back end tool vendors. > > FPGA tools > > are a moving target and very different from software development tools. > > Every new generation of FPGAs require very different software. > > So did every generation of CPUs in the days when every generation had > an new instruction set. Today it is less work, because we have binary > compatibility and improvement goes into making the existing "bitfiles" > (read: binary applications) move faster. As soon as the x86 came out (~1981, IIRC) the basic instruction set was cast in concrete. About 5 years later compilers matured and by 1991 they had become commodities. > I expect FPGAs will have to go the same route: mass market with binary > compatibility, cloners[2], etc and an more diversifed "specialist" market > where everything goes, for max performance, at high price. Patents will stop cloners. There is no market force driving FPGAs in this direction, just as there is no market force driving all CPU makers to adopt a common instruction set. If Intel could stop them, there would be no AMD or Cyrix chips. But even Intel is smart enough to know that multiple instruction sets are a *good* thing. That is whey they built so many different chips over the years. > The Virtex vs Spartan split already points in that direction. Think of > an non-compatible max-power series of Virtex-II, -III, -IV, -V and an > Virtex(-I) compatible staying low cost line of Spartan-II, -IIE, -IIEM, > -IIX, -II? as an possible future. I'm not sure what you mean by this. Are you talking about a competitor chip? Xilinx won't let that happen... > [2] Think of the next Clearpath with the same size relationship to Altera > or Xilinx that AMD has to Intel. And aiming for full pin and bit compatible > SRAM based chips (not mask based specials). Drop in replacement, like an > AMD K6 (what I am typing this on) fitting an Pentium I socket. And an > power/price race ensuing, fought on process technology and feature. I think you mean Clearlogic... and they have gone the way of the dodo bird because of infringement issues. AMD could make parts that fit the Pentium socket because they had a license for that. After Socket 7 (IIRC) they no longer had that license and they now have to make their own interfaces. No FPGA company is going to let a startup copy their technology. > > Before anyone starts asking the FPGA vendors to hand over the inside > > info on their parts, how about we get some *good* open source *front end > > tools*??? > > They are simply not interesting to program (an important prerequisite > for open source programmers, entertainment value), so long the missing > back end makes an full-open path impossible. If you are going to do > something that requires you to get closed P&R to work, then just use > the VHDL/Verilog compiler that comes with it. Now you understand... :) > The "magnet" is a running bitstream, and the shortest path to that is > interesting. So the action starts at the back end. So you want to do the hardest part first, show the least result and have your work obsoleted most rapidly? > > Trust > > me, if there were decent open source tools for FPGA work, there would be > > a lot of people working with them. > > They will happen, they are happening. > > You may remember that 1 year ago said I was planning on doing something, > as soon as I get time? I have now got time. I am doing something[3]. > > I started coding 2.5 months ago. I expect to arrive at 2nd milestone > this weekend. About 5th or 6th milestone (these will take longer, and > have to share time with other projects that were dormant last 2.5 months) > should see bitstreams generated from scratch. Look again in 1 year. > > [3] http://neil.franklin.ch/Projects/VirtexTools/ I looked at your page and I do not see where you are headed. Once you have built all the parts of the intended toolchain, what will the flow be? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 21:34:02 -0400 Organization: Arius, Inc Lines: 19 Message-ID: <3DA62A8A.EBDBD1E@yahoo.com> References: <3DA60613.11828B38@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbMyWH3wFG2Vgz6RAV9T5S5texI2o/8o5msDA/pWdIp7KlFA0owwiDl X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 11 Oct 2002 01:33:58 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.wirehub.nl!news.tele.dk!small.news.tele.dk!204.71.34.15!news-out.cwix.com!newsfeed.cwix.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21863 lass wrote: > > Yes, Xilinx is listening. Stop it! You're creeping me out... :-( -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3DA63608.C5A58E9E@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.10.164 Lines: 72 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Fri, 11 Oct 2002 12:23:04 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034302640 203.134.67.67 (Thu, 10 Oct 2002 22:17:20 EDT) NNTP-Posting-Date: Thu, 10 Oct 2002 22:17:20 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.usenet-edu.net!usenet-edu.net!fr.clara.net!heighliner.fr.clara.net!news-hub.siol.net!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21881 rickman wrote: > > Neil Franklin wrote: > > > ... > They can not in the sense of copyright infringement or patent issues > perhaps. But if they don't have the inside scoop on the chips, they > will have a long row to hoe. That brings us back to one of my points. > The open source tools will *never* be up to date. The chip cycle is > just too short for a bunch of freeware guys to keep up with. The *family* of a chip stays around for a while, and any compilers/fitters can be tuned to each size and architecture with table-driven rules that would be easy to update given a sufficient data sheet. There's also the advantage that you can still maintain old designs easily. > This point has been discussed here several times before. It always > comes down to a few designers who say it won't happen and a few others > who say it is inevitable. But we never see the tools... ... > However there is *nothing* to adapt to. There are *no* open source > tools that can be used on a production design. Linux and open source are only fairly new, and there's a certain learning curve before capable developers appear for more specialized tool development. Also, before jbits, creating open source tools is completely uninteresting if all it involves is making a pretty front-end. > > gcc currently under-perfoms Intels C compiler by about 20%. It is used > > by way over 10 (or 100 or 1000) times as many users. Because it is a lot > > easier to use, easier available, more software for it because one can > > expect it everywhere, no licencing trouble/faillures ... > > > > I expect an similar open/wide/basic vs vendor/power/complex split in > > FPGA tools. And yes, at the prices of top end FPGA tools (5-digit-$), > > and the cost structure of their paying customers, they should be able > > to do this. > > You can expect what you want, but that won't make it happen. There are > very few engineers that are going to start a significant project with > open source FPGA tools when their company will pay for the commercial > tools. You make a lot of predictions that won't be tested for 10 years > or more. I would start with an open source tool if there was one at the time. I'd also be doing bug fixes and adding *useful* features (i'm not quite up to that level on linux yet). > Someone correct me if I am wrong, but Xilinx and Altera have NO $5-digit > tools (unless you are counting the pennies). The expensive tools are > the synthesis and simulation tools. These are third party and they > charge so much because they are so good. Leonardo-spectrum GUI good? Most of the other tools could be improved too. > But this is the first place > that open-source tools should show up. All the interfaces are defined > in public standards, the functionality is known, all that is needed is > the open source code. So where is it??? Where are the open source > synthesizers and simulators? There's no motivation to do it if there's no info available for the low-level control of most fpgas. It would be like doing open source development if the only compilers available had to be bought from microsoft. The opcodes and assembly instructions of microprocessors are freely released by cpu vendors to encourage tool creation. The same should apply to fpgas. FPGAs have a short life cycle because the industry is immature. Process limits will slow this down in a few years, when open-source will be much more common-place. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 10 Oct 2002 22:28:25 -0400 Organization: Arius, Inc Lines: 52 Message-ID: <3DA63749.134CE79C@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVYb7OjHE/OG/SAfWWWzu0Q0YV+s4XvmIygY8zAVT9zz9dIskz2+wOu2 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 11 Oct 2002 02:28:23 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.cwix.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21861 Steve Casselman wrote: > This is not a clear picture of what it is all about. By understanding the > bit level you can do some very interesting things. You can an algorithm and > design it so that when given the data you produce a design just for that > data. This is the way to be ASICs. For example there is a DES paper done in > JBits where you take the key and generate a DES design just for that key. > Sure an ASIC could use the same techniques but who wants to buy a chip that > can only encode/decode with one key? If you load constants at the bit level > then you save the area you would have to use to mux in the constants so you > can put more logic in the same area and thus have a high through-put. Uh, correct me if I am wrong, but don't the FPGAs have RAM and muxes to do all this??? So you could just as easily put RAM and muxes on your ASIC and accomplish the same task in the same *single key but programmable* way. It would certainly be more expensive to make an ASIC, but there would still be performance gains. The ASIC would have about the same timing on the RAM and logic, but certainly it would have faster routing. > The > only reason we are still using (say it with me) sucky simulated annealing is > everyone treats FPGAs like ASICs and not like CPUs. Imagine have your C code > chopped up with no regard for your subroutines and then randomly moved > around till its "pretty close to what you want." It is historically > hysterical. Some day it will be different. I'm also working on tools that > let you manipulate the bit stream and they work with the V1 and V2 parts. > You should be able to give a name to some LUT or flop and change it from a > command line and have the software generate a partial packet and down load > the change live. I'll have that working in a few weeks. Of course no one treats FPGAs as CPUs... CPUs are so slow compared to logic. Very few FPGAs run C code. But if you goal is to run C code then an FPGA could be the best way to do that using on the fly configured logic. But there is a lot of work that needs to be done that does not require the FPGA tools. It will be hard indeed to see what is happening inside the chip when the chip is programming itself. This would be much better simulated at a higher level and when working well brought down to the bit stream, IMHO. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Fri, 11 Oct 2002 04:15:02 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> X-Complaints-To: abuse@supernews.com Lines: 15 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed1.cidera.com!Cidera!telocity-west!TELOCITY!sn-xit-03!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:21892 > Imagine have your C code >chopped up with no regard for your subroutines and then randomly moved >around till its "pretty close to what you want." Works well in some cases. :) Run the code, sample the PC, move things around to avoid cache conflicts and/or cache polution by unused code. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Fri, 11 Oct 2002 05:20:00 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: X-Complaints-To: abuse@supernews.com Lines: 50 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed1.cidera.com!Cidera!telocity-west!TELOCITY!sn-xit-03!sn-xit-06!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:21899 >I am an independent consultant developing FPGAs and PLDs using both >Xilinx and Altera development software. ... >The Altera tools are such a pleasure to use. The tools are very well >integrated into a single Windows program. ... >The Xilinx toolset is a hodgepodge of command line tools with a lousy >user interface on top of it. ... Sounds like you are doing one person sized projects and that you like GUIs. GUIs are good for things you only do a few times. They are horrible if you need to keep track of all the fine print (flag/option settings) and/or want somebody else (on a different machine) to be able to reproduce your work exactly. As FPGA designs become more complicated, the problem is changing from hardware/schematics to software/simulation. Hopefully the FPGA tool builders will learn/steal from the software community rather than reinventing too many wheels. I think the key step that most non-tiny software projects need is to be able to recreate a set of output bits from a specified version of the input files. That means you need to identify all the input files and record the recipe for a sequence of commands (with their flags and parameters) [or the GUI interactions] that are needed to make the output files. Most software projects use some form of source control setup to keep track of versions of the source files. If you have something like that then it is often reasonable to use something like make to hold the recipe in a file called "makefile". My main gripe about the Xilinx software is that the documentation needed to do make style (aka command line) work flow was hard to find/understand. I could find the info on each indivdual command but I missed the big picture. What I wanted was a flow-chart style diagram with something like boxes for files, circles for commands, and diamonds/branches for checking the status of the previous command. A sample makefile would be great too - or two, one for a tiny project and one for a large sample. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: Petter Gustad Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 11 Oct 2002 10:01:35 +0200 Organization: 502 You are not allowed to talk Lines: 29 Message-ID: References: NNTP-Posting-Host: 195.0.185.86 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: oslo-nntp.eunet.no 1034323557 29597 195.0.185.86 (11 Oct 2002 08:05:57 GMT) X-Complaints-To: abuse@KPNQwest.no NNTP-Posting-Date: 11 Oct 2002 08:05:57 GMT User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.teledanmark.no!uninett.no!Norway.EU.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21913 hmurray@suespammers.org (Hal Murray) writes: > GUIs are good for things you only do a few times. They are horrible > if you need to keep track of all the fine print (flag/option settings) > and/or want somebody else (on a different machine) to be able to > reproduce your work exactly. Hal, we're probably from the same planet, even though I'm probably a little closer to the North Pole :-) > My main gripe about the Xilinx software is that the documentation > needed to do make style (aka command line) work flow was hard > to find/understand. I could find the info on each indivdual > command but I missed the big picture. What I wanted was a > flow-chart style diagram with something like boxes for files, > circles for commands, and diamonds/branches for checking the I found a flowchart on page 2-4 of http://support.xilinx.com/support/sw_manuals/3_1i/download/dev_ref.zip This together with a description of all the different programs was fairly easy to incorporate into script to run partgen, ngdbuild, map, par, trce, bitgen, promgen, ngdanno, and ngd2ver. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter ###### Message-ID: <3DA6C878.EBDD5A90@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 47 Date: Fri, 11 Oct 2002 12:48:25 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034340505 68.15.41.165 (Fri, 11 Oct 2002 08:48:25 EDT) NNTP-Posting-Date: Fri, 11 Oct 2002 08:48:25 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!newsfeed.icl.net!newsfeed.fjserv.net!kibo.news.demon.net!demon!news-hub.cableinet.net!blueyonder!newspeer1-gui.server.ntli.net!ntli.net!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21877 One can also use the program.his or fe.log files out of the gui to reconstruct the command sequence and exact switch settings. Petter Gustad wrote: > hmurray@suespammers.org (Hal Murray) writes: > > > GUIs are good for things you only do a few times. They are horrible > > if you need to keep track of all the fine print (flag/option settings) > > and/or want somebody else (on a different machine) to be able to > > reproduce your work exactly. > > Hal, we're probably from the same planet, even though I'm probably a > little closer to the North Pole :-) > > > My main gripe about the Xilinx software is that the documentation > > needed to do make style (aka command line) work flow was hard > > to find/understand. I could find the info on each indivdual > > command but I missed the big picture. What I wanted was a > > flow-chart style diagram with something like boxes for files, > > circles for commands, and diamonds/branches for checking the > > I found a flowchart on page 2-4 of > > http://support.xilinx.com/support/sw_manuals/3_1i/download/dev_ref.zip > > This together with a description of all the different programs was > fairly easy to incorporate into script to run partgen, ngdbuild, map, > par, trce, bitgen, promgen, ngdanno, and ngd2ver. > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Fri, 11 Oct 2002 15:52:02 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 45 Message-ID: References: <6u4rbundwm.fsf@chonsp.franklin.ch> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1034351522 424 128.32.112.203 (11 Oct 2002 15:52:02 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Fri, 11 Oct 2002 15:52:02 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21884 In article , Steve Casselman wrote: >This is not a clear picture of what it is all about. By understanding the >bit level you can do some very interesting things. You can an algorithm and >design it so that when given the data you produce a design just for that >data. This is the way to be ASICs. For example there is a DES paper done in >JBits where you take the key and generate a DES design just for that key. >Sure an ASIC could use the same techniques but who wants to buy a chip that >can only encode/decode with one key? Probably IDEA, not DES, as IDEA is the one which really benefits from specialization (turns 16x16->32 multiplies into multiplies by constant). And this is only suitable when you unroll the whole encryption pipeline anyway, which costs a fair amount of area. AES wins effectively nothing from specialization (removes 128 xors/round and the space used to store whateever subkeys, when you can easily do AES fully key agile) I always like specialization, but I've never been able to think of too much use for it beyond cases where you can strenght reduce a multiply/divide or radically shrink a bitwidth. > The only reason we are still using (say it with me) sucky simulated > annealing is everyone treats FPGAs like ASICs and not like > CPUs. Imagine have your C code chopped up with no regard for your > subroutines and then randomly moved around till its "pretty close to > what you want." It is historically hysterical. Some day it will be > different. I more blame the synthesis tools, as a synthesis tool's produced datapath shouln't care about the placer at all, because everything should be nicely locked down. But everyone's heard this rant already. > I'm also working on tools that let you manipulate the bit stream and > they work with the V1 and V2 parts. You should be able to give a > name to some LUT or flop and change it from a command line and have > the software generate a partial packet and down load the change > live. I'll have that working in a few weeks. Nifty. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### Message-ID: <3da79b0d$0$23169$afc38c87@news.optusnet.com.au> From: hamish@cloud.net.au Subject: Re: Why can Xilinx sw be as good as Altera's sw? Newsgroups: comp.arch.fpga References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> <3da42e14$0$12760$afc38c87@news.optusnet.com.au> <3DA45599.E098230E@andraka.com> User-Agent: tin/1.5.14-20020917 ("Chop Suey!") (UNIX) (Linux/2.2.18 (i586)) Date: 12 Oct 2002 03:46:22 GMT Lines: 18 NNTP-Posting-Host: 211.28.158.161 X-Trace: 1034394382 23169 211.28.158.161 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!psinet-eu-nl!news-x2.support.nl!newsfeed.zip.com.au!spool01.syd.optusnet.com.au!spool.optusnet.com.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21927 Ray Andraka wrote: > Hamish, be careful with that. 4.2 has a bug where designs with large ncds gets a > memory conflict under win2K. We made that mistake, and had to run under NT4 in > order to continue on with the design. That 2v6000 design gets through map in an > hour and 40 minutes on an old 800 MHz P3 with 1GB (paging like crazy) under 4.2i > on NT, won't run on 4.2i under win2K, and takes over 25 hrs under 5.1 running on a > 2GHz K7 with 2GB memory . Ouch. What was the % utilisation of the 2V6000? The biggest I've done is 50-60% and map and par times and memory usage haven't been unreasonable. We've had some regular BITGEN crashes on NT which haven't happened on 2000. Occasionally a PAR crash too. Hamish -- Hamish Moffatt VK3SB ###### Message-ID: <3da79b35$0$23169$afc38c87@news.optusnet.com.au> From: hamish@cloud.net.au Subject: Re: Why can Xilinx sw be as good as Altera's sw? Newsgroups: comp.arch.fpga References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> <3da42e14$0$12760$afc38c87@news.optusnet.com.au> User-Agent: tin/1.5.14-20020917 ("Chop Suey!") (UNIX) (Linux/2.2.18 (i586)) Date: 12 Oct 2002 03:47:01 GMT Lines: 12 NNTP-Posting-Host: 211.28.158.161 X-Trace: 1034394421 23169 211.28.158.161 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!feed.news.nacamar.de!newsfeed.stueberl.de!solnet.ch!solnet.ch!triton.net!smallfeed.triton.net!newsfeed.zip.com.au!spool01.syd.optusnet.com.au!spool.optusnet.com.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21925 Uwe Bonnes wrote: > hamish@cloud.net.au wrote: > : Still waiting for v5.1 to arrive. Upgrading all machines to Win2000 in > : anticipation. > > For a start, use the free downloadable Webpack, which is based on 5.1. Does it do 2V6000s? I'd guess not! Hamish -- Hamish Moffatt VK3SB ###### Message-ID: <3DA7A3EF.6105238B@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> <3da42e14$0$12760$afc38c87@news.optusnet.com.au> <3DA45599.E098230E@andraka.com> <3da79b0d$0$23169$afc38c87@news.optusnet.com.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 66 Date: Sat, 12 Oct 2002 04:24:46 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034396686 68.15.41.165 (Sat, 12 Oct 2002 00:24:46 EDT) NNTP-Posting-Date: Sat, 12 Oct 2002 00:24:46 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21873 The whole thing compiles in about 6 hours on an 800 MHz P3 with 1GB memory with lots of paging under 4.2i with NT. Gets a memory conflict under win2K while reading the .ncd, which is just over 100MB. With 5.1sp1, it complestes map over 25 hours into the compile on a 2GHz P4 with 2GB memory, independent of OS. We still do alot of virtex (QPRO), spartanII and virtexE designs, for which we use 3.3sp8 because it does better. Haven't really seen PAR and bitgen problems there. Here's the design summary from map under the NT machine: Design Summary -------------- Number of errors: 0 Number of warnings: 18390 Number of Slices: 26,854 out of 33,792 79% Number of Slices containing unrelated logic: 0 out of 26,854 0% Number of Slice Flip Flops: 46,882 out of 67,584 69% Total Number 4 input LUTs: 34,907 out of 67,584 51% Number used as LUTs: 30,327 Number used as a route-thru: 32 Number used for Dual Port RAMs: 1,334 (Two LUTs used per Dual Port RAM) Number used as Shift registers: 3,214 Number of bonded IOBs: 779 out of 824 94% IOB Flip Flops: 1,601 Number of Tbufs: 278 out of 16,896 1% Number of Block RAMs: 75 out of 144 52% Number of MULT18X18s: 50 out of 144 34% Number of GCLKs: 6 out of 16 37% Number of Startups: 1 out of 1 100% Number of Captures: 1 out of 1 100% Number of RPM macros: 88 Total equivalent gate count for design: 6,224,453 hamish@cloud.net.au wrote: > Ray Andraka wrote: > > Hamish, be careful with that. 4.2 has a bug where designs with large ncds gets a > > memory conflict under win2K. We made that mistake, and had to run under NT4 in > > order to continue on with the design. That 2v6000 design gets through map in an > > hour and 40 minutes on an old 800 MHz P3 with 1GB (paging like crazy) under 4.2i > > on NT, won't run on 4.2i under win2K, and takes over 25 hrs under 5.1 running on a > > 2GHz K7 with 2GB memory . > > Ouch. What was the % utilisation of the 2V6000? The biggest I've done is > 50-60% and map and par times and memory usage haven't been unreasonable. > > We've had some regular BITGEN crashes on NT which haven't happened on > 2000. Occasionally a PAR crash too. > > Hamish > -- > Hamish Moffatt VK3SB -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Sat, 12 Oct 2002 12:00:23 +0100 Lines: 13 Message-ID: References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> <3da42e14$0$12760$afc38c87@news.optusnet.com.au> <3DA45599.E098230E@andraka.com> <3da79b0d$0$23169$afc38c87@news.optusnet.com.au> <3DA7A3EF.6105238B@andraka.com> NNTP-Posting-Host: tile.demon.co.uk X-Trace: news.demon.co.uk 1034420662 28382 158.152.50.250 (12 Oct 2002 11:04:22 GMT) X-Complaints-To: abuse@demon.net NNTP-Posting-Date: Sat, 12 Oct 2002 11:04:22 +0000 (UTC) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 X-Priority: 3 X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MSMail-Priority: Normal Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!newsfeed.icl.net!newsfeed.fjserv.net!proxad.net!proxad.net!kibo.news.demon.net!news.demon.co.uk!demon!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21901 Ray Andraka wrote > The whole thing compiles in about 6 hours on an 800 MHz P3 with 1GB > memory with lots of paging under 4.2i with NT. Gets a memory conflict > under win2K while reading the .ncd, which is just over 100MB. How big was the EDIF? I hate the binary format. Searching through text is not for fun, but with a binary file you are up the river without a paddle if something goes wrong. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 12 Oct 2002 16:29:58 +0200 Organization: My own Private Self Lines: 22 Message-ID: <6u3crb3f2x.fsf@chonsp.franklin.ch> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1034432998 442 10.0.3.2 (12 Oct 2002 14:29:58 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 12 Oct 2002 14:29:58 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:21935 ldoolitt@recycle.lbl.gov (Larry Doolittle) writes: > On 11 Oct 2002 00:10:33 +0200, Neil Franklin wrote: > >Xilinx has already [made a publicly available API for their devices]. > >It is called JBits. Mail to jbits@xilinx.com to get an FTP URL and > >password to download it (its free as in free beer). > > Free beer doesn't normally come with an NDA. Neither does JBits. At least I was never presented with, nor have signed an NDA. And I of principle do not sign anythign that forces me to withhold information from anyone, and consider NDAs an total KO criterium for using anything. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 12 Oct 2002 18:21:20 +0200 Organization: My own Private Self Lines: 330 Message-ID: <6uzntj1vcv.fsf@chonsp.franklin.ch> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1034439680 549 10.0.3.2 (12 Oct 2002 16:21:20 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 12 Oct 2002 16:21:20 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:21936 rickman writes: > Neil Franklin wrote: > > > > Given that they can not[1] stop open source tools, they are going to have > > to learn to live with them when they arrive (which is just a question > > of time, nothing else). They can only delay them by not helping (which > > they will not help, also for liability and support cost reasons, which > > I fully agree with them). > > They can not in the sense of copyright infringement or patent issues > perhaps. That is the only "stop dead" type of stopping. And so the only deadly one to open source developers. And so the only one that I mind. Technical problems we can handle. An buch of armed law enforcers saying "stop or we arrest you (or kill if you resist) for daring our rulers" we can not. > But if they don't have the inside scoop on the chips, they > will have a long row to hoe. That is not "stop dead", just delay. Better late than never. A lot better. > That brings us back to one of my points. > The open source tools will *never* be up to date. The chip cycle is > just too short for a bunch of freeware guys to keep up with. Xilinx still sells XC4000/Spartan. After that came XC4000XL/Spartan-XL, then Virtex/Spartan-II, then Virtex-E/Spartan-IIE, then Virtex-II, now Virtex-IIpro. That makes 6 families being sold in parallel. Actually 3 large families, with each 2 subfamilies. Looks like an active sales life of about 10 years for one particular family. So any tool supporting Virtex/Spartan-II in say 1-2 years, and extendable to Virtex-E/Spartan-IIE, has at least an 5 year market life in it. Reverse-engineering Virtex-II should not take 5 years, so we can keep up... > who say it is inevitable. But we never see the tools... You can now see an actual project, started, that has an planned out path leading to tools. > > When my tools arrive, it is going to be Xilinx that profits (because I > > started from JBits out). And any extra chip they sell because of them > > will be the best "thanks" (dollars, not words) I can give them for > > enabling my stuff. > > And when can we expect this tool? First minimal stuff in estimated 1 years time, decently usable in 2 years, is my current estimate. > What devices will it support? Initially Virtex/Spartan-II (what JBits does), later Virtex-E/Spartan-IIE. > What > will be *better* about it than the tools already in use? All that in open source is better: - simple download/compile/install/use, any computer/OS native - no licensing, can give copy to anyone. allows "config&compile at customers site" designs, and yes, that includes "customer selects modules and generates bitstream that runs them" style adaption to modular interface hardware (see recompiling Linux kernel as an example) - bugs can be fixed by anyone, or more likey have already got fixed before you ever hit them, even OpenBSD style code audits go - guaranteed to remain available (because user-adaptable to new systems ad infinitum), no forced upgrade cycle - anyone can add their brains to development, wherever they have the expertise (compare the open process of science vs pronouncements from high from any closed governing body) For such features many (including myself) are willing to sacrifice using the latest chip family for the time needed to reverse-engineer, dito also not wringing the last drop of power out of an chip. > > And in the embedded market (more similar to FPGAs than desktop PCs > > are) we see 8051s from various cloners (with different feature sets) > > and official Intel tools vs open source ones. > > This has also been discussed before. Compilers have become commodity > items where one is about as good as another for 99% of the work done > with them. FPGA software is still in the stage of being very highly > tuned to the chip else it is of little value. FPGAs are newer than CPUs, they are bound to be at an earlier stage in the normal industrial process from novelty to mature technology. Screws from one manufacturer once did not fit nuts from an other, about 120 years ago, due to everyone using their own threads. Once the basic issues and design space in thread design were explored, standards came. > If you are doing simple > designs in uncrowded chips then you don't care what tools you use, but > most FPGA users push their designs if not initially, they do when being > upgraded in the field. They need tools that work very well with their > chip. How many today forgo the ultimate performance of FPGA Editor in favor of the simpler life with VHDL or Verilog? How many forgo the power increases of floorplanning for less work? How many are going to soon start using things like Handel-C because programmer time costs more than chip space (in small series work)? There exist "ultimate power" users, and they will demand "ultimate power" tools (and pay for them). There also exist less demanding users who will put up with an less powerfull tools if they offer them an better deal for their particular circumstances. It is horses for courses. > > I expect an similar open/wide/basic vs vendor/power/complex split in > > FPGA tools. And yes, at the prices of top end FPGA tools (5-digit-$), > > and the cost structure of their paying customers, they should be able > > to do this. > > You can expect what you want, but that won't make it happen. There are > very few engineers that are going to start a significant project with > open source FPGA tools when their company will pay for the commercial > tools. Some companies can expect an >5-digit profit increase from 5-digit tools. They will stay with them (stupid if they did not). Others can not expect such added profits, they already today do not afford them (they are those that today demand free Webpack&so on). > You make a lot of predictions that won't be tested for 10 years > or more. Anyone planning on shaping the future has to make predictions. The best we can do is look for similar cases. CPUs, in particular embedded/DSP are the nearest case. It happened there. > Someone correct me if I am wrong, but Xilinx and Altera have NO $5-digit > tools (unless you are counting the pennies). The expensive tools are > the synthesis and simulation tools. I was talking of those. > These are third party and they > charge so much because they are so good. And all the better for their makers, an for those users (their customers), that can convert such tools into the profit that can pay for them. They prove my point: vendor tools will not die (that was your claim) just because open source tools appear and reduce user count of vendor tools. Vendor tools can survive in that market. > But this is the first place > that open-source tools should show up. Why? Those that can pay have no needs. They are satified (nice for them). Those that can not pay have needs. Those that want open stuff have needs. And those that are unsatisfied are those that will experiment with new stuff, and accept the costs of working with untried stuff. > All the interfaces are defined > in public standards, the functionality is known, all that is needed is > the open source code. So where is it??? Where are the open source > synthesizers and simulators? You are forgetting the most important part of open source: motivation. It takes a lot of it. To accept sacrifice of the time to make software without pay. That motivation must come from somewhere. Look for the "somewheres" if you want to know where to look for the first appearances. > they are much more like the gcc target. But the back end tools are very > different. *That* is why there are no third party back end tool > vendors. They are software, like all other. I.e. designs to be specced, lines of implementing program code to be written, work time to be spent. That process is well understood. > > > FPGA tools > > > are a moving target and very different from software development tools. > > > Every new generation of FPGAs require very different software. > > > > So did every generation of CPUs in the days when every generation had > > an new instruction set. Today it is less work, because we have binary > > compatibility and improvement goes into making the existing "bitfiles" > > (read: binary applications) move faster. > > As soon as the x86 came out (~1981, IIRC) the basic instruction set was > cast in concrete. About 5 years later compilers matured and by 1991 > they had become commodities. 8086 was 1977 or 78, 8088 one year later. 386 was an massive update, nearly a new architecture, around 1984. Neither were particularly compiler friendly. But I expect 5 years "catch up" to be realistic for FPGA tools. > > I expect FPGAs will have to go the same route: mass market with binary > > compatibility, cloners[2], etc and an more diversifed "specialist" market > > where everything goes, for max performance, at high price. > > Patents will stop cloners. There is no market force driving FPGAs in > this direction, just as there is no market force driving all CPU makers > to adopt a common instruction set. Huh? I never said "all" CPUs, nor did I say all FPGAs. I clearly stated 2 markets, "mass" and "specialist". > > The Virtex vs Spartan split already points in that direction. Think of > > an non-compatible max-power series of Virtex-II, -III, -IV, -V and an > > Virtex(-I) compatible staying low cost line of Spartan-II, -IIE, -IIEM, > > -IIX, -II? as an possible future. > > I'm not sure what you mean by this. Are you talking about a competitor > chip? Xilinx won't let that happen... No I was pointing out an possible development path for Xilinx. If binary compatible becomes important, they can play with it. You claimed that binary incompatible is neccessary, and as such will break tools, I pointed out that binary compatibility is possible in this market, just as it turned out to be in CPUs, and sketched what its result could look like. > > [2] Think of the next Clearpath with the same size relationship to Altera > > or Xilinx that AMD has to Intel. And aiming for full pin and bit compatible > > SRAM based chips (not mask based specials). Drop in replacement, like an > > AMD K6 (what I am typing this on) fitting an Pentium I socket. And an > > power/price race ensuing, fought on process technology and feature. > > I think you mean Clearlogic... and they have gone the way of the dodo > bird because of infringement issues. And those were infringment on the software licenses on the Altera devel tools used to make the bitstreams that 100% of all their customers would be sending them. It is interesting that Altera did not chose the direct course of attacking them with their patents on the actual chip technology. That they needed to use such an indirect method of helping users breach the the devel tools software license, which is less likely to succeed in court, is telling us a lot. > AMD could make parts that fit the Pentium socket because they had a > license for that. After Socket 7 (IIRC) they no longer had that license > and they now have to make their own interfaces. Socket 7 did not require any license. It is only with Slot 1 and later Socket 370 that Intel introduced an patented signalling protocol (not pinout) which required an license that they then refused to AMD. The pinout is copyable, but useless it one can implement the signalling. > No FPGA company is > going to let a startup copy their technology. No copying the technology is needed. Just making something compatible with the bitstreams. May not happen, may well happen. But it sould be kept in mind as something that could happen in an future bit-compatible market. > > The "magnet" is a running bitstream, and the shortest path to that is > > interesting. So the action starts at the back end. > > So you want to do the hardest part first, show the least result and have > your work obsoleted most rapidly? Also known as: do the most/first needed part first, show an actually usable result, and accept that obsolence will happen and require an "chase the moving target" attitude. gcc did/does this (different CPUs), Linux did/does this (different computer architectures). Sure. > > I started coding 2.5 months ago. I expect to arrive at 2nd milestone > > > > [3] http://neil.franklin.ch/Projects/VirtexTools/ > > I looked at your page and I do not see where you are headed. See the "2.5 months" (should have been 3.5, oops) remark? > Once you > have built all the parts of the intended toolchain, what will the flow > be? Tentatively (subject to changes while implementing): Users chosen language -> compiler (3rd party, multiple) -> design reduced to LUT-sized elements, relative placed, their connections reduced design -> vas (from my toolset) -> design fitted to LUTs/F5s/etc, absolute placed, connections to PIP lists placed/routed design -> vm and libvirtex it calls (from my toolset) -> .bit file to be used or displayed/debugged (using existing vd and vv) -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### Message-ID: <3DA822A0.83F78F6B@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> <3da42e14$0$12760$afc38c87@news.optusnet.com.au> <3DA45599.E098230E@andraka.com> <3da79b0d$0$23169$afc38c87@news.optusnet.com.au> <3DA7A3EF.6105238B@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 28 Date: Sat, 12 Oct 2002 13:25:21 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034429121 68.15.41.165 (Sat, 12 Oct 2002 09:25:21 EDT) NNTP-Posting-Date: Sat, 12 Oct 2002 09:25:21 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21943 There are 4 edifs (components created separately and instantiated as black boxes to speed up synthesis), 10.6 MB, 1.4MB, 128kB and 12.9MB Tim wrote: > Ray Andraka wrote > > The whole thing compiles in about 6 hours on an 800 MHz P3 with 1GB > > memory with lots of paging under 4.2i with NT. Gets a memory conflict > > under win2K while reading the .ncd, which is just over 100MB. > > How big was the EDIF? > > I hate the binary format. Searching through text is not for fun, but > with a binary file you are up the river without a paddle if something > goes wrong. -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3DA86DE2.838D0303@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 351 Date: Sat, 12 Oct 2002 18:46:26 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034448386 68.15.41.165 (Sat, 12 Oct 2002 14:46:26 EDT) NNTP-Posting-Date: Sat, 12 Oct 2002 14:46:26 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!news-hog.berkeley.edu!ucberkeley!newshub.sdsu.edu!west.cox.net!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21940 The hooks for third party development of open source are already available for xilinx via jbits and XDL for those that are inclined to write their own mapping, place and route tools. I don't think you really need source that is any more open than that to make it possible for people to develop their own tool set. Still, there is precious little visible as 3rd party stuff goes here. Probably has a lot to do with the much smaller user base FPGAs have vs CPUs and the much harder task that map, place and route is compared with compiling code to a CPU. The point is the FPGA software is open enough for you to insert your tools at any point in the chain except the final bitstream generation. That is plenty of lattitude to spin your own tools for any of the hard parts, should you be up to the challenge and have nothing better to do with your time. Settling on a standard bitstream is also not likely to happen, as the bitstream is much more dependent on the hardware than is an instruction set for a CPU. The bitstream generally controls some pretty low level switches in the cells, so cell architecture is going to directly influence the bitstream. It has to be this way in order to keep the bitstream length manageable...every extra bit of encoding or recoding is duplicated thousands of times on the chip. As hardware features come in and out of fashion, the bitstreams have to change to accommodate the evolution of the hardware. That evolution is going to be driven by individual innovations by different companies, and since this is not a government effort, the companies will want to keep the rights to their innovations. With a CPU, the cost of recoding an instruction for compatibility is not huge since the instruction unit is not duplicated all over the place, plus the instruction set is very limited. With an FPGA, the 'instruction set' is essentially the bit stream, which I suppose could be broken into smaller kernels but still it is orders of magnitude larger than a CPU instruction set. Neil Franklin wrote: > rickman writes: > > > Neil Franklin wrote: > > > > > > Given that they can not[1] stop open source tools, they are going to have > > > to learn to live with them when they arrive (which is just a question > > > of time, nothing else). They can only delay them by not helping (which > > > they will not help, also for liability and support cost reasons, which > > > I fully agree with them). > > > > They can not in the sense of copyright infringement or patent issues > > perhaps. > > That is the only "stop dead" type of stopping. And so the only deadly > one to open source developers. And so the only one that I mind. > > Technical problems we can handle. An buch of armed law enforcers > saying "stop or we arrest you (or kill if you resist) for daring > our rulers" we can not. > > > But if they don't have the inside scoop on the chips, they > > will have a long row to hoe. > > That is not "stop dead", just delay. Better late than never. A lot better. > > > That brings us back to one of my points. > > The open source tools will *never* be up to date. The chip cycle is > > just too short for a bunch of freeware guys to keep up with. > > Xilinx still sells XC4000/Spartan. After that came XC4000XL/Spartan-XL, > then Virtex/Spartan-II, then Virtex-E/Spartan-IIE, then Virtex-II, now > Virtex-IIpro. > > That makes 6 families being sold in parallel. Actually 3 large families, > with each 2 subfamilies. Looks like an active sales life of about 10 > years for one particular family. > > So any tool supporting Virtex/Spartan-II in say 1-2 years, and extendable > to Virtex-E/Spartan-IIE, has at least an 5 year market life in it. > Reverse-engineering Virtex-II should not take 5 years, so we can keep up... > > > who say it is inevitable. But we never see the tools... > > You can now see an actual project, started, that has an planned out > path leading to tools. > > > > When my tools arrive, it is going to be Xilinx that profits (because I > > > started from JBits out). And any extra chip they sell because of them > > > will be the best "thanks" (dollars, not words) I can give them for > > > enabling my stuff. > > > > And when can we expect this tool? > > First minimal stuff in estimated 1 years time, decently usable in 2 > years, is my current estimate. > > > What devices will it support? > > Initially Virtex/Spartan-II (what JBits does), later Virtex-E/Spartan-IIE. > > > What > > will be *better* about it than the tools already in use? > > All that in open source is better: > > - simple download/compile/install/use, any computer/OS native > - no licensing, can give copy to anyone. allows "config&compile at > customers site" designs, and yes, that includes "customer selects > modules and generates bitstream that runs them" style adaption to > modular interface hardware (see recompiling Linux kernel as an example) > - bugs can be fixed by anyone, or more likey have already got fixed > before you ever hit them, even OpenBSD style code audits go > - guaranteed to remain available (because user-adaptable to new > systems ad infinitum), no forced upgrade cycle > - anyone can add their brains to development, wherever they have the > expertise (compare the open process of science vs pronouncements > from high from any closed governing body) > > For such features many (including myself) are willing to sacrifice > using the latest chip family for the time needed to reverse-engineer, > dito also not wringing the last drop of power out of an chip. > > > > And in the embedded market (more similar to FPGAs than desktop PCs > > > are) we see 8051s from various cloners (with different feature sets) > > > and official Intel tools vs open source ones. > > > > This has also been discussed before. Compilers have become commodity > > items where one is about as good as another for 99% of the work done > > with them. FPGA software is still in the stage of being very highly > > tuned to the chip else it is of little value. > > FPGAs are newer than CPUs, they are bound to be at an earlier stage in > the normal industrial process from novelty to mature technology. > > Screws from one manufacturer once did not fit nuts from an other, > about 120 years ago, due to everyone using their own threads. Once the > basic issues and design space in thread design were explored, standards > came. > > > If you are doing simple > > designs in uncrowded chips then you don't care what tools you use, but > > most FPGA users push their designs if not initially, they do when being > > upgraded in the field. They need tools that work very well with their > > chip. > > How many today forgo the ultimate performance of FPGA Editor in favor > of the simpler life with VHDL or Verilog? > > How many forgo the power increases of floorplanning for less work? > > How many are going to soon start using things like Handel-C because > programmer time costs more than chip space (in small series work)? > > There exist "ultimate power" users, and they will demand "ultimate > power" tools (and pay for them). There also exist less demanding users > who will put up with an less powerfull tools if they offer them an > better deal for their particular circumstances. > > It is horses for courses. > > > > I expect an similar open/wide/basic vs vendor/power/complex split in > > > FPGA tools. And yes, at the prices of top end FPGA tools (5-digit-$), > > > and the cost structure of their paying customers, they should be able > > > to do this. > > > > You can expect what you want, but that won't make it happen. There are > > very few engineers that are going to start a significant project with > > open source FPGA tools when their company will pay for the commercial > > tools. > > Some companies can expect an >5-digit profit increase from 5-digit > tools. They will stay with them (stupid if they did not). Others can > not expect such added profits, they already today do not afford them > (they are those that today demand free Webpack&so on). > > > You make a lot of predictions that won't be tested for 10 years > > or more. > > Anyone planning on shaping the future has to make predictions. The > best we can do is look for similar cases. CPUs, in particular > embedded/DSP are the nearest case. It happened there. > > > Someone correct me if I am wrong, but Xilinx and Altera have NO $5-digit > > tools (unless you are counting the pennies). The expensive tools are > > the synthesis and simulation tools. > > I was talking of those. > > > These are third party and they > > charge so much because they are so good. > > And all the better for their makers, an for those users (their > customers), that can convert such tools into the profit that can pay > for them. > > They prove my point: vendor tools will not die (that was your claim) > just because open source tools appear and reduce user count of vendor > tools. Vendor tools can survive in that market. > > > But this is the first place > > that open-source tools should show up. > > Why? Those that can pay have no needs. They are satified (nice for them). > > Those that can not pay have needs. Those that want open stuff have > needs. And those that are unsatisfied are those that will experiment > with new stuff, and accept the costs of working with untried stuff. > > > All the interfaces are defined > > in public standards, the functionality is known, all that is needed is > > the open source code. So where is it??? Where are the open source > > synthesizers and simulators? > > You are forgetting the most important part of open source: motivation. > It takes a lot of it. To accept sacrifice of the time to make software > without pay. That motivation must come from somewhere. Look for the > "somewheres" if you want to know where to look for the first appearances. > > > they are much more like the gcc target. But the back end tools are very > > different. *That* is why there are no third party back end tool > > vendors. > > They are software, like all other. I.e. designs to be specced, lines > of implementing program code to be written, work time to be spent. > That process is well understood. > > > > > FPGA tools > > > > are a moving target and very different from software development tools. > > > > Every new generation of FPGAs require very different software. > > > > > > So did every generation of CPUs in the days when every generation had > > > an new instruction set. Today it is less work, because we have binary > > > compatibility and improvement goes into making the existing "bitfiles" > > > (read: binary applications) move faster. > > > > As soon as the x86 came out (~1981, IIRC) the basic instruction set was > > cast in concrete. About 5 years later compilers matured and by 1991 > > they had become commodities. > > 8086 was 1977 or 78, 8088 one year later. 386 was an massive update, > nearly a new architecture, around 1984. Neither were particularly > compiler friendly. > > But I expect 5 years "catch up" to be realistic for FPGA tools. > > > > I expect FPGAs will have to go the same route: mass market with binary > > > compatibility, cloners[2], etc and an more diversifed "specialist" market > > > where everything goes, for max performance, at high price. > > > > Patents will stop cloners. There is no market force driving FPGAs in > > this direction, just as there is no market force driving all CPU makers > > to adopt a common instruction set. > > Huh? I never said "all" CPUs, nor did I say all FPGAs. I clearly > stated 2 markets, "mass" and "specialist". > > > > The Virtex vs Spartan split already points in that direction. Think of > > > an non-compatible max-power series of Virtex-II, -III, -IV, -V and an > > > Virtex(-I) compatible staying low cost line of Spartan-II, -IIE, -IIEM, > > > -IIX, -II? as an possible future. > > > > I'm not sure what you mean by this. Are you talking about a competitor > > chip? Xilinx won't let that happen... > > No I was pointing out an possible development path for Xilinx. If > binary compatible becomes important, they can play with it. > > You claimed that binary incompatible is neccessary, and as such will > break tools, I pointed out that binary compatibility is possible in this > market, just as it turned out to be in CPUs, and sketched what its > result could look like. > > > > [2] Think of the next Clearpath with the same size relationship to Altera > > > or Xilinx that AMD has to Intel. And aiming for full pin and bit compatible > > > SRAM based chips (not mask based specials). Drop in replacement, like an > > > AMD K6 (what I am typing this on) fitting an Pentium I socket. And an > > > power/price race ensuing, fought on process technology and feature. > > > > I think you mean Clearlogic... and they have gone the way of the dodo > > bird because of infringement issues. > > And those were infringment on the software licenses on the Altera > devel tools used to make the bitstreams that 100% of all their > customers would be sending them. > > It is interesting that Altera did not chose the direct course of > attacking them with their patents on the actual chip technology. That > they needed to use such an indirect method of helping users breach the > the devel tools software license, which is less likely to succeed in > court, is telling us a lot. > > > AMD could make parts that fit the Pentium socket because they had a > > license for that. After Socket 7 (IIRC) they no longer had that license > > and they now have to make their own interfaces. > > Socket 7 did not require any license. It is only with Slot 1 and later > Socket 370 that Intel introduced an patented signalling protocol (not > pinout) which required an license that they then refused to AMD. The > pinout is copyable, but useless it one can implement the signalling. > > > No FPGA company is > > going to let a startup copy their technology. > > No copying the technology is needed. Just making something compatible > with the bitstreams. May not happen, may well happen. But it sould be > kept in mind as something that could happen in an future bit-compatible > market. > > > > The "magnet" is a running bitstream, and the shortest path to that is > > > interesting. So the action starts at the back end. > > > > So you want to do the hardest part first, show the least result and have > > your work obsoleted most rapidly? > > Also known as: do the most/first needed part first, show an actually > usable result, and accept that obsolence will happen and require an > "chase the moving target" attitude. gcc did/does this (different CPUs), > Linux did/does this (different computer architectures). Sure. > > > > I started coding 2.5 months ago. I expect to arrive at 2nd milestone > > > > > > [3] http://neil.franklin.ch/Projects/VirtexTools/ > > > > I looked at your page and I do not see where you are headed. > > See the "2.5 months" (should have been 3.5, oops) remark? > > > Once you > > have built all the parts of the intended toolchain, what will the flow > > be? > > Tentatively (subject to changes while implementing): > > Users chosen language -> compiler (3rd party, multiple) > -> design reduced to LUT-sized elements, relative placed, their connections > reduced design -> vas (from my toolset) > -> design fitted to LUTs/F5s/etc, absolute placed, connections to PIP lists > placed/routed design -> vm and libvirtex it calls (from my toolset) > -> .bit file to be used or displayed/debugged (using existing vd and vv) > > -- > Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ > Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer > - hardware runs the world, software controls the hardware > code generates the software, have you coded today? -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Mon, 14 Oct 2002 00:41:48 -0400 Organization: Arius, Inc Lines: 88 Message-ID: <3DAA4B0C.EEC162EF@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <3DA63608.C5A58E9E@iprimus.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZff01rVK4tzOZAfKrYDO74+7b43cil79+4nQ6ZWW/ekVkQXo2ZVBg2 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 14 Oct 2002 04:41:21 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21971 Russell wrote: > > rickman wrote: > > However there is *nothing* to adapt to. There are *no* open source > > tools that can be used on a production design. > > Linux and open source are only fairly new, and there's a certain > learning curve before capable developers appear for more specialized > tool development. Also, before jbits, creating open source tools is > completely uninteresting if all it involves is making a pretty front-end. The front end doesn't have to be the *only* part, but it makes sense to me that it should be the *first* part. The backend tool is of no value without a frontend tool. Right now you can get by without an open source backend because you can use the only *good* backend tool available which just happens to be available for free. To start with building the backend tool, you would need a good front end tool. You could use the one from Xilinx, but I hear a lot of complaints about it and that is where a lot of improvements can be made with much less effort. The front end tools have a lot more in common with current compiler technology. Maybe I am wrong, and I am not planning to help with any of this. So if you no playah da game, you no makeah dah rules. So I will butt out. > > You can expect what you want, but that won't make it happen. There are > > very few engineers that are going to start a significant project with > > open source FPGA tools when their company will pay for the commercial > > tools. You make a lot of predictions that won't be tested for 10 years > > or more. > > I would start with an open source tool if there was one at the time. I'd > also be doing bug fixes and adding *useful* features (i'm not quite up > to that level on linux yet). I would submit that you would start with an open source tool not because that would be the best for your project, but because that is what interests you. The engineers that use these tools need to get design work done and don't have time to improve the tools. > > Someone correct me if I am wrong, but Xilinx and Altera have NO $5-digit > > tools (unless you are counting the pennies). The expensive tools are > > the synthesis and simulation tools. These are third party and they > > charge so much because they are so good. > > Leonardo-spectrum GUI good? Most of the other tools could be improved > too. I don't give a rat's ass about the GUI. I care about how well a tool works to give me usable gates. I also have never used Leonardo-spectrum. The tools I have used may have warts, but I could get my work done with them. That is what I care about. > > But this is the first place > > that open-source tools should show up. All the interfaces are defined > > in public standards, the functionality is known, all that is needed is > > the open source code. So where is it??? Where are the open source > > synthesizers and simulators? > > There's no motivation to do it if there's no info available for the > low-level control of most fpgas. It would be like doing open source > development if the only compilers available had to be bought from > microsoft. The opcodes and assembly instructions of microprocessors > are freely released by cpu vendors to encourage tool creation. The > same should apply to fpgas. FPGAs have a short life cycle because > the industry is immature. Process limits will slow this down in a > few years, when open-source will be much more common-place. I don't know what motovates you, but I don't think it is the same as most users of the tools. I would like to stop working with analogies and hear what the game plan is. Can you give us a roadmap of how you would procede? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Mon, 14 Oct 2002 00:57:44 -0400 Organization: Arius, Inc Lines: 27 Message-ID: <3DAA4EC8.CD1E09E4@yahoo.com> References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> <3da42e14$0$12760$afc38c87@news.optusnet.com.au> <3da79b35$0$23169$afc38c87@news.optusnet.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbZ3tHFKZf7Pwo25a5XSZoBwYEpdx8kwdsfZCX9gqWCLQ8TapraM1vp X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 14 Oct 2002 04:57:13 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21970 hamish@cloud.net.au wrote: > > Uwe Bonnes wrote: > > hamish@cloud.net.au wrote: > > : Still waiting for v5.1 to arrive. Upgrading all machines to Win2000 in > > : anticipation. > > > > For a start, use the free downloadable Webpack, which is based on 5.1. > > Does it do 2V6000s? I'd guess not! Does that really matter? Do you really expect to be targeting a part in a week or two? You can do a lot of work under Webpack before you have to do P&R. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Mon, 14 Oct 2002 01:34:58 -0400 Organization: Arius, Inc Lines: 414 Message-ID: <3DAA5782.D3869B5@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVboCe2CKO5cREvqGKQqSU7a2LNiNWDtjs9Gfw07SGXWsqXqUbe+YGGc X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 14 Oct 2002 05:34:45 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21995 Neil Franklin wrote: > > rickman writes: > > That brings us back to one of my points. > > The open source tools will *never* be up to date. The chip cycle is > > just too short for a bunch of freeware guys to keep up with. > > Xilinx still sells XC4000/Spartan. After that came XC4000XL/Spartan-XL, > then Virtex/Spartan-II, then Virtex-E/Spartan-IIE, then Virtex-II, now > Virtex-IIpro. > > That makes 6 families being sold in parallel. Actually 3 large families, > with each 2 subfamilies. Looks like an active sales life of about 10 > years for one particular family. > > So any tool supporting Virtex/Spartan-II in say 1-2 years, and extendable > to Virtex-E/Spartan-IIE, has at least an 5 year market life in it. > Reverse-engineering Virtex-II should not take 5 years, so we can keep up... You are working from the wrong end. No one cares about what tools will support a chip after it has been on the market after 2 years. By that point all the *major* new designs that are going to be done with it *have* been done and every thing else is maintenance. At that point the *new* designs will be on the *new* parts which the open source tool will not support. So if you want to be guaranteed to be behind the cutting edge, then by all means use tools that are perpetually out of date. > > who say it is inevitable. But we never see the tools... > > You can now see an actual project, started, that has an planned out > path leading to tools. I did check out the web site and I am not clear about where it is going. Can you explain in terms that an FPGA engineer can understand? > > > When my tools arrive, it is going to be Xilinx that profits (because I > > > started from JBits out). And any extra chip they sell because of them > > > will be the best "thanks" (dollars, not words) I can give them for > > > enabling my stuff. > > > > And when can we expect this tool? > > First minimal stuff in estimated 1 years time, decently usable in 2 > years, is my current estimate. > > > What devices will it support? > > Initially Virtex/Spartan-II (what JBits does), later Virtex-E/Spartan-IIE. > > > What > > will be *better* about it than the tools already in use? > > All that in open source is better: > > - simple download/compile/install/use, any computer/OS native don't care, I only use one OS and that will be what the tool is compatible with. I'm an FPGA engineer, not a SW engineer. > - no licensing, can give copy to anyone. allows "config&compile at > customers site" designs, and yes, that includes "customer selects > modules and generates bitstream that runs them" style adaption to > modular interface hardware (see recompiling Linux kernel as an example) don't care. X and A both give away tools and the paid for versions are affordable in the context of running a business. > - bugs can be fixed by anyone, or more likey have already got fixed > before you ever hit them, even OpenBSD style code audits go If that is true, then that will be a plus. X and A tools have quite a few bugs in them and they never really get fixed, they are just substituted for other ones. > - guaranteed to remain available (because user-adaptable to new > systems ad infinitum), no forced upgrade cycle No one forces you to upgrade. Many engineers stay with a given version all the way through a design or several designs. Just read here about Xilinx 5.1. Many are choosing to stay with 4.x for now. > - anyone can add their brains to development, wherever they have the > expertise (compare the open process of science vs pronouncements > from high from any closed governing body) don't care. I want tools to use to do work, not tools I can work on. > For such features many (including myself) are willing to sacrifice > using the latest chip family for the time needed to reverse-engineer, > dito also not wringing the last drop of power out of an chip. Many does not include the majority of FPGA engineers, IMHO. In the FPGA world you have to work with the best chip for the job and that is often the most current chip. > > > And in the embedded market (more similar to FPGAs than desktop PCs > > > are) we see 8051s from various cloners (with different feature sets) > > > and official Intel tools vs open source ones. > > > > This has also been discussed before. Compilers have become commodity > > items where one is about as good as another for 99% of the work done > > with them. FPGA software is still in the stage of being very highly > > tuned to the chip else it is of little value. > > FPGAs are newer than CPUs, they are bound to be at an earlier stage in > the normal industrial process from novelty to mature technology. I don't know how this is relevant. You are carrying an analogy outside of its usefulness. > Screws from one manufacturer once did not fit nuts from an other, > about 120 years ago, due to everyone using their own threads. Once the > basic issues and design space in thread design were explored, standards > came. Bad analogy. It was in the best interest of the dozens or hundreds of manufacturer's interests to be compatible. Just as chip vendors have to work with the same power supply voltages and signal levels. But X and A have no reason to use the same tools. Ask them, they will tell you... It is a competitive advantage for them to have their own tools so they can be better than the competition's. > > If you are doing simple > > designs in uncrowded chips then you don't care what tools you use, but > > most FPGA users push their designs if not initially, they do when being > > upgraded in the field. They need tools that work very well with their > > chip. > > How many today forgo the ultimate performance of FPGA Editor in favor > of the simpler life with VHDL or Verilog? > > How many forgo the power increases of floorplanning for less work? > > How many are going to soon start using things like Handel-C because > programmer time costs more than chip space (in small series work)? > > There exist "ultimate power" users, and they will demand "ultimate > power" tools (and pay for them). There also exist less demanding users > who will put up with an less powerfull tools if they offer them an > better deal for their particular circumstances. > > It is horses for courses. Not sure what that means, but I have seen $1000 FPGAs go on a board. If they had known that they would need a $2000 chip, the board would have never been designed. Tools are important and good tools are essential. > > > I expect an similar open/wide/basic vs vendor/power/complex split in > > > FPGA tools. And yes, at the prices of top end FPGA tools (5-digit-$), > > > and the cost structure of their paying customers, they should be able > > > to do this. > > > > You can expect what you want, but that won't make it happen. There are > > very few engineers that are going to start a significant project with > > open source FPGA tools when their company will pay for the commercial > > tools. > > Some companies can expect an >5-digit profit increase from 5-digit > tools. They will stay with them (stupid if they did not). Others can > not expect such added profits, they already today do not afford them > (they are those that today demand free Webpack&so on). So? Few if any significant companies can't afford the low end tools that will get the job done. Not all tools are 5 figure. In fact very few are. What is your point? > > You make a lot of predictions that won't be tested for 10 years > > or more. > > Anyone planning on shaping the future has to make predictions. The > best we can do is look for similar cases. CPUs, in particular > embedded/DSP are the nearest case. It happened there. When it happens with FPGAs I will be happy to use the new tools... but I expect to be retired by then. :) > > Someone correct me if I am wrong, but Xilinx and Altera have NO $5-digit > > tools (unless you are counting the pennies). The expensive tools are > > the synthesis and simulation tools. > > I was talking of those. And you can live a rich full life without the $10,000+ tools. Right? > > These are third party and they > > charge so much because they are so good. > > And all the better for their makers, an for those users (their > customers), that can convert such tools into the profit that can pay > for them. > > They prove my point: vendor tools will not die (that was your claim) > just because open source tools appear and reduce user count of vendor > tools. Vendor tools can survive in that market. I am not talking about Synthesis and Simulation. I am talking about the back end tools. If Xilinx loses > 50% of its tool market to open source or third party tools, I expect they will drop their inhouse tools. They would have to either cut their tool staff by half which would ruin their tools in the future or start charging more for the chips to make up the differernce which would make it harder for them to compete. So sucessful open source tools will drive FPGA vendors out of the tool market. Then they would have to compete on just the chips and be a driving force somehow with the tools. > > But this is the first place > > that open-source tools should show up. > > Why? Those that can pay have no needs. They are satified (nice for them). > > Those that can not pay have needs. Those that want open stuff have > needs. And those that are unsatisfied are those that will experiment > with new stuff, and accept the costs of working with untried stuff. > > All the interfaces are defined > > in public standards, the functionality is known, all that is needed is > > the open source code. So where is it??? Where are the open source > > synthesizers and simulators? > > You are forgetting the most important part of open source: motivation. > It takes a lot of it. To accept sacrifice of the time to make software > without pay. That motivation must come from somewhere. Look for the > "somewheres" if you want to know where to look for the first appearances. Why would anyone be more motivated to develop backend tools? What is their value without the front end tools? > > they are much more like the gcc target. But the back end tools are very > > different. *That* is why there are no third party back end tool > > vendors. > > They are software, like all other. I.e. designs to be specced, lines > of implementing program code to be written, work time to be spent. > That process is well understood. I am glad that you think *all* software is the same. Technology is a matter of solving problems, not writing code. If you don't have good agorithms, you code will be lousy. Writing code is the *easy* part. Developing the algorithm is the hard part. > > > > FPGA tools > > > > are a moving target and very different from software development tools. > > > > Every new generation of FPGAs require very different software. > > > > > > So did every generation of CPUs in the days when every generation had > > > an new instruction set. Today it is less work, because we have binary > > > compatibility and improvement goes into making the existing "bitfiles" > > > (read: binary applications) move faster. > > > > As soon as the x86 came out (~1981, IIRC) the basic instruction set was > > cast in concrete. About 5 years later compilers matured and by 1991 > > they had become commodities. > > 8086 was 1977 or 78, 8088 one year later. 386 was an massive update, > nearly a new architecture, around 1984. Neither were particularly > compiler friendly. > > But I expect 5 years "catch up" to be realistic for FPGA tools. > > > > I expect FPGAs will have to go the same route: mass market with binary > > > compatibility, cloners[2], etc and an more diversifed "specialist" market > > > where everything goes, for max performance, at high price. > > > > Patents will stop cloners. There is no market force driving FPGAs in > > this direction, just as there is no market force driving all CPU makers > > to adopt a common instruction set. > > Huh? I never said "all" CPUs, nor did I say all FPGAs. I clearly > stated 2 markets, "mass" and "specialist". What is your point? NO ONE can make a Xilinx compatible FPGA except Xilinx. NO ONE can make an Altera FPGA except Altera... Just ask Clearlogic. :) > > > The Virtex vs Spartan split already points in that direction. Think of > > > an non-compatible max-power series of Virtex-II, -III, -IV, -V and an > > > Virtex(-I) compatible staying low cost line of Spartan-II, -IIE, -IIEM, > > > -IIX, -II? as an possible future. > > > > I'm not sure what you mean by this. Are you talking about a competitor > > chip? Xilinx won't let that happen... > > No I was pointing out an possible development path for Xilinx. If > binary compatible becomes important, they can play with it. > > You claimed that binary incompatible is neccessary, and as such will > break tools, I pointed out that binary compatibility is possible in this > market, just as it turned out to be in CPUs, and sketched what its > result could look like. How is compatibility necessary in CPUs or FPGAs? It only exists in the x86 world because the cat is out of the bag. With other processors, it is not available unless you pay a license fee. Just ask the student who developed the ARM core HDL. Notice you can't get it anymore... > > > [2] Think of the next Clearpath with the same size relationship to Altera > > > or Xilinx that AMD has to Intel. And aiming for full pin and bit compatible > > > SRAM based chips (not mask based specials). Drop in replacement, like an > > > AMD K6 (what I am typing this on) fitting an Pentium I socket. And an > > > power/price race ensuing, fought on process technology and feature. > > > > I think you mean Clearlogic... and they have gone the way of the dodo > > bird because of infringement issues. > > And those were infringment on the software licenses on the Altera > devel tools used to make the bitstreams that 100% of all their > customers would be sending them. > > It is interesting that Altera did not chose the direct course of > attacking them with their patents on the actual chip technology. That > they needed to use such an indirect method of helping users breach the > the devel tools software license, which is less likely to succeed in > court, is telling us a lot. You are talking about making chips, now you are talking about the tools. What are you talking about? THERE WILL BE NO BITSTREAM COMPATIBLE CHIPS!!! > > AMD could make parts that fit the Pentium socket because they had a > > license for that. After Socket 7 (IIRC) they no longer had that license > > and they now have to make their own interfaces. > > Socket 7 did not require any license. It is only with Slot 1 and later > Socket 370 that Intel introduced an patented signalling protocol (not > pinout) which required an license that they then refused to AMD. The > pinout is copyable, but useless it one can implement the signalling. No, you are confused. Socket 7 required a license, but AMD and several other companies already had that license due to manufacturing agreements that Intel had set up previously. They were later interpreted to include the pinout, the instruction set and even the microcode for processors up to the 386. There are *always* licenses. You buy them or you trade for them. But they are always there... > > No FPGA company is > > going to let a startup copy their technology. > > No copying the technology is needed. Just making something compatible > with the bitstreams. May not happen, may well happen. But it sould be > kept in mind as something that could happen in an future bit-compatible > market. Again you are talking tools now when we were talking chips. > > > The "magnet" is a running bitstream, and the shortest path to that is > > > interesting. So the action starts at the back end. > > > > So you want to do the hardest part first, show the least result and have > > your work obsoleted most rapidly? > > Also known as: do the most/first needed part first, show an actually > usable result, and accept that obsolence will happen and require an > "chase the moving target" attitude. gcc did/does this (different CPUs), > Linux did/does this (different computer architectures). Sure. I disagree that the backend is needed most or first. But then it is not my decision to make. > > > I started coding 2.5 months ago. I expect to arrive at 2nd milestone > > > > > > [3] http://neil.franklin.ch/Projects/VirtexTools/ > > > > I looked at your page and I do not see where you are headed. > > See the "2.5 months" (should have been 3.5, oops) remark? > > > Once you > > have built all the parts of the intended toolchain, what will the flow > > be? > > Tentatively (subject to changes while implementing): > > Users chosen language -> compiler (3rd party, multiple) > -> design reduced to LUT-sized elements, relative placed, their connections > reduced design -> vas (from my toolset) > -> design fitted to LUTs/F5s/etc, absolute placed, connections to PIP lists > placed/routed design -> vm and libvirtex it calls (from my toolset) > -> .bit file to be used or displayed/debugged (using existing vd and vv) I don't understand any of this. What are you planning to do? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3DAA6DF8.6BBFDD16@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.10.230 Lines: 82 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Mon, 14 Oct 2002 17:10:48 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034579095 203.134.67.67 (Mon, 14 Oct 2002 03:04:55 EDT) NNTP-Posting-Date: Mon, 14 Oct 2002 03:04:55 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!zen.net.uk!nntp.theplanet.net!inewsm1.nntp.theplanet.net!newspeerenv1.svr.pol.co.uk!newsfeed.wirehub.nl!news-hub.siol.net!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21981 rickman wrote: > > Neil Franklin wrote: > > > You are working from the wrong end. No one cares about what tools will > support a chip after it has been on the market after 2 years. By that > point all the *major* new designs that are going to be done with it > *have* been done and every thing else is maintenance. At that point the > *new* designs will be on the *new* parts which the open source tool will > not support. So if you want to be guaranteed to be behind the cutting > edge, then by all means use tools that are perpetually out of date. Many designs want availability and cheapness instead of cutting edge. With process problems, life cycles will get longer. > > All that in open source is better: > > > > - simple download/compile/install/use, any computer/OS native > > don't care, I only use one OS and that will be what the tool is > compatible with. I'm an FPGA engineer, not a SW engineer. Irrelevant. > > - no licensing, can give copy to anyone. allows "config&compile at > > customers site" designs, and yes, that includes "customer selects > > modules and generates bitstream that runs them" style adaption to > > modular interface hardware (see recompiling Linux kernel as an example) > > don't care. X and A both give away tools and the paid for versions are > affordable in the context of running a business. Irrelevant. The tools are broken compared to what a decent open source tool would be like. > > - anyone can add their brains to development, wherever they have the > > expertise (compare the open process of science vs pronouncements > > from high from any closed governing body) > > don't care. I want tools to use to do work, not tools I can work on. Irrelevant. The tools are broken compared to what a decent open source tool would be like. > > For such features many (including myself) are willing to sacrifice > > using the latest chip family for the time needed to reverse-engineer, > > dito also not wringing the last drop of power out of an chip. > > Many does not include the majority of FPGA engineers, IMHO. In the FPGA > world you have to work with the best chip for the job and that is often > the most current chip. Rarely. The biggest latest chips have the highest profile. > > They prove my point: vendor tools will not die (that was your claim) > > just because open source tools appear and reduce user count of vendor > > tools. Vendor tools can survive in that market. > > I am not talking about Synthesis and Simulation. I am talking about the > back end tools. If Xilinx loses > 50% of its tool market to open source > or third party tools, I expect they will drop their inhouse tools. They > would have to either cut their tool staff by half which would ruin their > tools in the future or start charging more for the chips to make up the > differernce which would make it harder for them to compete. So > sucessful open source tools will drive FPGA vendors out of the tool > market. Then they would have to compete on just the chips and be a > driving force somehow with the tools. No. Internal tools can be fixed in short time if companies have a 4 digit support contract, which many will. > > You are forgetting the most important part of open source: motivation. > > It takes a lot of it. To accept sacrifice of the time to make software > > without pay. That motivation must come from somewhere. Look for the > > "somewheres" if you want to know where to look for the first appearances. > > Why would anyone be more motivated to develop backend tools? What is > their value without the front end tools? Without free chip information to make backend tools, frontend tools are useless. Compilers and fitters are fun to make. GUIs are boring. ###### Message-ID: <3DAA7156.4DF4C1B9@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <3DA63608.C5A58E9E@iprimus.com.au> <3DAA4B0C.EEC162EF@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.118.158 Lines: 92 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Mon, 14 Oct 2002 17:25:10 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034579960 203.134.67.67 (Mon, 14 Oct 2002 03:19:20 EDT) NNTP-Posting-Date: Mon, 14 Oct 2002 03:19:20 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!cox.net!nntp2.aus1.giganews.com!border1.nntp.aus1.giganews.com!nntp.giganews.com!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21980 rickman wrote: > > Russell wrote: > > > > rickman wrote: > > > However there is *nothing* to adapt to. There are *no* open source > > > tools that can be used on a production design. > > > > Linux and open source are only fairly new, and there's a certain > > learning curve before capable developers appear for more specialized > > tool development. Also, before jbits, creating open source tools is > > completely uninteresting if all it involves is making a pretty front-end. > > The front end doesn't have to be the *only* part, but it makes sense to > me that it should be the *first* part. The backend tool is of no value > without a frontend tool. Right now you can get by without an open > source backend because you can use the only *good* backend tool > available which just happens to be available for free. To start with > building the backend tool, you would need a good front end tool. You > could use the one from Xilinx, but I hear a lot of complaints about it > and that is where a lot of improvements can be made with much less > effort. The front end tools have a lot more in common with current > compiler technology. > > Maybe I am wrong, and I am not planning to help with any of this. So if > you no playah da game, you no makeah dah rules. So I will butt out. > > > > You can expect what you want, but that won't make it happen. There are > > > very few engineers that are going to start a significant project with > > > open source FPGA tools when their company will pay for the commercial > > > tools. You make a lot of predictions that won't be tested for 10 years > > > or more. > > > > I would start with an open source tool if there was one at the time. I'd > > also be doing bug fixes and adding *useful* features (i'm not quite up > > to that level on linux yet). > > I would submit that you would start with an open source tool not because > that would be the best for your project, but because that is what > interests you. The engineers that use these tools need to get design > work done and don't have time to improve the tools. > > > > Someone correct me if I am wrong, but Xilinx and Altera have NO $5-digit > > > tools (unless you are counting the pennies). The expensive tools are > > > the synthesis and simulation tools. These are third party and they > > > charge so much because they are so good. > > > > Leonardo-spectrum GUI good? Most of the other tools could be improved > > too. > > I don't give a rat's ass about the GUI. I care about how well a tool > works to give me usable gates. I also have never used > Leonardo-spectrum. The tools I have used may have warts, but I could > get my work done with them. That is what I care about. > > > > But this is the first place > > > that open-source tools should show up. All the interfaces are defined > > > in public standards, the functionality is known, all that is needed is > > > the open source code. So where is it??? Where are the open source > > > synthesizers and simulators? > > > > There's no motivation to do it if there's no info available for the > > low-level control of most fpgas. It would be like doing open source > > development if the only compilers available had to be bought from > > microsoft. The opcodes and assembly instructions of microprocessors > > are freely released by cpu vendors to encourage tool creation. The > > same should apply to fpgas. FPGAs have a short life cycle because > > the industry is immature. Process limits will slow this down in a > > few years, when open-source will be much more common-place. > > I don't know what motovates you, but I don't think it is the same as > most users of the tools. I would like to stop working with analogies > and hear what the game plan is. Can you give us a roadmap of how you > would procede? You compile a design a subcircuit at a time in HDL. You manually place all the primitives into a compact area, or let a fitter do it for you with suitable constraints, making an RPM. Repeat for all subcircuits. Place these RPMs into bigger groups of RPMs if needed. Place these 'mega' RPMs. Proceed up the hierarchy until the whole design is done (one big RPM). This is what webpack 5.1i should allow you to do, but i still need to try it. 4.2i was aimed there, but was broken. Naturally, a GUI is involved in the floorplanning stage, and is a suitable technical challenge for an open-source project. The fitter would also be an excellent thing to work on. I once made a pcb autorouter in dos that caused all the tracks to naturally 'coalesce' into parallel paths and minimize track lengths/bends. ###### From: allan_herriman.hates.spam@agilent.com (Allan Herriman) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Mon, 14 Oct 2002 07:47:00 GMT Organization: Agilent Technologies Lines: 25 Message-ID: <3daa753e.11353605@netnews.agilent.com> References: <3da33699$0$194$4d4ebb8e@read.news.de.uu.net> <3da42e14$0$12760$afc38c87@news.optusnet.com.au> <3da79b35$0$23169$afc38c87@news.optusnet.com.au> <3DAA4EC8.CD1E09E4@yahoo.com> NNTP-Posting-Host: cswreg.cos.agilent.com X-Trace: cswtrans.cos.agilent.com 1034581621 31233 130.29.154.45 (14 Oct 2002 07:47:01 GMT) X-Complaints-To: usenet@cswtrans.cos.agilent.com NNTP-Posting-Date: Mon, 14 Oct 2002 07:47:01 +0000 (UTC) X-Newsreader: Forte Free Agent 1.21/32.243 Cache-Post-Path: cswreg.cos.agilent.com!unknown@hpiw0398.aus.agilent.com X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!enews.sgi.com!sdd.hp.com!agilent.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21988 On Mon, 14 Oct 2002 00:57:44 -0400, rickman wrote: >hamish@cloud.net.au wrote: >> >> Uwe Bonnes wrote: >> > hamish@cloud.net.au wrote: >> > : Still waiting for v5.1 to arrive. Upgrading all machines to Win2000 in >> > : anticipation. >> > >> > For a start, use the free downloadable Webpack, which is based on 5.1. >> >> Does it do 2V6000s? I'd guess not! > >Does that really matter? Do you really expect to be targeting a part in >a week or two? You can do a lot of work under Webpack before you have >to do P&R. When you already have XC2V6000 designs working in 4.2, and you want to try them in 5.1, yes, this does matter. It's been a few years since I've done a design that was small enough to allow webpack to be used. YMMV. Allan. ###### Message-ID: <3DAACDBD.498D6B78@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <3DA63608.C5A58E9E@iprimus.com.au> <3DAA4B0C.EEC162EF@yahoo.com> <3DAA7156.4DF4C1B9@iprimus.com.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 44 Date: Mon, 14 Oct 2002 13:59:51 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034603991 68.15.41.165 (Mon, 14 Oct 2002 09:59:51 EDT) NNTP-Posting-Date: Mon, 14 Oct 2002 09:59:51 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!central.cox.net!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21976 This is basically what we already do with the existing tools. We build a set of hierachical RPMs by structural instantiation with RLOCs in the VHDL, and then use them as blocks in bigger RPMs. The tools are reasonable (sure they have warts, but for the most part I can get the job done in a reasonable amount of time without having to go outside the normal flow). There are some extra features that would be nice, but certainly not essential. The weakest part of the existing tools is the floorplanner, so if I were to identify a first hit, it would be a hierarchical floorplanner with a capability to back-annotate to structural source. In any event, the existing tools do support this kind of design flow. Russell wrote: > > You compile a design a subcircuit at a time in HDL. You manually > place all the primitives into a compact area, or let a fitter do > it for you with suitable constraints, making an RPM. > Repeat for all subcircuits. Place these RPMs into bigger > groups of RPMs if needed. Place these 'mega' RPMs. Proceed > up the hierarchy until the whole design is done (one big RPM). > > This is what webpack 5.1i should allow you to do, but > i still need to try it. 4.2i was aimed there, but was > broken. > > Naturally, a GUI is involved in the floorplanning stage, > and is a suitable technical challenge for an open-source > project. The fitter would also be an excellent thing to > work on. I once made a pcb autorouter in dos that caused > all the tracks to naturally 'coalesce' into parallel > paths and minimize track lengths/bends. -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Mon, 14 Oct 2002 15:40:10 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 88 Message-ID: References: <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1034610010 69167 128.32.112.203 (14 Oct 2002 15:40:10 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Mon, 14 Oct 2002 15:40:10 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21985 I mostly agree, but some minor additions. In article <3DAA5782.D3869B5@yahoo.com>, rickman wrote: >Many does not include the majority of FPGA engineers, IMHO. In the FPGA >world you have to work with the best chip for the job and that is often >the most current chip. OR it is the cheapest chip possible, in which case one wants really good quality because of the resource constraints. >> Some companies can expect an >5-digit profit increase from 5-digit >> tools. They will stay with them (stupid if they did not). Others can >> not expect such added profits, they already today do not afford them >> (they are those that today demand free Webpack&so on). > >So? Few if any significant companies can't afford the low end tools >that will get the job done. Not all tools are 5 figure. In fact very >few are. What is your point? Also, lets face it, the NRE time to design just a board to do what you want it to is fairly substantial, let alone the FPGA chip. WHen you are paying the engineers $50k/year, so they cost you $100k/year, you aren't going to blanch at the ~$1000 for the back-end xilinx tools. Even front end tools at $10k are going to be "Will this, over the project lifetime, save you 10% of your time? Yes? Good, here you go." >> You are forgetting the most important part of open source: motivation. >> It takes a lot of it. To accept sacrifice of the time to make software >> without pay. That motivation must come from somewhere. Look for the >> "somewheres" if you want to know where to look for the first appearances. > >Why would anyone be more motivated to develop backend tools? What is >their value without the front end tools? And back end tools are LESS valuable, as they cost less, generally work better, and don't have very many interesting problems anymore. And if you want to do open source synthesis, you don't touch the back-end, you jsut feed it to the Xilinx/Altera P&R flow which have nicely documented interfaces. >I am glad that you think *all* software is the same. Technology is a >matter of solving problems, not writing code. If you don't have good >agorithms, you code will be lousy. Writing code is the *easy* part. >Developing the algorithm is the hard part. Ohh, strongly disagree. Developing the algorthms and proving the concepts in code is the easy part (its prototyping), its turning or recreatingthat code into something robust an widely usable thats hard, IMO. >How is compatibility necessary in CPUs or FPGAs? It only exists in the >x86 world because the cat is out of the bag. With other processors, it >is not available unless you pay a license fee. Just ask the student who >developed the ARM core HDL. Notice you can't get it anymore... Or they made a strategic decision to make it avaiable, because their market doesn't cover small/embedded generally (SPARC). >> Also known as: do the most/first needed part first, show an actually >> usable result, and accept that obsolence will happen and require an >> "chase the moving target" attitude. gcc did/does this (different CPUs), >> Linux did/does this (different computer architectures). Sure. > >I disagree that the backend is needed most or first. But then it is not >my decision to make. I'll second this. Front end tools cost more. Most of the room for improvment is in the front end. Place and route and bitgen and static timing analysis are really just boring crud needed to get the parts to work. {flow munched} >I don't understand any of this. What are you planning to do? Back end tools. Starting with bitgen and working backwards. Oh, where was static timing analysis? -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 14 Oct 2002 21:18:09 +0200 Organization: My own Private Self Lines: 266 Message-ID: <6ubs5wkexa.fsf@chonsp.franklin.ch> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1034623091 997 10.0.3.2 (14 Oct 2002 19:18:11 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 14 Oct 2002 19:18:11 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:21998 rickman writes: > Neil Franklin wrote: > > > > So any tool supporting Virtex/Spartan-II in say 1-2 years, and extendable > > to Virtex-E/Spartan-IIE, has at least an 5 year market life in it. > > Reverse-engineering Virtex-II should not take 5 years, so we can keep up... > > You are working from the wrong end. No one cares about what tools will > support a chip after it has been on the market after 2 years. You may not care about an 2 year old chip. Other "leading edge" people may also take that approach. I care for whatever chip solves my problem. The 2 year old ones do so. > point all the *major* new designs that are going to be done with it > *have* been done and every thing else is maintenance. Makes one wonder why Xilinx re-warmed their over 2 years old Virtex in form of Spartan-II. After already doing the same trick with Spartan, and have since repeated it with Spartan-IIE. Seem to sell, so there seem to be quite a few people who do not need then newest possible. > > You can now see an actual project, started, that has an planned out > > path leading to tools. > > I did check out the web site and I am not clear about where it is > going. Can you explain in terms that an FPGA engineer can understand? I can only say stuff in whatever language I know. Which contains 74xx logic, 8051s, Unix programming in C, shell/perl programming, and doing FPGA in JBits. Sorry if your particular jargon is not supported. > > For such features many (including myself) are willing to sacrifice > > using the latest chip family for the time needed to reverse-engineer, > > dito also not wringing the last drop of power out of an chip. > > Many does not include the majority of FPGA engineers, IMHO. Even if that is majority, there still is the rest. > > Screws from one manufacturer once did not fit nuts from an other, > > about 120 years ago, due to everyone using their own threads. Once the > > basic issues and design space in thread design were explored, standards > > came. > > Bad analogy. It was in the best interest of the dozens or hundreds of > manufacturer's interests to be compatible. Nope. It was in their best interst to lock in customers with incompatible designs. It was users professional societies that forced the change in style. > > It is horses for courses. > > Not sure what that means, It means that what is best for one, is not automatically best for another. And that the anther may be best served with something that the first would never want. > but I have seen $1000 FPGAs go on a board. If > they had known that they would need a $2000 chip, the board would have > never been designed. Absolutely not relevant for me, not for my project sizes. > > > tools (unless you are counting the pennies). The expensive tools are > > > the synthesis and simulation tools. > > > > I was talking of those. > > And you can live a rich full life without the $10,000+ tools. Right? Could you point out, where I am supposed to have claimed contrary to that? I was pointing out, that your "less users, A and X will not bei able to afford development" stuff was nonsense. That there exists people prepared to pay large sums for tools proves that A and X can keep on making tools, by simply rising their price a bit. > I am not talking about Synthesis and Simulation. I am talking about the > back end tools. If Xilinx loses > 50% of its tool market to open source > or third party tools, I expect they will drop their inhouse tools. Or rise their price to 2 times what they are today. Still a lot less than what some people are prepared to pay. > tools in the future or start charging more for the chips to make up the > difference which would make it harder for them to compete. And so what? Their competitors (ASIC vendors) also have to pay for their tool development. Both can then chose how to distribute the costs over software licenses (less larger ones) or chip costs (possibly more sales due to the open source software), or use some of the open source stuff to reduce their costs. May the best win. > sucessful open source tools will drive FPGA vendors out of the tool > market. Then they would have to compete on just the chips and be a CPU manufacturers seem to be living ok, on doing just that. > > You are forgetting the most important part of open source: motivation. > > It takes a lot of it. To accept sacrifice of the time to make software > > without pay. That motivation must come from somewhere. Look for the > > "somewheres" if you want to know where to look for the first appearances. > > Why would anyone be more motivated to develop backend tools? What is > their value without the front end tools? As foundation to build front end tools on? The bitstream is the target. Back end makes that. From there on to the front is ever increasing comfort. > > > they are much more like the gcc target. But the back end tools are very > > > different. *That* is why there are no third party back end tool > > > vendors. > > > > They are software, like all other. I.e. designs to be specced, lines > > of implementing program code to be written, work time to be spent. > > That process is well understood. > > I am glad that you think *all* software is the same. All software in the end boils down to the same: time. Learning, researching, coding, testing are all in the end time. > matter of solving problems, not writing code. If you don't have good > agorithms, you code will be lousy. Writing code is the *easy* part. > Developing the algorithm is the hard part. It is in the end just time. > > Huh? I never said "all" CPUs, nor did I say all FPGAs. I clearly > > stated 2 markets, "mass" and "specialist". > > What is your point? NO ONE can make a Xilinx compatible FPGA except > Xilinx. NO ONE can make an Altera FPGA except Altera... I have my doubts. Where there is a will (enough money) competitors will appear. > Just ask > Clearlogic. :) AFAIK, they did not make FPGAs. They made ASICs that were layouted automatically from Altera bitstreams. And it was not their ASICs that got them into trouble, but rather that every single use of their technology being helping Altera software licensees break the license. So they are not particularly a good example for "cloning not possible". In fact in an hypothetical world with open source (no-Altera) tools, user using them could develop on Altera and then manufacture on Clearlogic, and those would not be violation licences, and so there would be an non-infringing use for Clearlogic -> Altera loses case. > > You claimed that binary incompatible is neccessary, and as such will > > break tools, I pointed out that binary compatibility is possible in this > > market, just as it turned out to be in CPUs, and sketched what its > > result could look like. > > How is compatibility necessary in CPUs or FPGAs? It only exists in the > x86 world because the cat is out of the bag. And who says it will not get out of the bag in the FPGA world? > > It is interesting that Altera did not chose the direct course of > > attacking them with their patents on the actual chip technology. That > > they needed to use such an indirect method of helping users breach the > > the devel tools software license, which is less likely to succeed in > > court, is telling us a lot. > > You are talking about making chips, now you are talking about the > tools. Because the Clearlogic case was about tool missuse, or rather about helping people missuse an tool, and no non-infringing use. > > > AMD could make parts that fit the Pentium socket because they had a > > > license for that. After Socket 7 (IIRC) they no longer had that license > > > and they now have to make their own interfaces. > > > > Socket 7 did not require any license. It is only with Slot 1 and later > > Socket 370 that Intel introduced an patented signalling protocol (not > > pinout) which required an license that they then refused to AMD. The > > pinout is copyable, but useless it one can implement the signalling. > > No, you are confused. Socket 7 required a license, but AMD and several > other companies already had that license due to manufacturing agreements > that Intel had set up previously. They were later interpreted to > include the pinout, the instruction set and even the microcode for > processors up to the 386. AMDs license agreements only went up to 486. Even there they were not complete (the ICE code was not covered). Socket 7 is Pentium, and so not covered by any 486 stuff. Sockets can not be copyrighted, can not be patented, can not be trademarked, so no protection. Signaling protocols can be patented, that is what Intel then did on PentiumII. Same issue that they had with numbers not being trademarkable, so AMD copied the 486 name with impunity. So Intel renamed the becomeing 586 into Pentium, to prevent AMD being able to copy it. > > Also known as: do the most/first needed part first, show an actually > > usable result, and accept that obsolence will happen and require an > > "chase the moving target" attitude. gcc did/does this (different CPUs), > > Linux did/does this (different computer architectures). Sure. > > I disagree that the backend is needed most or first. But then it is not > my decision to make. Exactly. That is my descision. And my knowledge of the open source community that runs into it. > > > Once you > > > have built all the parts of the intended toolchain, what will the flow > > > be? > > > > Tentatively (subject to changes while implementing): > > > > Users chosen language -> compiler (3rd party, multiple) > > -> design reduced to LUT-sized elements, relative placed, their connection s > > reduced design -> vas (from my toolset) > > -> design fitted to LUTs/F5s/etc, absolute placed, connections to PIP list s > > placed/routed design -> vm and libvirtex it calls (from my toolset) > > -> .bit file to be used or displayed/debugged (using existing vd and vv) > > I don't understand any of this. What are you planning to do? If we do not have that much common language to base our discourse on, I might as well give up. Good bye. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 14 Oct 2002 21:27:30 +0200 Organization: My own Private Self Lines: 44 Message-ID: <6u8z10kehp.fsf@chonsp.franklin.ch> References: <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1034623650 997 10.0.3.2 (14 Oct 2002 19:27:30 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 14 Oct 2002 19:27:30 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:21999 nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > rickman wrote: > > >So? Few if any significant companies can't afford the low end tools > >that will get the job done. Not all tools are 5 figure. In fact very > >few are. What is your point? > > WHen you are paying the engineers $50k/year, so they cost you > $100k/year, you aren't going to blanch at the ~$1000 for the back-end > xilinx tools. IF you are in that price range. Sure. I am not. > >I am glad that you think *all* software is the same. Technology is a > >matter of solving problems, not writing code. If you don't have good > >agorithms, you code will be lousy. Writing code is the *easy* part. > >Developing the algorithm is the hard part. > > Ohh, strongly disagree. Developing the algorthms and proving the > concepts in code is the easy part (its prototyping), its turning or > recreatingthat code into something robust an widely usable thats hard, > IMO. So the main 2 critics disagree totally with each other. > {flow munched} > > >I don't understand any of this. What are you planning to do? > > Back end tools. Starting with bitgen and working backwards. > > Oh, where was static timing analysis? Not mentioned in the post, as not part of the question I was answering. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Mon, 14 Oct 2002 15:08:38 -0400 Organization: Arius, Inc Lines: 126 Message-ID: <3DAB1636.3714C61A@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <3DAA6DF8.6BBFDD16@iprimus.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbDqId40/LdymdG7RaZXGYYc2BDKVGOf3vFKauVl0AnTpQ4c9flbvRj X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 14 Oct 2002 19:08:30 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22009 Russell wrote: > > rickman wrote: > > > > Neil Franklin wrote: > > > > > You are working from the wrong end. No one cares about what tools will > > support a chip after it has been on the market after 2 years. By that > > point all the *major* new designs that are going to be done with it > > *have* been done and every thing else is maintenance. At that point the > > *new* designs will be on the *new* parts which the open source tool will > > not support. So if you want to be guaranteed to be behind the cutting > > edge, then by all means use tools that are perpetually out of date. > > Many designs want availability and cheapness instead of cutting edge. > With process problems, life cycles will get longer. Actually the cheapest parts *are* the newest. Spartan2 and 2E are much cheaper than Spartan or XC4000 or anything else that Xilinx makes. None of these parts have been out more than a year if I am not mistaken and some are only out a few months. By the time open source tools are ready for these parts, I expect Xilinx will have one or maybe even two new low cost families around. > > > All that in open source is better: > > > > > > - simple download/compile/install/use, any computer/OS native > > > > don't care, I only use one OS and that will be what the tool is > > compatible with. I'm an FPGA engineer, not a SW engineer. > > Irrelevant. That was my point! > > > - no licensing, can give copy to anyone. allows "config&compile at > > > customers site" designs, and yes, that includes "customer selects > > > modules and generates bitstream that runs them" style adaption to > > > modular interface hardware (see recompiling Linux kernel as an example) > > > > don't care. X and A both give away tools and the paid for versions are > > affordable in the context of running a business. > > Irrelevant. The tools are broken compared to what a decent > open source tool would be like. Open source tools are more broken. :) > > > - anyone can add their brains to development, wherever they have the > > > expertise (compare the open process of science vs pronouncements > > > from high from any closed governing body) > > > > don't care. I want tools to use to do work, not tools I can work on. > > Irrelevant. The tools are broken compared to what a decent > open source tool would be like. Open source tools are far more broken :) > > > For such features many (including myself) are willing to sacrifice > > > using the latest chip family for the time needed to reverse-engineer, > > > dito also not wringing the last drop of power out of an chip. > > > > Many does not include the majority of FPGA engineers, IMHO. In the FPGA > > world you have to work with the best chip for the job and that is often > > the most current chip. > > Rarely. The biggest latest chips have the highest profile. Don't know what you mean by profile. If you want to build a product rather than play, you pick the best part for the job and use the tools that support it. The commercial tools may have warts, but they let you get the job done. > > > They prove my point: vendor tools will not die (that was your claim) > > > just because open source tools appear and reduce user count of vendor > > > tools. Vendor tools can survive in that market. > > > > I am not talking about Synthesis and Simulation. I am talking about the > > back end tools. If Xilinx loses > 50% of its tool market to open source > > or third party tools, I expect they will drop their inhouse tools. They > > would have to either cut their tool staff by half which would ruin their > > tools in the future or start charging more for the chips to make up the > > differernce which would make it harder for them to compete. So > > sucessful open source tools will drive FPGA vendors out of the tool > > market. Then they would have to compete on just the chips and be a > > driving force somehow with the tools. > > No. Internal tools can be fixed in short time if companies have > a 4 digit support contract, which many will. What does this mean? I don't get it. > > > You are forgetting the most important part of open source: motivation. > > > It takes a lot of it. To accept sacrifice of the time to make software > > > without pay. That motivation must come from somewhere. Look for the > > > "somewheres" if you want to know where to look for the first appearances. > > > > Why would anyone be more motivated to develop backend tools? What is > > their value without the front end tools? > > Without free chip information to make backend tools, frontend > tools are useless. Compilers and fitters are fun to make. > GUIs are boring. Tell that to the frontend tool vendors. :) You are making up rules to suit your purposes. No one is talking about GUIs. The compilier *is* a front end tool. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Mon, 14 Oct 2002 15:12:06 -0400 Organization: Arius, Inc Lines: 43 Message-ID: <3DAB1706.B8F5B936@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <3DA63608.C5A58E9E@iprimus.com.au> <3DAA4B0C.EEC162EF@yahoo.com> <3DAA7156.4DF4C1B9@iprimus.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVabkHiITBOMSzKU+tqaksaOSiYseVTRwyYn3I4pxVkOzlia/JFBXdKK X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 14 Oct 2002 19:11:56 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed1.cidera.com!Cidera!dca6-feed2.news.algx.net!allegiance!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22000 Russell wrote: > > rickman wrote: > > I don't know what motovates you, but I don't think it is the same as > > most users of the tools. I would like to stop working with analogies > > and hear what the game plan is. Can you give us a roadmap of how you > > would procede? > > You compile a design a subcircuit at a time in HDL. You manually > place all the primitives into a compact area, or let a fitter do > it for you with suitable constraints, making an RPM. > Repeat for all subcircuits. Place these RPMs into bigger > groups of RPMs if needed. Place these 'mega' RPMs. Proceed > up the hierarchy until the whole design is done (one big RPM). > > This is what webpack 5.1i should allow you to do, but > i still need to try it. 4.2i was aimed there, but was > broken. > > Naturally, a GUI is involved in the floorplanning stage, > and is a suitable technical challenge for an open-source > project. The fitter would also be an excellent thing to > work on. I once made a pcb autorouter in dos that caused > all the tracks to naturally 'coalesce' into parallel > paths and minimize track lengths/bends. You are talking about the implementation of fitter and such. I want to hear how you plan to execute this project. What are the parts to be built and what will be the sequence of building them? How long will it take? What resources or information do you need? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Mon, 14 Oct 2002 19:40:04 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 105 Message-ID: References: <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1034624404 74825 128.32.112.203 (14 Oct 2002 19:40:04 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Mon, 14 Oct 2002 19:40:04 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22002 In article <6ubs5wkexa.fsf@chonsp.franklin.ch>, Neil Franklin wrote: >> point all the *major* new designs that are going to be done with it >> *have* been done and every thing else is maintenance. > >Makes one wonder why Xilinx re-warmed their over 2 years old Virtex in >form of Spartan-II. After already doing the same trick with Spartan, >and have since repeated it with Spartan-IIE. > >Seem to sell, so there seem to be quite a few people who do not need >then newest possible. The latest Spartan xx is "What was the top part 1.5 process generations ago" in the sweet spot die sizes. This is simply because 1.5 process generations behind is the sweet spot for volume manufacturing, where all the costs ends up being low and you can crank out $10-30, in package, tested, signed, sealed, and delivered chips. So why redesign the logic block? >> And you can live a rich full life without the $10,000+ tools. Right? > >Could you point out, where I am supposed to have claimed contrary to that? > >I was pointing out, that your "less users, A and X will not bei able >to afford development" stuff was nonsense. That there exists people >prepared to pay large sums for tools proves that A and X can keep on >making tools, by simply rising their price a bit. Xilinx and Altera do NOT NOT NOT make money from their tools. The only money they make is to act as a barrier so they will only need to support those likely to actually do something with their chips, and to pay for whatever software not developed in-house (which is a lot in the case of Foundation). People don't cry about using $2500 tools for putting designs on $2000 chips, or $0 tools for putting designs on $30 chips. Anyone who actually has the resources to do a design has access to the tool: small parts -> free beer, big parts -> full version. >Or rise their price to 2 times what they are today. Still a lot less >than what some people are prepared to pay. XILINX AND ALTERA DO NOT MAKE MONEY ON THE BACK END TOOLS, and never will because the customer would know when they are being gouged and refuse to deal with it, or switch brands. When you pay $2500 for foundation or $1100 for Alliance, you are paying for the ability to call up and get (hopefully) clued people on the other end of the line. >> tools in the future or start charging more for the chips to make up the >> difference which would make it harder for them to compete. > >And so what? Their competitors (ASIC vendors) also have to pay for >their tool development. Both can then chose how to distribute the >costs over software licenses (less larger ones) or chip costs >(possibly more sales due to the open source software), or use some of >the open source stuff to reduce their costs. > >May the best win. Actually, ASIC venders generally don't provide tools. TSMC etc just takes designs and pops out chips. Cadence etc provide the tools, which the customers directly pay for. >> Why would anyone be more motivated to develop backend tools? What is >> their value without the front end tools? > >As foundation to build front end tools on? > >The bitstream is the target. Back end makes that. From there on to >the front is ever increasing comfort. If I want a foundation to build INTERESTINg tools on, I'd borrow the existing back-ends. All the interesting stuff is int the front. >> What is your point? NO ONE can make a Xilinx compatible FPGA except >> Xilinx. NO ONE can make an Altera FPGA except Altera... > >I have my doubts. Where there is a will (enough money) competitors >will appear. Wait another decade, and THEN you may see Xilinx 4000 compatable parts. Patents are an enforced monopoly. >> How is compatibility necessary in CPUs or FPGAs? It only exists in the >> x86 world because the cat is out of the bag. > >And who says it will not get out of the bag in the FPGA world? It doesn't even exist across parts, a V300 is NOT bitfile compatable with a V400. >> I disagree that the backend is needed most or first. But then it is not >> my decision to make. > >Exactly. That is my descision. And my knowledge of the open source >community that runs into it. And I have given up disuading your that this is the wrong end to flow into. Ah well. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### Message-ID: <3DAB37BA.3A34@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 34 Date: Tue, 15 Oct 2002 10:31:38 +1300 NNTP-Posting-Host: 203.79.99.115 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1034631157 203.79.99.115 (Tue, 15 Oct 2002 10:32:37 NZDT) NNTP-Posting-Date: Tue, 15 Oct 2002 10:32:37 NZDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!telocity-west!TELOCITY!news-out.spamkiller.net!propagator2-maxim!news-in.spamkiller.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22001 Nicholas C. Weaver wrote: > >> I disagree that the backend is needed most or first. But then it is not > >> my decision to make. > > > >Exactly. That is my descision. And my knowledge of the open source > >community that runs into it. > > And I have given up disuading your that this is the wrong end to flow > into. Ah well. Steady on guys.... If Neil F. wants to work up from JBITS, that's his choice, and I can see some merit in it. ( I have given him some info on reduced eqn/vanilla outputs from other tools, to use in VAS ) some examples : I have used a humble uC diss-assembler, as a '2nd opinion' when chasing compiler/linker issues. It it often mentioned on this ng, the importance of being able to 'see what the tools did (wrong)' - things like encrypted netlists make that harder. There is also plenty of education potential for a 'JBITS up' - system designers who 'have their head around' how it all comes together at the lowest levels, can get better results from higher level tools. Reports and analysis are an important part of a design process, and it seems this can only help that. -jg ###### Message-ID: <3DAB73D0.29D78FEE@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <3DA63608.C5A58E9E@iprimus.com.au> <3DAA4B0C.EEC162EF@yahoo.com> <3DAA7156.4DF4C1B9@iprimus.com.au> <3DAB1706.B8F5B936@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.10.1 Lines: 15 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Tue, 15 Oct 2002 11:48:00 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034646125 203.134.67.67 (Mon, 14 Oct 2002 21:42:05 EDT) NNTP-Posting-Date: Mon, 14 Oct 2002 21:42:05 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.tele.dk!small.news.tele.dk!24.226.1.12!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22019 rickman wrote: > > Russell wrote: > > ... > You are talking about the implementation of fitter and such. I want to > hear how you plan to execute this project. What are the parts to be > built and what will be the sequence of building them? How long will it > take? What resources or information do you need? One disadvantage of knowing how to do everything is having time to do just about nothing. It's a project i'll attempt some time, but it's too destracting to do right now. Anyway, i need to learn more about programming X windows. I can do M$ windows, but it's strangely unattractive to do so;) ###### Message-ID: <3DAB75EB.FB680AD2@iprimus.com.au> From: Russell X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <3DAA6DF8.6BBFDD16@iprimus.com.au> <3DAB1636.3714C61A@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.10.1 Lines: 42 X-Original-NNTP-Posting-Host: 127.0.0.1 Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Date: Tue, 15 Oct 2002 11:56:59 +1000 NNTP-Posting-Host: 203.134.67.67 X-Complaints-To: news@primus.ca X-Trace: news.primus.ca 1034646677 203.134.67.67 (Mon, 14 Oct 2002 21:51:17 EDT) NNTP-Posting-Date: Mon, 14 Oct 2002 21:51:17 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed-east.nntpserver.com!nntpserver.com!feed.cgocable.net!feed.tor.primus.ca!news.primus.ca!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22020 rickman wrote: > > Russell wrote: > > > > rickman wrote: > > > ... > > > Many does not include the majority of FPGA engineers, IMHO. In the FPGA > > > world you have to work with the best chip for the job and that is often > > > the most current chip. > > > > Rarely. The biggest latest chips have the highest profile. > > Don't know what you mean by profile. Just means that the latest and greatest big chip is what everyone hears about, but the garden variety 2-year old chips are the biggest sellers and are a good target for open-source tools. Once the tools are developed, adapting to new chips would be easier and quicker. > > No. Internal tools can be fixed in short time if companies have > > a 4 digit support contract, which many will. > > What does this mean? I don't get it. Just means that open-source tools won't cause vendor-supplied tools to disappear due to lack of profit. > > > Why would anyone be more motivated to develop backend tools? What is > > > their value without the front end tools? > > > > Without free chip information to make backend tools, frontend > > tools are useless. Compilers and fitters are fun to make. > > GUIs are boring. > > Tell that to the frontend tool vendors. :) You are making up rules to > suit your purposes. No one is talking about GUIs. The compilier *is* a > front end tool. I think a good graphic interface like floor-planner is needed for doing manual routing. This is an intermediate tool after the HDL compilation step. ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Tue, 15 Oct 2002 07:53:37 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: X-Complaints-To: abuse@supernews.com Lines: 19 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!freenix!news-feed.riddles.org.uk!sn-xit-03!sn-xit-06!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:22029 Thanks. >I found a flowchart on page 2-4 of > >http://support.xilinx.com/support/sw_manuals/3_1i/download/dev_ref.zip > >This together with a description of all the different programs was >fairly easy to incorporate into script to run partgen, ngdbuild, map, >par, trce, bitgen, promgen, ngdanno, and ngd2ver. Is the Floorplanner in there? I didn't see it but I might have missed it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### Message-ID: <3DAC27F6.1FC6B2E6@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 36 Date: Tue, 15 Oct 2002 14:37:17 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034692637 68.15.41.165 (Tue, 15 Oct 2002 10:37:17 EDT) NNTP-Posting-Date: Tue, 15 Oct 2002 10:37:17 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22016 Hal, didn't you know that floorplanning isn't considered a normal design flow, only the 5% designs from hell need it ;-) Hal Murray wrote: > Thanks. > > >I found a flowchart on page 2-4 of > > > >http://support.xilinx.com/support/sw_manuals/3_1i/download/dev_ref.zip > > > >This together with a description of all the different programs was > >fairly easy to incorporate into script to run partgen, ngdbuild, map, > >par, trce, bitgen, promgen, ngdanno, and ngd2ver. > > Is the Floorplanner in there? I didn't see it but I might > have missed it. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Wed, 16 Oct 2002 14:09:15 -0400 Organization: Arius, Inc Lines: 329 Message-ID: <3DADAB4B.F39DB266@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVYt9ODvuoTp7DJ4m9dy5uM19XUxFK6tV9wc//LZk9mGrimpyWtDupEA X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 16 Oct 2002 18:09:15 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.cwix.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22067 Neil Franklin wrote: > > I care for whatever chip solves my problem. The 2 year old ones do so. That is my point. You are focusing on tools for "out of date" chips. I am talking about the fact that open source tools will always be out of date. If that is all you need, then great. But don't expect the design community to welcome open source with open arms. :) > > point all the *major* new designs that are going to be done with it > > *have* been done and every thing else is maintenance. > > Makes one wonder why Xilinx re-warmed their over 2 years old Virtex in > form of Spartan-II. After already doing the same trick with Spartan, > and have since repeated it with Spartan-IIE. > > Seem to sell, so there seem to be quite a few people who do not need > then newest possible. You clearly don't understand the FPGA market. The Spartan II parts are low cost versions of the Virtex parts. They are a major improvement over the previous Spartan parts. In that sense they are the "latest" parts for that market segment. > > > You can now see an actual project, started, that has an planned out > > > path leading to tools. > > > > I did check out the web site and I am not clear about where it is > > going. Can you explain in terms that an FPGA engineer can understand? > > I can only say stuff in whatever language I know. Which contains 74xx > logic, 8051s, Unix programming in C, shell/perl programming, and doing > FPGA in JBits. Sorry if your particular jargon is not supported. > > > > For such features many (including myself) are willing to sacrifice > > > using the latest chip family for the time needed to reverse-engineer, > > > dito also not wringing the last drop of power out of an chip. > > > > Many does not include the majority of FPGA engineers, IMHO. > > Even if that is majority, there still is the rest. And therefore the open source tools will be an also-ran, poor step child. > > > Screws from one manufacturer once did not fit nuts from an other, > > > about 120 years ago, due to everyone using their own threads. Once the > > > basic issues and design space in thread design were explored, standards > > > came. > > > > Bad analogy. It was in the best interest of the dozens or hundreds of > > manufacturer's interests to be compatible. > > Nope. It was in their best interst to lock in customers with incompatible > designs. It was users professional societies that forced the change in style. That is not correct. Even today electronics vendors know that they are better off making "standardized" parts because they are much more widely accepted and therefore sell better. > > > It is horses for courses. > > > > Not sure what that means, > > It means that what is best for one, is not automatically best for > another. And that the anther may be best served with something that > the first would never want. Yes, you are not an FPGA designer. You are on the fringe and you can use whatever you want. But this discussion was about the viability of open source tools and I think you will still find that they will not be well received by the FPGA design community. In the end they will be like Charles Moore and his small, but loyal following of Forth programmers. Not to say there is nothing good about Forth, but it is in very, very limited use even today. > > but I have seen $1000 FPGAs go on a board. If > > they had known that they would need a $2000 chip, the board would have > > never been designed. > > Absolutely not relevant for me, not for my project sizes. Yes, but that is the FPGA world. You are working in a different one where you can afford to spend manyears to develop your own tools to do a project that would otherwise be done in a few weeks. > > > > tools (unless you are counting the pennies). The expensive tools are > > > > the synthesis and simulation tools. > > > > > > I was talking of those. > > > > And you can live a rich full life without the $10,000+ tools. Right? > > Could you point out, where I am supposed to have claimed contrary to that? I believe you snipped your own statements and I have lost track of this. > I was pointing out, that your "less users, A and X will not bei able > to afford development" stuff was nonsense. That there exists people > prepared to pay large sums for tools proves that A and X can keep on > making tools, by simply rising their price a bit. My point is that X and A won't cooperate with open source tools so that the users keep buying their tools since it will be a large impact on them to lose that revenue. Maybe I am wrong. Maybe they don't care about the revenue. But they still care very much about having control of their in house tools and will not support open source efforts. They have said that they feel they have to provide support to anyone using their chips regardless of the tools they are using. So if open source tools are being used for their chips it creates problems for them in support. So they will try to stop it since they feel they can provide better tools anyway. > > I am not talking about Synthesis and Simulation. I am talking about the > > back end tools. If Xilinx loses > 50% of its tool market to open source > > or third party tools, I expect they will drop their inhouse tools. > > Or rise their price to 2 times what they are today. Still a lot less > than what some people are prepared to pay. > > > tools in the future or start charging more for the chips to make up the > > difference which would make it harder for them to compete. > > And so what? Their competitors (ASIC vendors) also have to pay for > their tool development. Both can then chose how to distribute the > costs over software licenses (less larger ones) or chip costs > (possibly more sales due to the open source software), or use some of > the open source stuff to reduce their costs. > > May the best win. > > > sucessful open source tools will drive FPGA vendors out of the tool > > market. Then they would have to compete on just the chips and be a > > CPU manufacturers seem to be living ok, on doing just that. You like to make this comparison. But there is very little to compare. > > > You are forgetting the most important part of open source: motivation. > > > It takes a lot of it. To accept sacrifice of the time to make software > > > without pay. That motivation must come from somewhere. Look for the > > > "somewheres" if you want to know where to look for the first appearances. > > > > Why would anyone be more motivated to develop backend tools? What is > > their value without the front end tools? > > As foundation to build front end tools on? > > The bitstream is the target. Back end makes that. From there on to > the front is ever increasing comfort. What will you feed into the backend? Output from the X or A front end? > > > > they are much more like the gcc target. But the back end tools are very > > > > different. *That* is why there are no third party back end tool > > > > vendors. > > > > > > They are software, like all other. I.e. designs to be specced, lines > > > of implementing program code to be written, work time to be spent. > > > That process is well understood. > > > > I am glad that you think *all* software is the same. > > All software in the end boils down to the same: time. Learning, > researching, coding, testing are all in the end time. Yes, but the time required to solve a problem depends greatly on the problem. Why do you think there are no third party back end tool vendors? > > matter of solving problems, not writing code. If you don't have good > > agorithms, you code will be lousy. Writing code is the *easy* part. > > Developing the algorithm is the hard part. > > It is in the end just time. > > > > Huh? I never said "all" CPUs, nor did I say all FPGAs. I clearly > > > stated 2 markets, "mass" and "specialist". > > > > What is your point? NO ONE can make a Xilinx compatible FPGA except > > Xilinx. NO ONE can make an Altera FPGA except Altera... > > I have my doubts. Where there is a will (enough money) competitors > will appear. You don't understand patent law, copyright and the economics of chip design and manufacture. How could anyone make a bitstream compatible FPGA? Can you explain how they would get around the legal IP issues? > > Just ask > > Clearlogic. :) > > AFAIK, they did not make FPGAs. They made ASICs that were layouted > automatically from Altera bitstreams. And it was not their ASICs that > got them into trouble, but rather that every single use of their > technology being helping Altera software licensees break the license. You misunderstand. The did nothing to "help break the license" other than to use the bitstream that came from an Altera tool. Likewise the innards of an FPGA are patented and otherwise protected IP. If you try to make an FPGA that is bitstream compatible you will either violate patents or end up with a very unworkable chip design or both. > So they are not particularly a good example for "cloning not possible". > > In fact in an hypothetical world with open source (no-Altera) tools, > user using them could develop on Altera and then manufacture on > Clearlogic, and those would not be violation licences, and so there > would be an non-infringing use for Clearlogic -> Altera loses case. Yes, but that is not an FPGA is it? The point is that Altera felt a threat and used their IP to shut them down. End of story. Do you know about the student who wrote an HDL version of an ARM processor? I don't remember the name, but he pulled it from the web after the ARM people had a chat with him. Same issues and he never once put it in silicon. > > > You claimed that binary incompatible is neccessary, and as such will > > > break tools, I pointed out that binary compatibility is possible in this > > > market, just as it turned out to be in CPUs, and sketched what its > > > result could look like. > > > > How is compatibility necessary in CPUs or FPGAs? It only exists in the > > x86 world because the cat is out of the bag. > > And who says it will not get out of the bag in the FPGA world? I do as well as X and A. How do you expect that to happen? > > > It is interesting that Altera did not chose the direct course of > > > attacking them with their patents on the actual chip technology. That > > > they needed to use such an indirect method of helping users breach the > > > the devel tools software license, which is less likely to succeed in > > > court, is telling us a lot. > > > > You are talking about making chips, now you are talking about the > > tools. > > Because the Clearlogic case was about tool missuse, or rather about > helping people missuse an tool, and no non-infringing use. > > > > > AMD could make parts that fit the Pentium socket because they had a > > > > license for that. After Socket 7 (IIRC) they no longer had that license > > > > and they now have to make their own interfaces. > > > > > > Socket 7 did not require any license. It is only with Slot 1 and later > > > Socket 370 that Intel introduced an patented signalling protocol (not > > > pinout) which required an license that they then refused to AMD. The > > > pinout is copyable, but useless it one can implement the signalling. > > > > No, you are confused. Socket 7 required a license, but AMD and several > > other companies already had that license due to manufacturing agreements > > that Intel had set up previously. They were later interpreted to > > include the pinout, the instruction set and even the microcode for > > processors up to the 386. > > AMDs license agreements only went up to 486. Even there they were not > complete (the ICE code was not covered). Socket 7 is Pentium, and so > not covered by any 486 stuff. > > Sockets can not be copyrighted, can not be patented, can not be > trademarked, so no protection. Signaling protocols can be patented, > that is what Intel then did on PentiumII. > > Same issue that they had with numbers not being trademarkable, so AMD > copied the 486 name with impunity. So Intel renamed the becomeing 586 > into Pentium, to prevent AMD being able to copy it. So you *do* understand that companies will protect their IP!!! Glad you could grasp this concept. > > > Also known as: do the most/first needed part first, show an actually > > > usable result, and accept that obsolence will happen and require an > > > "chase the moving target" attitude. gcc did/does this (different CPUs), > > > Linux did/does this (different computer architectures). Sure. > > > > I disagree that the backend is needed most or first. But then it is not > > my decision to make. > > Exactly. That is my descision. And my knowledge of the open source > community that runs into it. > > > > > Once you > > > > have built all the parts of the intended toolchain, what will the flow > > > > be? > > > > > > Tentatively (subject to changes while implementing): > > > > > > Users chosen language -> compiler (3rd party, multiple) > > > -> design reduced to LUT-sized elements, relative placed, their connection > s > > > reduced design -> vas (from my toolset) > > > -> design fitted to LUTs/F5s/etc, absolute placed, connections to PIP list > s > > > placed/routed design -> vm and libvirtex it calls (from my toolset) > > > -> .bit file to be used or displayed/debugged (using existing vd and vv) > > > > I don't understand any of this. What are you planning to do? > > If we do not have that much common language to base our discourse on, > I might as well give up. Good bye. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Wed, 16 Oct 2002 14:13:55 -0400 Organization: Arius, Inc Lines: 59 Message-ID: <3DADAC63.83648134@yahoo.com> References: <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6u8z10kehp.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZ00K7pJ+PQVBFN2flRZteW5d0NUeXs+RiW0RVe3hTLhUgY4c1VQc4Y X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 16 Oct 2002 18:13:51 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.cwix.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22112 Neil Franklin wrote: > > nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > > > rickman wrote: > > > > >So? Few if any significant companies can't afford the low end tools > > >that will get the job done. Not all tools are 5 figure. In fact very > > >few are. What is your point? > > > > WHen you are paying the engineers $50k/year, so they cost you > > $100k/year, you aren't going to blanch at the ~$1000 for the back-end > > xilinx tools. > > IF you are in that price range. Sure. I am not. > > > >I am glad that you think *all* software is the same. Technology is a > > >matter of solving problems, not writing code. If you don't have good > > >agorithms, you code will be lousy. Writing code is the *easy* part. > > >Developing the algorithm is the hard part. > > > > Ohh, strongly disagree. Developing the algorthms and proving the > > concepts in code is the easy part (its prototyping), its turning or > > recreatingthat code into something robust an widely usable thats hard, > > IMO. > > So the main 2 critics disagree totally with each other. Not really. I am saying that good routing algorithms are not easy. If they were we would have better ones already. FPGA is not the only world that uses them. There is tons of money spent on making them better. Nicholas is saying that even when you pick an algorithm and get it coded, it is a much larger job to make it commercially acceptable. > > {flow munched} > > > > >I don't understand any of this. What are you planning to do? > > > > Back end tools. Starting with bitgen and working backwards. > > > > Oh, where was static timing analysis? > > Not mentioned in the post, as not part of the question I was answering. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Wed, 16 Oct 2002 14:17:58 -0400 Organization: Arius, Inc Lines: 24 Message-ID: <3DADAD56.87E6338A@yahoo.com> References: <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZa85Ghh4EB42XuXxKKHnZDYSEsmBuNBYs3QW5fUuHpsEInMA8zx7Cq X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 16 Oct 2002 18:17:56 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22065 "Nicholas C. Weaver" wrote: > When you pay $2500 for foundation or $1100 for Alliance, you are > paying for the ability to call up and get (hopefully) clued people on > the other end of the line. GOOD LUCK!!! The best support I have gotten is in this newsgroup. When I call the support lines, I get people who are dying to get me off the phone so they can get credit for closing the case. When I mention some of the problems I have had with tools or parts I get emails not posted here. Too bad that is usually well after I need help. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Wed, 16 Oct 2002 14:26:39 -0400 Organization: Arius, Inc Lines: 119 Message-ID: <3DADAF5F.EE12D1CD@yahoo.com> References: <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> <6uk7kkinvy.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVa+lJcPYNJWzBPotdoIiEBHwR3JWcSEn82jrrTi3DGeiQiDG0eiQBTJ X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 16 Oct 2002 18:26:37 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed1.cidera.com!Cidera!dca6-feed2.news.algx.net!allegiance!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22068 Neil Franklin wrote: > > nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > > > Neil Franklin wrote: > > > > > >Makes one wonder why Xilinx re-warmed their over 2 years old Virtex in > > >form of Spartan-II. After already doing the same trick with Spartan, > > >and have since repeated it with Spartan-IIE. > > > > > >Seem to sell, so there seem to be quite a few people who do not need > > >then newest possible. > > > > The latest Spartan xx is "What was the top part 1.5 process > > generations ago" in the sweet spot die sizes. > > And it (SPartan-IIE) is also very similar to the Virtex-E and as such > an easy target to expand to. But by the time open source is ready for the SpartanII parts, there will be SpartanIII or SpartanIV parts out with *no* open source tools. > > So why redesign the logic block? > > No need to. And that is why we have quite a few near bit compatible > families. > > > >> And you can live a rich full life without the $10,000+ tools. Right? > > > > > >Could you point out, where I am supposed to have claimed contrary to that? > > > > > >I was pointing out, that your "less users, A and X will not bei able > > >to afford development" stuff was nonsense. That there exists people > > > > Xilinx and Altera do NOT NOT NOT make money from their tools. > > And that makes rickmans "open source is a threat" argument totally moot. I have already made the point that even if the $$$ are not an issue, FPGA vendors *have* to have control over their tools and will have major hearburn over trying to support open source tools for their chip customers. So they will not cooperate with open source tools. Heck, it has only been the last year or so that they will support *running* the tools under Linux!!! > > >> tools in the future or start charging more for the chips to make up the > > >> difference which would make it harder for them to compete. > > > > > >And so what? Their competitors (ASIC vendors) also have to pay for > > >their tool development. Both can then chose how to distribute the > > >costs over software licenses (less larger ones) or chip costs > > >(possibly more sales due to the open source software), or use some of > > >the open source stuff to reduce their costs. > > > > > >May the best win. > > > > Actually, ASIC venders generally don't provide tools. TSMC etc just > > takes designs and pops out chips. Cadence etc provide the tools, > > which the customers directly pay for. > > Which in the end, for the customer still is just a total-cost > comparison. Whether they pay Cadence direct or via TSMC is not really > relevant. Just as it is irrelevant whether they pay Xilinx via > software costs or chip costs. That is totally not true. NRE and chip costs are totally different. Anyone using large quantities of chips will switch for a few cents difference in price. Not so for thousands of dollars of tools costs. > > >> What is your point? NO ONE can make a Xilinx compatible FPGA except > > >> Xilinx. NO ONE can make an Altera FPGA except Altera... > > > > > >I have my doubts. Where there is a will (enough money) competitors > > >will appear. > > > > Wait another decade, and THEN you may see Xilinx 4000 compatable > > parts. Patents are an enforced monopoly. > > I know enough about patent law. It is just a matter of money to get > around it (even if that means buying strategic patents to trip Xilinx > up and make it cheaper for them to license their stuff). That is BS. A large company can spend their way around a small company, but two large companies play games to the death. Where is the money to start a new FPGA going to come from... ? > > >> How is compatibility necessary in CPUs or FPGAs? It only exists in the > > >> x86 world because the cat is out of the bag. > > > > > >And who says it will not get out of the bag in the FPGA world? > > > > It doesn't even exist across parts, a V300 is NOT bitfile compatable > > with a V400. > > Depends on your definition of compatible. I regard them as identical, > modulo some size parameters (1 line in an table each). Even XC2S30 and > XCV300 are just table differences. Only from the E types on do we have > bit meanings change (seems to be limited to DLLs and IOBs). And XCVxxxE > to XC2SxxxE seems to also be just table lines. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 16 Oct 2002 22:07:23 +0200 Organization: My own Private Self Lines: 233 Message-ID: <6uelaqjgg4.fsf@chonsp.franklin.ch> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> <3DADAB4B.F39DB266@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1034798844 978 10.0.3.2 (16 Oct 2002 20:07:24 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 16 Oct 2002 20:07:24 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:22113 rickman writes: > Neil Franklin wrote: > > > > I care for whatever chip solves my problem. The 2 year old ones do so. > > date. If that is all you need, then great. But don't expect the design > community to welcome open source with open arms. :) Did I ever do thet? I only said that I was doing something. You then decided to jump on me. Perhaps they are not for you, perhaps you will never use them. I could not care. I dont't make them for everyone. I make them for those people who want to use them. And I know that such people exist. Some of them outside of todays FPGA market. FPGAs are growing, not just in chip size, but also into new user groups. Some of them are lookign for what I am making. > > Seem to sell, so there seem to be quite a few people who do not need > > then newest possible. > > You clearly don't understand the FPGA market. I expect that Xilinx does understand it. They launched Spartan-II. I will take their estimate over yours. > > > > It is horses for courses. > > > > > > Not sure what that means, > > > > It means that what is best for one, is not automatically best for > > another. And that the anther may be best served with something that > > the first would never want. > > Yes, you are not an FPGA designer. You are on the fringe and you can > use whatever you want. But this discussion was about the viability of > open source tools and I think you will still find that they will not be > well received by the FPGA design community. For me it is, and has allways been, about making them, and those people I know who intend to use them. It you were labouring under the impression that I intended to take over the market, then you were reading my stuff wrong. > > I was pointing out, that your "less users, A and X will not bei able > > to afford development" stuff was nonsense. That there exists people > > prepared to pay large sums for tools proves that A and X can keep on > > making tools, by simply rising their price a bit. > > My point is that X and A won't cooperate with open source tools so that > the users keep buying their tools since it will be a large impact on > them to lose that revenue. Maybe I am wrong. Maybe they don't care > about the revenue. Given that they put out Webpack (and Alteras counterpart) for free, I doubt they will feel any financial impact. > have said that they feel they have to provide support to anyone using > their chips regardless of the tools they are using. Simply point out, that it is not out tool - no support - come back if problem also happens with our official tool. Open source users understand this. > > The bitstream is the target. Back end makes that. From there on to > > the front is ever increasing comfort. > > What will you feed into the backend? Output from the X or A front end? At present just interest to feed in my own simple language. May add XDL if that is sufficiently interesting. > > > > Huh? I never said "all" CPUs, nor did I say all FPGAs. I clearly > > > > stated 2 markets, "mass" and "specialist". > > > > > > What is your point? NO ONE can make a Xilinx compatible FPGA except > > > Xilinx. NO ONE can make an Altera FPGA except Altera... > > > > I have my doubts. Where there is a will (enough money) competitors > > will appear. > > You don't understand patent law, copyright and the economics of chip > design and manufacture. You seem to be good at missestimating. I actually know law quite well. To the extent that I am usually the persone everyone around here ask for legal advise. Most likely due to me having actually read the relevant law texts. > How could anyone make a bitstream compatible > FPGA? Can you explain how they would get around the legal IP issues? As I said: worst case get an license, in absolute worst case by tripping up one of the existing players (if they blankly refuse). IP law can be very interesting in that respect. Also anyone with enough financial interest can actually take an patent to court and have it declared irrelevant on an whole range of issues. It takes time and cost. But if enough profit are waiting, things like that happen. Lesser case: You do know, that nearly all the fundamental patents in FPGAs appeared around/pre 1985 (XC2000) and are now nearing their 17 year, and so at end of life? Give a few years (needed for any hypothetical bit-compatible scenario that makes cloning interesting anyway), and quite a lot of them will be gone. Don't forget that then the only patents remaining are detail patents, i.e. on the actual implementation. And that can be varied, without losing bit compatibility. The situation is getting simpler the longer time goes. Also you may want to take into account, that Altera managed to survive Xilinxes patents, despite starting when they Xilinx had maximal protection, and with Altera an latecomer. Any new competitor has an easier situation. And an further scenario: assume bit compatible becomes important. Either X or A is the winner in becoming the standard. How long do you think will the other of the 2 look at declining sales, until they clone? And we already know that a patent battle between them 2 ends in stalemate. The short conclusion: IP law is in no way the "no chance" you seem to regard it as. In particular when one has got enough money to run through an dedicated battle. > > > Just ask > > > Clearlogic. :) > > > > AFAIK, they did not make FPGAs. They made ASICs that were layouted > > automatically from Altera bitstreams. And it was not their ASICs that > > got them into trouble, but rather that every single use of their > > technology being helping Altera software licensees break the license. > > You misunderstand. The did nothing to "help break the license" other > than to use the bitstream that came from an Altera tool. And that is exactly the entire meaning of "help break the license". Offering an service that is auxillary to an crime, without any other legal use for that service. Look up "contributary infringement" if you want an interesting read. I understand the legal concept here very well, having read quite a bit on the Napster/Kazaa/etc cases and the deCSS/2600/websites cases, and the argumentation against them. > Likewise the > innards of an FPGA are patented and otherwise protected IP. If you try > to make an FPGA that is bitstream compatible you will either violate > patents or end up with a very unworkable chip design or both. You can get around an patent. Altera survived Xilinxes ones. AMD has wrung patents off of Intel, by tripping them over other stuff. Via has stopped Intel attacks by tripping them up. Ask an good IP lawyer about all the possibilities. IP law is not the clear "you lose" that you believe it to be. In fact the very name IP is an error, they are no property, but rather privileges, granted for very specific terms. And many patents do not fit those terms, and only survive because being not challenged, because fighting them is not profitable. Add an good slice of potential profit and the overturning starts. > > So they are not particularly a good example for "cloning not possible". > > > > In fact in an hypothetical world with open source (no-Altera) tools, > > user using them could develop on Altera and then manufacture on > > Clearlogic, and those would not be violation licences, and so there > > would be an non-infringing use for Clearlogic -> Altera loses case. > > Yes, but that is not an FPGA is it? The point is that Altera felt a > threat and used their IP to shut them down. The point is that they only just managed. That IP is not the surefire "end of competition" you seem to regard it as. > o you know > about the student who wrote an HDL version of an ARM processor? I don't > remember the name, but he pulled it from the web after the ARM people > had a chat with him. Yes, I know the case. I also know that IP owners (and any other financially strong party) can push financially weak opponents aside, ever if the patent would not hold up. AFAIK ARMs patent claim was not that strong, they had luck that their opponent was weak or possibly simply not interested (better stuff to do than fight[1]) and caved in. MIPS had a stronger case against a cloner, but their patent is also near/in EOL. [1] A motive I know well, having also given up against a weak trumped up claim (of violating data protection laws), because the cost (in time, the case was classic multiple appeals type stuff, with an good chance of going right up to the supreme court) of defending was larger than the loss of giving in. And yes, that is an other reason why I know quite a lot about law. > > Sockets can not be copyrighted, can not be patented, can not be > > trademarked, so no protection. Signaling protocols can be patented, > > that is what Intel then did on PentiumII. > > > > Same issue that they had with numbers not being trademarkable, so AMD > > copied the 486 name with impunity. So Intel renamed the becomeing 586 > > into Pentium, to prevent AMD being able to copy it. > > So you *do* understand that companies will protect their IP!!! Glad you > could grasp this concept. I understand IP law very well. Glad that you have noticed it. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### Message-ID: <3DADCC88.7D9F5D9@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? References: <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> <6uk7kkinvy.fsf@chonsp.franklin.ch> <3DADAF5F.EE12D1CD@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 31 Date: Wed, 16 Oct 2002 20:31:42 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034800302 68.15.41.165 (Wed, 16 Oct 2002 16:31:42 EDT) NNTP-Posting-Date: Wed, 16 Oct 2002 16:31:42 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22118 Good question. The road is littered with FPGA start ups and even big companies that tried to get in on the action: Dynachip, Gatefield, Motorola, TI, AMD,.... rickman wrote: > Where is the money to start a new FPGA going to come from... ? > > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 17 Oct 2002 00:11:28 -0400 Organization: Arius, Inc Lines: 266 Message-ID: <3DAE3870.702263CB@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> <3DADAB4B.F39DB266@yahoo.com> <6uelaqjgg4.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbs4amdnqzKMfF1G0SSZS8lwQwwywF4gtBAV4+IUo99//bZxkrsPD61 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 17 Oct 2002 04:11:25 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.abs.net!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22180 Neil Franklin wrote: > > rickman writes: > > > Neil Franklin wrote: > > > > > > I care for whatever chip solves my problem. The 2 year old ones do so. > > > > date. If that is all you need, then great. But don't expect the design > > community to welcome open source with open arms. :) > > Did I ever do thet? I only said that I was doing something. You then > decided to jump on me. I did not jump on you. If that is what this conversation has come to, then I will stop. :) > > > Seem to sell, so there seem to be quite a few people who do not need > > > then newest possible. > > > > You clearly don't understand the FPGA market. > > I expect that Xilinx does understand it. They launched Spartan-II. I > will take their estimate over yours. You don't understand that I am agreeing with Xilinx. You are saying you want to use second level chips and by the time you have support for SpartanII it will be a second level chip. > > Yes, you are not an FPGA designer. You are on the fringe and you can > > use whatever you want. But this discussion was about the viability of > > open source tools and I think you will still find that they will not be > > well received by the FPGA design community. > > For me it is, and has allways been, about making them, and those > people I know who intend to use them. It you were labouring under > the impression that I intended to take over the market, then you were > reading my stuff wrong. No, but you have been saying that open source tools will become "better" than X or A tools. I don't agree that this will ever happen. > Given that they put out Webpack (and Alteras counterpart) for free, I > doubt they will feel any financial impact. Not if the open source tools are not widely used. Webpack is an introductory tool. If you are doing a significant design you won't want to work with limited and "crippled" tools. You will pay for them, that is, assuming that you are a company with a financial interest in the result. > > have said that they feel they have to provide support to anyone using > > their chips regardless of the tools they are using. > > Simply point out, that it is not out tool - no support - come back > if problem also happens with our official tool. Open source users > understand this. I don't know what this means. > > > The bitstream is the target. Back end makes that. From there on to > > > the front is ever increasing comfort. > > > > What will you feed into the backend? Output from the X or A front end? > > At present just interest to feed in my own simple language. May add > XDL if that is sufficiently interesting. > > > > > > Huh? I never said "all" CPUs, nor did I say all FPGAs. I clearly > > > > > stated 2 markets, "mass" and "specialist". > > > > > > > > What is your point? NO ONE can make a Xilinx compatible FPGA except > > > > Xilinx. NO ONE can make an Altera FPGA except Altera... > > > > > > I have my doubts. Where there is a will (enough money) competitors > > > will appear. > > > > You don't understand patent law, copyright and the economics of chip > > design and manufacture. > > You seem to be good at missestimating. I actually know law quite > well. To the extent that I am usually the persone everyone around here > ask for legal advise. Most likely due to me having actually read the > relevant law texts. If you feel that anyone can make compatible, viable FPGAs then you don't understand the law or the technology. There are simply too many barriers. Instead of playing word games, perhaps you can tell us *how* this will happen. > > How could anyone make a bitstream compatible > > FPGA? Can you explain how they would get around the legal IP issues? > > As I said: worst case get an license, in absolute worst case by > tripping up one of the existing players (if they blankly refuse). IP > law can be very interesting in that respect. > > Also anyone with enough financial interest can actually take an patent > to court and have it declared irrelevant on an whole range of issues. > It takes time and cost. But if enough profit are waiting, things like > that happen. Where do open source advocates get the financial backing??? X and A regularly fight over patents. They spend tons of money on this because they know it is what they have to do. Then they settle down and agree to cooperate. But if you don't *have* IP, how will you bargan with them? > Lesser case: You do know, that nearly all the fundamental patents in > FPGAs appeared around/pre 1985 (XC2000) and are now nearing their 17 > year, and so at end of life? Give a few years (needed for any hypothetical > bit-compatible scenario that makes cloning interesting anyway), and > quite a lot of them will be gone. > > Don't forget that then the only patents remaining are detail patents, > i.e. on the actual implementation. And that can be varied, without > losing bit compatibility. The situation is getting simpler the longer > time goes. That is the part I don't agree with. But I will let you show us. > Also you may want to take into account, that Altera managed to > survive Xilinxes patents, despite starting when they Xilinx had > maximal protection, and with Altera an latecomer. Any new competitor > has an easier situation. > > And an further scenario: assume bit compatible becomes important. > Either X or A is the winner in becoming the standard. How long do you > think will the other of the 2 look at declining sales, until they > clone? And we already know that a patent battle between them 2 ends in > stalemate. I disagree that a newcomer *now* has an easier time of it. Now you have not only X to deal with, you have the X&A cartel. They have a vested interest in keeping others out. They are now sharing more patents than ever before because each one has IP that the other wants. They don't need anything from others. > The short conclusion: IP law is in no way the "no chance" you seem to > regard it as. In particular when one has got enough money to run > through an dedicated battle. Well, then show us the money :) > > > > Just ask > > > > Clearlogic. :) > > > > > > AFAIK, they did not make FPGAs. They made ASICs that were layouted > > > automatically from Altera bitstreams. And it was not their ASICs that > > > got them into trouble, but rather that every single use of their > > > technology being helping Altera software licensees break the license. > > > > You misunderstand. The did nothing to "help break the license" other > > than to use the bitstream that came from an Altera tool. > > And that is exactly the entire meaning of "help break the license". > Offering an service that is auxillary to an crime, without any other > legal use for that service. Look up "contributary infringement" if you > want an interesting read. I understand the legal concept here very > well, having read quite a bit on the Napster/Kazaa/etc cases and the > deCSS/2600/websites cases, and the argumentation against them. But you make a point that has nothing to do with the discussion. We are talking about making chips. > > Likewise the > > innards of an FPGA are patented and otherwise protected IP. If you try > > to make an FPGA that is bitstream compatible you will either violate > > patents or end up with a very unworkable chip design or both. > > You can get around an patent. Altera survived Xilinxes ones. AMD has > wrung patents off of Intel, by tripping them over other stuff. Via has > stopped Intel attacks by tripping them up. Ask an good IP lawyer about > all the possibilities. IP law is not the clear "you lose" that you > believe it to be. > > In fact the very name IP is an error, they are no property, but rather > privileges, granted for very specific terms. And many patents do not > fit those terms, and only survive because being not challenged, because > fighting them is not profitable. Add an good slice of potential profit > and the overturning starts. Who is going to go up against X and A over these patents? Who has this money? > > > So they are not particularly a good example for "cloning not possible". > > > > > > In fact in an hypothetical world with open source (no-Altera) tools, > > > user using them could develop on Altera and then manufacture on > > > Clearlogic, and those would not be violation licences, and so there > > > would be an non-infringing use for Clearlogic -> Altera loses case. > > > > Yes, but that is not an FPGA is it? The point is that Altera felt a > > threat and used their IP to shut them down. > > The point is that they only just managed. That IP is not the surefire > "end of competition" you seem to regard it as. You say they "just managed" but Clearpoint was not making FPGAs were they? So how is their case relevant? > > o you know > > about the student who wrote an HDL version of an ARM processor? I don't > > remember the name, but he pulled it from the web after the ARM people > > had a chat with him. > > Yes, I know the case. I also know that IP owners (and any other > financially strong party) can push financially weak opponents aside, > ever if the patent would not hold up. > > AFAIK ARMs patent claim was not that strong, they had luck that their > opponent was weak or possibly simply not interested (better stuff to > do than fight[1]) and caved in. MIPS had a stronger case against a > cloner, but their patent is also near/in EOL. If the ARM case is not strong, then why does everyone including the behemoth Intel license rather than "break" the patents? > [1] A motive I know well, having also given up against a weak trumped > up claim (of violating data protection laws), because the cost (in > time, the case was classic multiple appeals type stuff, with an good > chance of going right up to the supreme court) of defending was larger > than the loss of giving in. > > And yes, that is an other reason why I know quite a lot about law. > > > > Sockets can not be copyrighted, can not be patented, can not be > > > trademarked, so no protection. Signaling protocols can be patented, > > > that is what Intel then did on PentiumII. > > > > > > Same issue that they had with numbers not being trademarkable, so AMD > > > copied the 486 name with impunity. So Intel renamed the becomeing 586 > > > into Pentium, to prevent AMD being able to copy it. > > > > So you *do* understand that companies will protect their IP!!! Glad you > > could grasp this concept. > > I understand IP law very well. Glad that you have noticed it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: 17 Oct 2002 21:12:30 +0200 Organization: My own Private Self Lines: 175 Message-ID: <6ufzv4dgm9.fsf@chonsp.franklin.ch> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> <3DADAB4B.F39DB266@yahoo.com> <6uelaqjgg4.fsf@chonsp.franklin.ch> <3DAE3870.702263CB@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1034881950 597 10.0.3.2 (17 Oct 2002 19:12:30 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 17 Oct 2002 19:12:30 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:22181 rickman writes: > Neil Franklin wrote: > > > > > Yes, you are not an FPGA designer. You are on the fringe and you can > > > use whatever you want. But this discussion was about the viability of > > > open source tools and I think you will still find that they will not be > > > well received by the FPGA design community. > > > > For me it is, and has allways been, about making them, and those > > people I know who intend to use them. It you were labouring under > > the impression that I intended to take over the market, then you were > > reading my stuff wrong. > > No, but you have been saying that open source tools will become "better" > than X or A tools. I don't agree that this will ever happen. I think we need to define "better" here. You seem to define it as "supports newest stuff". Open source people define it as "more flexible, less bugs, less usage restrictions", and also an fairly difficult[1] to describe "feels right" that open source stuff has. [1] one ingredient is that it is user-written and therefore simple "fits" the way users work better than anything that is specified by an market research team. > > > have said that they feel they have to provide support to anyone using > > > their chips regardless of the tools they are using. > > > > Simply point out, that it is not out tool - no support - come back > > if problem also happens with our official tool. Open source users > > understand this. > > I don't know what this means. Translation: "we don't support you, unless you use our tools". > > > How could anyone make a bitstream compatible > > > FPGA? Can you explain how they would get around the legal IP issues? > > > > As I said: worst case get an license, in absolute worst case by > > tripping up one of the existing players (if they blankly refuse). IP > > law can be very interesting in that respect. > > > > Also anyone with enough financial interest can actually take an patent > > to court and have it declared irrelevant on an whole range of issues. > > It takes time and cost. But if enough profit are waiting, things like > > that happen. > > Where do open source advocates get the financial backing??? We were not talking of open source (= software) developers here. We are talking about an chip (= hardware) vendors. Such tend to have money, a lot of it. > to cooperate. But if you don't *have* IP, how will you bargan with > them? Any chip company can buy in IP, until they have enough to make A&X listen. Just look at how VIA got round Intels P4 signalling patents by exactly that trick. > > Also you may want to take into account, that Altera managed to > > survive Xilinxes patents, despite starting when they Xilinx had > > maximal protection, and with Altera an latecomer. Any new competitor > > has an easier situation. > > > > And an further scenario: assume bit compatible becomes important. > > Either X or A is the winner in becoming the standard. How long do you > > think will the other of the 2 look at declining sales, until they > > clone? And we already know that a patent battle between them 2 ends in > > stalemate. > > I disagree that a newcomer *now* has an easier time of it. Now you have > not only X to deal with, you have the X&A cartel. Whose remaining patents are becoming more and more detail focussed, as the basic ones are running out. And so easier to circumvent by using an different implementation. The days when simply an LUT or an PIP was an new idea and patentable are over. > They have a vested > interest in keeping others out. Interest yes, but success in doing it? > > The short conclusion: IP law is in no way the "no chance" you seem to > > regard it as. In particular when one has got enough money to run > > through an dedicated battle. > > Well, then show us the money :) A: the entire sub-discussion was about an potential (= not yet the case, and possible never the case) situation B: if the situation arrives, then the money can be shown. Basically that demonstration will point to (part of) the profit possible by cloning. > > > You misunderstand. The did nothing to "help break the license" other > > > than to use the bitstream that came from an Altera tool. > > > > And that is exactly the entire meaning of "help break the license". > > Offering an service that is auxillary to an crime, without any other > > legal use for that service. Look up "contributary infringement" if you > > want an interesting read. I understand the legal concept here very > > well, having read quite a bit on the Napster/Kazaa/etc cases and the > > deCSS/2600/websites cases, and the argumentation against them. > > But you make a point that has nothing to do with the discussion. We are > talking about making chips. In this sub-discussion (of about 5 subdiscussions in this thread) you were claiming that Altera broke Clearlogic on an FPGA patent. I was countering that claim. > > You can get around an patent. Altera survived Xilinxes ones. AMD has > > wrung patents off of Intel, by tripping them over other stuff. Via has > > stopped Intel attacks by tripping them up. Ask an good IP lawyer about > > all the possibilities. IP law is not the clear "you lose" that you > > believe it to be. > > > > In fact the very name IP is an error, they are no property, but rather > > privileges, granted for very specific terms. And many patents do not > > fit those terms, and only survive because being not challenged, because > > fighting them is not profitable. Add an good slice of potential profit > > and the overturning starts. > > Who is going to go up against X and A over these patents? Who has this > money? Whoever convinces an investor or managment that there is money to be made in clones. And no I am not going to try an predict a company name. > > > Yes, but that is not an FPGA is it? The point is that Altera felt a > > > threat and used their IP to shut them down. > > > > The point is that they only just managed. That IP is not the surefire > > "end of competition" you seem to regard it as. > > You say they "just managed" but Clearpoint was not making FPGAs were > they? So how is their case relevant? It is relevant to show you that FPGA patents are not the all-powerfull things you presented them as. Again here: annother sub-discussion. This thread has wandered quite far, even within single posts. > > AFAIK ARMs patent claim was not that strong, they had luck that their > > opponent was weak or possibly simply not interested (better stuff to > > do than fight[1]) and caved in. MIPS had a stronger case against a > > cloner, but their patent is also near/in EOL. > > If the ARM case is not strong, then why does everyone including the > behemoth Intel license rather than "break" the patents? Intel did not just re-implement the ARM instruction set, they actually took over ARM/DEC chip design internals and actual design code (and a few employees AFAIK). That translated into faster to market for them. That is what the license was for, and paid from. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Why can Xilinx sw be as good as Altera's sw? Date: Thu, 17 Oct 2002 19:24:25 -0400 Organization: Arius, Inc Lines: 244 Message-ID: <3DAF46A9.B345BC35@yahoo.com> References: <3da42f23$1_1@news.estpak.ee> <1034208063.92802.0@dyke.uk.clara.net> <3DA4DFF0.EFDF32D4@iprimus.com.au> <3DA4F385.BC767D4B@andraka.com> <3DA501C5.DE008F33@iprimus.com.au> <3DA504D9.D1CCB4A0@andraka.com> <3DA5091E.84202951@andraka.com> <3DA50F51.39CD1D0C@iprimus.com.au> <3DA51D11.D69E5E9C@yahoo.com> <3DA54C95.FFE0D5BA@iprimus.com.au> <3DA5D794.F75DB6F9@yahoo.com> <6u4rbundwm.fsf@chonsp.franklin.ch> <3DA628A6.A32FE4@yahoo.com> <6uzntj1vcv.fsf@chonsp.franklin.ch> <3DAA5782.D3869B5@yahoo.com> <6ubs5wkexa.fsf@chonsp.franklin.ch> <3DADAB4B.F39DB266@yahoo.com> <6uelaqjgg4.fsf@chonsp.franklin.ch> <3DAE3870.702263CB@yahoo.com> <6ufzv4dgm9.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZ1Tp2ZfJ2djDdeqESWvc7pfcRFcIIIhafoz5N0DMD8ryXQYTDTtHhH X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 17 Oct 2002 23:24:19 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.cwix.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22232 Neil Franklin wrote: > > rickman writes: > > > Neil Franklin wrote: > > > > > > > Yes, you are not an FPGA designer. You are on the fringe and you can > > > > use whatever you want. But this discussion was about the viability of > > > > open source tools and I think you will still find that they will not be > > > > well received by the FPGA design community. > > > > > > For me it is, and has allways been, about making them, and those > > > people I know who intend to use them. It you were labouring under > > > the impression that I intended to take over the market, then you were > > > reading my stuff wrong. > > > > No, but you have been saying that open source tools will become "better" > > than X or A tools. I don't agree that this will ever happen. > > I think we need to define "better" here. You seem to define it as > "supports newest stuff". Open source people define it as "more > flexible, less bugs, less usage restrictions", and also an fairly > difficult[1] to describe "feels right" that open source stuff has. > > [1] one ingredient is that it is user-written and therefore simple > "fits" the way users work better than anything that is specified by > an market research team. Ok, you define "better" that way then it may be better. But I don't know many engineer who use those metrics as their primary tests of a tool. Most of them want the tool to do a good job and to do it on the parts they want to use. > > > > have said that they feel they have to provide support to anyone using > > > > their chips regardless of the tools they are using. > > > > > > Simply point out, that it is not out tool - no support - come back > > > if problem also happens with our official tool. Open source users > > > understand this. > > > > I don't know what this means. > > Translation: "we don't support you, unless you use our tools". I think one of the problems we have is that you don't post in clear complete sentances and thoughts. The above "translation" is clear, but its purpose is not. I assume that you are saying that this is what Xilinx would say to a open source tool user? Xilinx people have posted here that they feel the need to support anyone buying their chips. If a company wants to put 1,000,000 boards out with a Xilinx FPGA and they are having trouble getting a bitstream to work reliably using open source tools, Xilinx isn't going to say "tough". Or at least this is how I understand the postings here on similar topics by Xilinx people. Providing such support will be very tough for Xilinx so they will try to avoid this situation ever happening by not supporting open source tools. > > > > How could anyone make a bitstream compatible > > > > FPGA? Can you explain how they would get around the legal IP issues? > > > > > > As I said: worst case get an license, in absolute worst case by > > > tripping up one of the existing players (if they blankly refuse). IP > > > law can be very interesting in that respect. > > > > > > Also anyone with enough financial interest can actually take an patent > > > to court and have it declared irrelevant on an whole range of issues. > > > It takes time and cost. But if enough profit are waiting, things like > > > that happen. > > > > Where do open source advocates get the financial backing??? > > We were not talking of open source (= software) developers here. We are > talking about an chip (= hardware) vendors. Such tend to have money, a > lot of it. So how do you know that anyone will be making a clone chip anytime in the future? Why do you think that a company could make money by trying to move into a "specialty" market and turning it into a "commodity" market? I certainly see no reason for a company to spend large sums of money to do so. > > to cooperate. But if you don't *have* IP, how will you bargan with > > them? > > Any chip company can buy in IP, until they have enough to make A&X > listen. Just look at how VIA got round Intels P4 signalling patents by > exactly that trick. They can't buy it from X&A! If X&A are using others IP, then they most likely are paying for it already so there is no leverage. I have not heard that the I&V suit is settled. Last I heard they were still in court, so Via has gotten away with nothing. > > > Also you may want to take into account, that Altera managed to > > > survive Xilinxes patents, despite starting when they Xilinx had > > > maximal protection, and with Altera an latecomer. Any new competitor > > > has an easier situation. > > > > > > And an further scenario: assume bit compatible becomes important. > > > Either X or A is the winner in becoming the standard. How long do you > > > think will the other of the 2 look at declining sales, until they > > > clone? And we already know that a patent battle between them 2 ends in > > > stalemate. > > > > I disagree that a newcomer *now* has an easier time of it. Now you have > > not only X to deal with, you have the X&A cartel. > > Whose remaining patents are becoming more and more detail focussed, as > the basic ones are running out. And so easier to circumvent by using > an different implementation. The days when simply an LUT or an PIP was > an new idea and patentable are over. And it would be very difficult to use that different implementation to make a bitstream compatible part. > > They have a vested > > interest in keeping others out. > > Interest yes, but success in doing it? So far, so good! What happened to all the others who have tried? > > > The short conclusion: IP law is in no way the "no chance" you seem to > > > regard it as. In particular when one has got enough money to run > > > through an dedicated battle. > > > > Well, then show us the money :) > > A: the entire sub-discussion was about an potential (= not yet the > case, and possible never the case) situation > > B: if the situation arrives, then the money can be shown. Basically > that demonstration will point to (part of) the profit possible by cloning. You are therefor making claims that you are now saying can not be demonstated. Kinda hard to draw a conclusion. I think you greatly under estimate the difficulty of starting such a business and over estimate the potential rewards. Both will keep any company out of the market for a long time unless they produce parts that are somehow new and don't infringe. > > > > You misunderstand. The did nothing to "help break the license" other > > > > than to use the bitstream that came from an Altera tool. > > > > > > And that is exactly the entire meaning of "help break the license". > > > Offering an service that is auxillary to an crime, without any other > > > legal use for that service. Look up "contributary infringement" if you > > > want an interesting read. I understand the legal concept here very > > > well, having read quite a bit on the Napster/Kazaa/etc cases and the > > > deCSS/2600/websites cases, and the argumentation against them. > > > > But you make a point that has nothing to do with the discussion. We are > > talking about making chips. > > In this sub-discussion (of about 5 subdiscussions in this thread) you > were claiming that Altera broke Clearlogic on an FPGA patent. I was > countering that claim. > > > > You can get around an patent. Altera survived Xilinxes ones. AMD has > > > wrung patents off of Intel, by tripping them over other stuff. Via has > > > stopped Intel attacks by tripping them up. Ask an good IP lawyer about > > > all the possibilities. IP law is not the clear "you lose" that you > > > believe it to be. > > > > > > In fact the very name IP is an error, they are no property, but rather > > > privileges, granted for very specific terms. And many patents do not > > > fit those terms, and only survive because being not challenged, because > > > fighting them is not profitable. Add an good slice of potential profit > > > and the overturning starts. > > > > Who is going to go up against X and A over these patents? Who has this > > money? > > Whoever convinces an investor or managment that there is money to be > made in clones. And no I am not going to try an predict a company name. And that is where we differ. There is very little money in making a "clone" and thereby changing the market to a commodity. All the manufacturers would suffer from this. > > > > Yes, but that is not an FPGA is it? The point is that Altera felt a > > > > threat and used their IP to shut them down. > > > > > > The point is that they only just managed. That IP is not the surefire > > > "end of competition" you seem to regard it as. > > > > You say they "just managed" but Clearpoint was not making FPGAs were > > they? So how is their case relevant? > > It is relevant to show you that FPGA patents are not the all-powerfull > things you presented them as. Again here: annother sub-discussion. > This thread has wandered quite far, even within single posts. And it failed to show that. > > > AFAIK ARMs patent claim was not that strong, they had luck that their > > > opponent was weak or possibly simply not interested (better stuff to > > > do than fight[1]) and caved in. MIPS had a stronger case against a > > > cloner, but their patent is also near/in EOL. > > > > If the ARM case is not strong, then why does everyone including the > > behemoth Intel license rather than "break" the patents? > > Intel did not just re-implement the ARM instruction set, they actually > took over ARM/DEC chip design internals and actual design code (and a > few employees AFAIK). That translated into faster to market for them. > That is what the license was for, and paid from. So in the Intel case it is a good business decision to license the technology from ARM rather than to try to fight them. In the case of Xilinx it is better to fight them than to license the technology or to buy the chips? Why? I think there is little difference. So what about all the dozens of other licensees of the ARM design? Obviously it is not that difficult a design to produce since a college student produced one. None of the licensees have tried to fight ARM over the patent issue rather than pay the license. And then there are dozens if not hundreds of competing CPUs that don't infringe the patents. You like making comparisons between CPUs and FPGAs. Why is it so different in this context? Why would *any* company try to build compatible FPGAs that infringe patents rather than build one that is different and does not? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX