From: "Ulises Hernandez" Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: Thu, 3 Oct 2002 13:42:10 +0100 Organization: ECS Technology Ltd. Lines: 47 Message-ID: <1033648940.927582@cswreg.cos.agilent.com> References: Reply-To: "Ulises Hernandez" NNTP-Posting-Host: cswreg.cos.agilent.com X-Trace: cswtrans.cos.agilent.com 1033648941 22877 130.29.154.45 (3 Oct 2002 12:42:21 GMT) X-Complaints-To: usenet@cswtrans.cos.agilent.com NNTP-Posting-Date: Thu, 3 Oct 2002 12:42:21 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Cache-Post-Path: cswreg.cos.agilent.com!unknown@sqf3448.britain.agilent.com X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!telocity-west!TELOCITY!enews.sgi.com!sdd.hp.com!agilent.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21585 Hi, There are a lot of things to consider in a low power design. - Your core voltage (1.5V is a good figure) - Packaging aspects (lower die tempearature, 'the hotter it runs, the quicker it fails' :o) - Metal Layers (passive silicon no longer dissipates/sink heat in these days because there is no passive stuff) - ... - RTL code For me the interesting bit is the RTL coding, for a FSM as you said, you can use one-hot encoding because only one-bit will change every clock (reduces clock activity which is a killer in power consumption). If you change from state A to state B more often than to state C try state A and B encoded with low toggle rate ("most likely branch encoding"). Disabling your clock in your IDLE state could be interesting (if you have the capability to do it) and enable it with the scape condition. There are a whole bunch of things you could do. This Xilinx paper is quite interesting http://www.xilinx.com/xcell/xl38/xcell38_40.pdf Google also helps. Regards Ulises Hernandez Design Enginner ECS Technology Ltd. www.ecs-tech.com "skillwood" wrote in message news:anhas6$e4ro0$1@ID-159866.news.dfncis.de... > Hi all, > Can some one give me an introduction to low power SoC design . What is > difference from an ordinary design and low power design in the design stage > . Suppose I am designing a fsm based sequential logic , at which stage the > "LOW POWER " Comes in . > > thanks > skillie > > ###### From: Steve Prokosch Newsgroups: comp.arch.fpga Subject: Re: Low power design Date: Thu, 03 Oct 2002 10:01:54 -0600 Organization: Xilinx, Inc. Lines: 15 Message-ID: <3D9C69F2.B4B21B89@xilinx.com> References: NNTP-Posting-Host: 149.199.109.19 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.78 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!arclight.uoregon.edu!enews.sgi.com!nntp.wetware.com!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21569 check the xilinx CPLD app note xapp 346 for some starters. http://www.xilinx.com/apps/epld.htm Steve skillwood wrote: > Hi all, > Can some one give me an introduction to low power SoC design . What is > difference from an ordinary design and low power design in the design stage > . Suppose I am designing a fsm based sequential logic , at which stage the > "LOW POWER " Comes in . > > thanks > skillie ###### From: russelmann@hotmail.com (Rudolf Usselmann) Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: 3 Oct 2002 18:56:45 -0700 Organization: http://groups.google.com/ Lines: 39 Message-ID: References: NNTP-Posting-Host: 203.152.41.201 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1033696605 31515 127.0.0.1 (4 Oct 2002 01:56:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 4 Oct 2002 01:56:45 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21641 "skillwood" wrote in message news:... > Hi all, > Can some one give me an introduction to low power SoC design . What is > difference from an ordinary design and low power design in the design stage > . Suppose I am designing a fsm based sequential logic , at which stage the > "LOW POWER " Comes in . > > thanks > skillie Understand first when a CMOS device "burns" power: Each time a node changes level (from 0 to 1; or from 2 to 0). [There is lot more but thats typically controlled by the technology vendor, use a LOW-POWER library if you are doing an ASIC ...] From the coding aspect, there are two things you can do: 1) Reduce the Clock speed 2) Reduce overall toggle rate To reduce the clock might not be easy if you are in an FPGA. If you are using a DPLL in an FPGA you might be able to change the clock rate. For example from "full speed" to "half speed". Make sure clock change is synchronous and glitch free .... The ultimate in "saving power" would be to turn the clock off all together. This might not always be practical or possible. The second technique, is to reduce toggles in your design. Make sure only registers that *have to* change, change. Make sure there is nothing toggling without any need. Use Clock Enables to enable and disable blocks when they are needed. Specially if you use counters, disable them when not needed. There should be absolutely nothing togeling when you are idle (well, I guess this is design dependent but you get my point ...:*) Hope this helps ! Cheers, rudi ---------------------------------------------- www.asics.ws - Solutions for your ASIC needs - ###### Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl From: leotran@att.net (Loi Tran) Subject: Re: Low power design References: X-Newsreader: News Xpress 2.01 Lines: 44 Message-ID: Date: Fri, 04 Oct 2002 04:56:58 GMT NNTP-Posting-Host: 12.86.232.230 X-Complaints-To: abuse@worldnet.att.net X-Trace: bgtnsc05-news.ops.worldnet.att.net 1033707418 12.86.232.230 (Fri, 04 Oct 2002 04:56:58 GMT) NNTP-Posting-Date: Fri, 04 Oct 2002 04:56:58 GMT Organization: AT&T Worldnet Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed1.cidera.com!Cidera!dca6-feed2.news.algx.net!allegiance!feed2.news.rcn.net!rcn!wn11feed!worldnet.att.net!bgtnsc05-news.ops.worldnet.att.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21618 In article , russelmann@hotmail.com (Rudolf Usselmann) wrote: >"skillwood" wrote in message > news:... >> Hi all, >> Can some one give me an introduction to low power SoC design . What is >> difference from an ordinary design and low power design in the design stage >> . Suppose I am designing a fsm based sequential logic , at which stage the >> "LOW POWER " Comes in . >> >> thanks >> skillie >Understand first when a CMOS device "burns" power: Each time a >node changes level (from 0 to 1; or from 2 to 0). [There is lot >more but thats typically controlled by the technology vendor, >use a LOW-POWER library if you are doing an ASIC ...] > >From the coding aspect, there are two things you can do: >1) Reduce the Clock speed >2) Reduce overall toggle rate > >To reduce the clock might not be easy if you are in an FPGA. If >you are using a DPLL in an FPGA you might be able to change the >clock rate. For example from "full speed" to "half speed". Make >sure clock change is synchronous and glitch free .... >The ultimate in "saving power" would be to turn the clock off all >together. This might not always be practical or possible. > >The second technique, is to reduce toggles in your design. Make >sure only registers that *have to* change, change. Make sure >there is nothing toggling without any need. Use Clock Enables >to enable and disable blocks when they are needed. Specially if >you use counters, disable them when not needed. There should be >absolutely nothing togeling when you are idle (well, I guess this >is design dependent but you get my point ...:*) > >Hope this helps ! > >Cheers, >rudi >---------------------------------------------- >www.asics.ws - Solutions for your ASIC needs - You could also stop the clock going to subsytems that aren't necessary at the time. ###### From: Petter Gustad Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: 04 Oct 2002 09:21:57 +0200 Organization: 502 You are not allowed to talk Lines: 17 Message-ID: References: <1033648940.927582@cswreg.cos.agilent.com> NNTP-Posting-Host: 195.0.185.86 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: oslo-nntp.eunet.no 1033716380 8213 195.0.185.86 (4 Oct 2002 07:26:20 GMT) X-Complaints-To: abuse@KPNQwest.no NNTP-Posting-Date: 4 Oct 2002 07:26:20 GMT User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!feed.news.nacamar.de!uninett.no!Norway.EU.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21633 "Ulises Hernandez" writes: > For me the interesting bit is the RTL coding, for a FSM as you said, you can > use one-hot encoding because only one-bit will change every clock (reduces > clock activity which is a killer in power consumption). If you change from One-hot encoding will cause *two* bits to change at each state transition. Grey-encoding will cause only one bit to change. However, in many cases it will be diffucult to make gray code for all state transitions. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter ###### From: "Ulises Hernandez" Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: Fri, 4 Oct 2002 09:34:13 +0100 Organization: ECS Technology Ltd. Lines: 40 Message-ID: <1033720463.137875@cswreg.cos.agilent.com> References: <1033648940.927582@cswreg.cos.agilent.com> Reply-To: "Ulises Hernandez" NNTP-Posting-Host: cswreg.cos.agilent.com X-Trace: cswtrans.cos.agilent.com 1033720463 18887 130.29.154.45 (4 Oct 2002 08:34:23 GMT) X-Complaints-To: usenet@cswtrans.cos.agilent.com NNTP-Posting-Date: Fri, 4 Oct 2002 08:34:23 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Cache-Post-Path: cswreg.cos.agilent.com!unknown@sqf3448.britain.agilent.com X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!telocity-west!TELOCITY!enews.sgi.com!sdd.hp.com!agilent.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21623 You are right Petter, Two bits change at each state in one-hot. I was probably thinking about Grey Code, as you said it's difficult to make grey code for all the transitions. I have heard that in your Memory Map the FW guys can change from binary to Grey Coding very easily in a uP, if your memoy map is massive this could reduce your power consumption, but it makes live more complicated, more difficult debug and more difficult coding in your VHDL. Good correction. Cheers Ulises Hernandez Design Enginner ECS Technology Ltd. www.ecs-tech.com "Petter Gustad" wrote in message news:m3u1k2vfca.fsf@scimul.dolphinics.no... > "Ulises Hernandez" writes: > > > For me the interesting bit is the RTL coding, for a FSM as you said, you can > > use one-hot encoding because only one-bit will change every clock (reduces > > clock activity which is a killer in power consumption). If you change from > > One-hot encoding will cause *two* bits to change at each state > transition. > > Grey-encoding will cause only one bit to change. However, in many > cases it will be diffucult to make gray code for all state > transitions. > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter ###### From: Petter Gustad Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: 04 Oct 2002 12:41:27 +0200 Organization: 502 You are not allowed to talk Lines: 16 Message-ID: References: <1033648940.927582@cswreg.cos.agilent.com> <1033720463.137875@cswreg.cos.agilent.com> NNTP-Posting-Host: 195.0.185.86 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: oslo-nntp.eunet.no 1033728350 7361 195.0.185.86 (4 Oct 2002 10:45:50 GMT) X-Complaints-To: abuse@KPNQwest.no NNTP-Posting-Date: 4 Oct 2002 10:45:50 GMT User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.tele.dk!small.news.tele.dk!195.54.122.107!newsfeed1.bredband.com!bredband!uio.no!Norway.EU.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21632 "Falk Brunner" writes: > Why more difficult? AFAIK every uptodate VHDL compiler offers a setting on > how to encode your FSMs. So in the code, you have only state names, NOT > encoded vectors. Make the thing much more readable. Your synthesis tool might have to add a lot of redundant bits to the states in order to make this happen. In some cases it might be difficult (for your synthesis tool that is). Imagine 10 states where there is a state transition from every single state to every other state. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter ###### Message-ID: <3D9D7554.9FD02FC8@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design References: <1033648940.927582@cswreg.cos.agilent.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 75 Date: Fri, 04 Oct 2002 11:03:32 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1033729412 68.15.41.165 (Fri, 04 Oct 2002 07:03:32 EDT) NNTP-Posting-Date: Fri, 04 Oct 2002 07:03:32 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!newspeer1-gui.server.ntli.net!ntli.net!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21613 A one-hot is pretty much minimal power for a decoded state machine. All the bits in a state machine necessarily have to have an even number of transitions in a complete cycle of the state machine. The one-hot puts both transitions in adjacent states. We've used a shft register style state machine where '1's get shifted in. Sort of like a sticky one-hot. While this reduces the number of input terms to each flip-flop, it only postpones the 1 to 0 transition to the end of the cycle. A grey coded machine is an encoded machine. It has fewer transitions (one per state instead of two) and less flip-flops so its power is less. Be aware that any gains in the state machine might be lost in the state decode, especially if there are not many 'hidden' states. A grey coded machine becomes difficult to design with many branches unless extra filler states are added, since every loop in the state diagram must have an even number of states. Ulises Hernandez wrote: > Hi, > > There are a lot of things to consider in a low power design. > > - Your core voltage (1.5V is a good figure) > - Packaging aspects (lower die tempearature, 'the hotter it runs, the > quicker it fails' :o) > - Metal Layers (passive silicon no longer dissipates/sink heat in these days > because there is no passive stuff) > - ... > - RTL code > > For me the interesting bit is the RTL coding, for a FSM as you said, you can > use one-hot encoding because only one-bit will change every clock (reduces > clock activity which is a killer in power consumption). If you change from > state A to state B more often than to state C try state A and B encoded with > low toggle rate ("most likely branch encoding"). Disabling your clock in > your IDLE state could be interesting (if you have the capability to do it) > and enable it with the scape condition. > There are a whole bunch of things you could do. > This Xilinx paper is quite interesting > http://www.xilinx.com/xcell/xl38/xcell38_40.pdf > Google also helps. > > Regards > > Ulises Hernandez > Design Enginner > ECS Technology Ltd. > www.ecs-tech.com > > "skillwood" wrote in message > news:anhas6$e4ro0$1@ID-159866.news.dfncis.de... > > Hi all, > > Can some one give me an introduction to low power SoC design . What is > > difference from an ordinary design and low power design in the design > stage > > . Suppose I am designing a fsm based sequential logic , at which stage > the > > "LOW POWER " Comes in . > > > > thanks > > skillie > > > > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Sender: artsb@volans Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design References: From: Bas Arts Organization: Philips Research Laboratories Eindhoven, The Netherlands Date: 04 Oct 2002 13:21:06 +0200 Message-ID: X-Newsreader: Gnus v5.6.45/XEmacs 21.1 - "Big Bend" Lines: 13 NNTP-Posting-Host: gw-ehv05.pnl.philips.com X-Trace: 1033730470 read-nat.news.nl.uu.net 229 212.153.190.4 X-Complaints-To: abuse@nl.uu.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news0.de.colt.net!peernews3.colt.net!colt.net!newspeer.clara.net!news.clara.net!oleane.net!oleane!bnewspeer00.bru.ops.eu.uu.net!bnewsifeed00.bru.ops.eu.uu.net!bnewspost00.bru.ops.eu.uu.net!emea.uu.net!read-nat.news.nl.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21607 > Can some one give me an introduction to low power SoC design . What is > difference from an ordinary design and low power design in the design stage > . Suppose I am designing a fsm based sequential logic , at which stage the > "LOW POWER " Comes in . Dependent on the type of design you are planning to design, you might also want to take a look at asynchronous design methods. If applicable, no synchronous method can give you less power consumption. -- greetz, |\_____---_____ Bas |/ (__|||__) """ ###### From: MR Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: Fri, 04 Oct 2002 09:38:23 -0700 Organization: Cisco Systems Inc. Message-ID: <3D9DC3FF.1040108@gtemail.net> User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:0.9.4.1) Gecko/20020508 Netscape6/6.2.3 X-Accept-Language: en-us MIME-Version: 1.0 References: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Cache-Post-Path: sj-nntpcache-3!unknown@rohm-lnx.cisco.com X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) X-Complaints-To: abuse@supernews.com Lines: 18 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!psinet-eu-nl!news-x2.support.nl!skynet.be!skynet.be!sn-xit-03!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21610 I second this notion. The typical CMOS clock tree can consume 30% of the total chip power. If you want to cut power, look for ways to reduce the number of clocked elements. Bas Arts wrote: >> Can some one give me an introduction to low power SoC design . What is >>difference from an ordinary design and low power design in the design stage >>. Suppose I am designing a fsm based sequential logic , at which stage the >>"LOW POWER " Comes in . >> > > Dependent on the type of design you are planning to design, you might also want > to take a look at asynchronous design methods. If applicable, no synchronous > method can give you less power consumption. > > ###### From: Ole User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.2a) Gecko/20020910 X-Accept-Language: en-us, en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design References: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Lines: 25 Message-ID: NNTP-Posting-Host: 64.170.116.193 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr13.news.prodigy.com 1033795384 ST000 64.170.116.193 (Sat, 05 Oct 2002 01:23:04 EDT) NNTP-Posting-Date: Sat, 05 Oct 2002 01:23:04 EDT Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: [[PAPDCA[S@KRQXX]ZHXOFXBWR\HPCTL@XT^OBPLAH[\RSAANVUEAE[YETZPIWWI[FCIZA^NBFXZ_D[BFNTCNVPDTNTKHWXKB@X^B_OCJLPZ@ET_O[G\XSG@E\G[ZKVLBL^CJINM@I_KVIOR\T_M_AW_M[_BWU_HFA_]@A_A^SGFAUDE_DFTMQPFWVW[QPJN Date: Sat, 05 Oct 2002 05:23:04 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!uni-erlangen.de!newsfeed1.telenordia.se!algonet!news01.chello.se!newsfeed1.bredband.com!bredband!news.tele.dk!small.news.tele.dk!207.115.63.138!newscon04.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr13.news.prodigy.com.POSTED!dfcf54f5!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21652 Rudolf Usselmann wrote: > Understand first when a CMOS device "burns" power: Each time a > node changes level (from 0 to 1; or from 2 to 0). [There is lot > more but thats typically controlled by the technology vendor, > use a LOW-POWER library if you are doing an ASIC ...] > > From the coding aspect, there are two things you can do: > 1) Reduce the Clock speed > 2) Reduce overall toggle rate > ---------------------------------------------- > www.asics.ws - Solutions for your ASIC needs - Remember the power consumed per transition is proportional to the capacitance of the net. Minimizing the transitions of a FSM will rarely minimize the power. More often than not, a state encoding that gives good power and timing will also be a good encoding for power. (letting the synthesis tool pick the state encoding will almost always give a better encoding than a hand choosen encoding - I then hard code the encodings back into the rtl to make gate sims match and simplify ecos) -- Dr. Eric Olson ###### From: rickman Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: Sat, 05 Oct 2002 04:45:55 -0400 Organization: Arius, Inc Lines: 55 Message-ID: <3D9EA6C3.2CADF289@yahoo.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVb9nEoQ3z6L65A+yGh9XccVf9iY3nG2WDSuKF6clsgHCmSJXzPJAj89 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 5 Oct 2002 08:45:52 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21653 Ole wrote: > > Rudolf Usselmann wrote: > > Understand first when a CMOS device "burns" power: Each time a > > node changes level (from 0 to 1; or from 2 to 0). [There is lot > > more but thats typically controlled by the technology vendor, > > use a LOW-POWER library if you are doing an ASIC ...] > > > > From the coding aspect, there are two things you can do: > > 1) Reduce the Clock speed > > 2) Reduce overall toggle rate > > > ---------------------------------------------- > > www.asics.ws - Solutions for your ASIC needs - > > Remember the power consumed per transition is proportional to the > capacitance of the net. Minimizing the transitions of a FSM will > rarely minimize the power. More often than not, a state encoding > that gives good power and timing will also be a good encoding for > power. (letting the synthesis tool pick the state encoding will > almost always give a better encoding than a hand choosen encoding > - I then hard code the encodings back into the rtl to make gate sims > match and simplify ecos) > > -- > Dr. Eric Olson I don't agree with this. If the state encoding uses 6 bits, the average number of bits changing will be more than two most likely. In addition the number of LUTs used on each bit will be greater since the logic will be more complex. With one hot encoding the number of bits is larger, but each transition only changes two bits. And the logic feeding the bit is normally very simple using very few LUTs. Unless the state machine is some degenerate case that just does not map at all well to a one hot encoding, this should always produce a near optimal design for power consumption. In the cases where the natual state machine does not map well to one hot encoding (such as states with many input transitions) you can always use state splitting to reduce the complexity of any give state. Then your only degenerate FSM becomes one with nearly all states transitioning to nearly every other state. Not many FSMs of any size are constructed that way. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Helmut Sennewald" Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: Sat, 5 Oct 2002 11:42:47 +0200 Organization: T-Online Lines: 41 Message-ID: References: <1033648940.927582@cswreg.cos.agilent.com> <3D9D7554.9FD02FC8@andraka.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1033810969 07 24557 1k-NbtWVSPYIaw 021005 09:42:49 X-Complaints-To: abuse@t-online.com X-Sender: 340021327918-0001@t-dialin.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.com!t-online.de!news.t-online.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21659 "Ray Andraka" schrieb im Newsbeitrag news:3D9D7554.9FD02FC8@andraka.com... > A one-hot is pretty much minimal power for a decoded state machine. All the > bits in a state machine necessarily have to have an even number of transitions > in a complete cycle of the state machine. The one-hot puts both transitions in > adjacent states. We've used a shft register style state machine where '1's get > shifted in. Sort of like a sticky one-hot. While this reduces the number of > input terms to each flip-flop, it only postpones the 1 to 0 transition to the > end of the cycle. A grey coded machine is an encoded machine. It has fewer > transitions (one per state instead of two) and less flip-flops so its power is > less. Be aware that any gains in the state machine might be lost in the state > decode, especially if there are not many 'hidden' states. A grey coded machine > becomes difficult to design with many branches unless extra filler states are > added, since every loop in the state diagram must have an even number of states. > Hello Ray, I have read here a lot about the power savings in the area of the flipflops used in the state machine, but all have forgotten that there is a lot of logic around the state flipflops which also change its level. Normally there are lots of AND and OR gates feeding the state flipflops. Especially the gray coder could dissipate more power than the less changing flipflops will save. Have anybody really measured any numbers in a real circuit? Best Regards Helmut ###### Message-ID: <3D9EE675.D82A8BFA@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design References: <1033648940.927582@cswreg.cos.agilent.com> <3D9D7554.9FD02FC8@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 61 Date: Sat, 05 Oct 2002 13:18:27 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1033823907 68.15.41.165 (Sat, 05 Oct 2002 09:18:27 EDT) NNTP-Posting-Date: Sat, 05 Oct 2002 09:18:27 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!solnet.ch!solnet.ch!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21654 I sort of alluded to that. In an FPGA it is even more true, as the routes also consume power. I like the shift register (bar graph) type machines because they minimize the logic leading into each state since the next state only needs an equation for set, not for reset. Unfortunately, they are a bit more obtuse to code and the synthesizers generally don't have them as an option style. They also are convenient for the SRL16 primitives. Helmut Sennewald wrote: > "Ray Andraka" schrieb im Newsbeitrag > news:3D9D7554.9FD02FC8@andraka.com... > > A one-hot is pretty much minimal power for a decoded state machine. All > the > > bits in a state machine necessarily have to have an even number of > transitions > > in a complete cycle of the state machine. The one-hot puts both > transitions in > > adjacent states. We've used a shft register style state machine where > '1's get > > shifted in. Sort of like a sticky one-hot. While this reduces the number > of > > input terms to each flip-flop, it only postpones the 1 to 0 transition to > the > > end of the cycle. A grey coded machine is an encoded machine. It has > fewer > > transitions (one per state instead of two) and less flip-flops so its > power is > > less. Be aware that any gains in the state machine might be lost in the > state > > decode, especially if there are not many 'hidden' states. A grey coded > machine > > becomes difficult to design with many branches unless extra filler states > are > > added, since every loop in the state diagram must have an even number of > states. > > > > Hello Ray, > I have read here a lot about the power savings in the area of > the flipflops used in the state machine, but all have forgotten > that there is a lot of logic around the state flipflops which also > change its level. Normally there are lots of AND and OR gates > feeding the state flipflops. Especially the gray coder could > dissipate more power than the less changing flipflops will save. > Have anybody really measured any numbers in a real circuit? > > Best Regards > Helmut -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: russelmann@hotmail.com (Rudolf Usselmann) Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: 5 Oct 2002 07:08:32 -0700 Organization: http://groups.google.com/ Lines: 37 Message-ID: References: NNTP-Posting-Host: 203.152.41.201 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1033826913 24118 127.0.0.1 (5 Oct 2002 14:08:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 5 Oct 2002 14:08:33 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21663 Ole wrote in message news:... > Rudolf Usselmann wrote: > > Understand first when a CMOS device "burns" power: Each time a > > node changes level (from 0 to 1; or from 2 to 0). [There is lot > > more but thats typically controlled by the technology vendor, > > use a LOW-POWER library if you are doing an ASIC ...] > > > > From the coding aspect, there are two things you can do: > > 1) Reduce the Clock speed > > 2) Reduce overall toggle rate > > > ---------------------------------------------- > > www.asics.ws - Solutions for your ASIC needs - > > Remember the power consumed per transition is proportional to the > capacitance of the net. Minimizing the transitions of a FSM will > rarely minimize the power. More often than not, a state encoding > that gives good power and timing will also be a good encoding for > power. (letting the synthesis tool pick the state encoding will > almost always give a better encoding than a hand choosen encoding > - I then hard code the encodings back into the rtl to make gate sims > match and simplify ecos) Well, Dr. Eric Olson, Dr. R. Usselmann disagrees with the second part of your statement :*). The optimal state encoding will depend on the usage of the FSM and many other factors.I'm not sure I agree with you that a tool can chose the best encoding for me either. Definitely not Synplify. Synopsys Design Compiler, hmm, I'd trust it more. Not sure how long you have been writing RTL, but my "gut feeling" enables me to chose the best encoding style 90% of the time. In any case, I have originally stated it all boils down to your toggle rate ! Best Regards, rudi ---------------------------------------------- www.asics.ws - Solutions for your ASIC needs - ###### Message-ID: <3DA0D7B5.1FCBC003@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Low power design References: <1033648940.927582@cswreg.cos.agilent.com> <3D9D7554.9FD02FC8@andraka.com> <3D9EE675.D82A8BFA@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 121 Date: Mon, 07 Oct 2002 00:40:00 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1033951200 68.15.41.165 (Sun, 06 Oct 2002 20:40:00 EDT) NNTP-Posting-Date: Sun, 06 Oct 2002 20:40:00 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news-mue1.dfn.de!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21692 There are a number of high current things in the FPGA. First, the static current is relatively high. The clock tree dissipates quite a bit of power because unlike an ASIC it goes to every CLB (columns can be turned off in some devices). Data transitions, however, are the Lion's share of the power dissipation. This can be demonstrated by observing the power when the clock is running but the design is held in an idle state (no data moving through it) and when it is no longer idle. In designs with high clock rates, the current change can be 10x or more. Actually, an interesting paper last year at FPGA claims that a large percentage of that power is due to the combinatorial glitching after the clock edge. In the FPGA, that can lead to a large number of nodes switching several times per clock cycle, especially where there are multiple levels of logic between flip-flops. That is aggrabated by long routes on those paths as well, since the routes in an FPGA include active switches. The degree of that intra-clock switching is obviously design dependent. What it does say is that keeping logic levels to a minimum (deeper pipelining), and floorplanning to all routing as short as practical are important to reducing power. I have seen a pretty consistent power savings of around 20% achieved by floorplanning, which seems to confirm the findings in the paper that power dissipation in the routing is a significant part of the overall power. Most of our designs already have just a single level of logic between flip-flops (we do that for performance and for floorplanning reasons), so I can't really collaborate that finding. The bottom line is that the same techiques used to achieve maximum performance also reduce power consumption. malgi wrote: > I designed FPGAs once upon a time, and the majority of the power was taken up by: > > a) the flops and clock tree > b) the large drivers out onto the bus routing network > > I used spice to determine this, and verified it by measuring power consumption of > hand built bitstreams. > > The LUTs and local logic are really too small in drive value into too small a capacitance > to really mean much in terms of power consumption. > > My gut says, keep the number of flops*toggle rate at a minimum. Keep the circuits as > small as possible, and floorplan the logic blocks to keep the routes down. I wouldn't worry > too much about the rest. > > Bob > > If you're still over power budget, then you may need Ray's advice. > > "Ray Andraka" wrote in message news:3D9EE675.D82A8BFA@andraka.com... > > I sort of alluded to that. In an FPGA it is even more true, as the routes > > also consume power. I like the shift register (bar graph) type machines > > because they minimize the logic leading into each state since the next state > > only needs an equation for set, not for reset. Unfortunately, they are a bit > > more obtuse to code and the synthesizers generally don't have them as an option > > style. They also are convenient for the SRL16 primitives. > > > > Helmut Sennewald wrote: > > > > > "Ray Andraka" schrieb im Newsbeitrag > > > news:3D9D7554.9FD02FC8@andraka.com... > > > > A one-hot is pretty much minimal power for a decoded state machine. All > > > the > > > > bits in a state machine necessarily have to have an even number of > > > transitions > > > > in a complete cycle of the state machine. The one-hot puts both > > > transitions in > > > > adjacent states. We've used a shft register style state machine where > > > '1's get > > > > shifted in. Sort of like a sticky one-hot. While this reduces the number > > > of > > > > input terms to each flip-flop, it only postpones the 1 to 0 transition to > > > the > > > > end of the cycle. A grey coded machine is an encoded machine. It has > > > fewer > > > > transitions (one per state instead of two) and less flip-flops so its > > > power is > > > > less. Be aware that any gains in the state machine might be lost in the > > > state > > > > decode, especially if there are not many 'hidden' states. A grey coded > > > machine > > > > becomes difficult to design with many branches unless extra filler states > > > are > > > > added, since every loop in the state diagram must have an even number of > > > states. > > > > > > > > > > Hello Ray, > > > I have read here a lot about the power savings in the area of > > > the flipflops used in the state machine, but all have forgotten > > > that there is a lot of logic around the state flipflops which also > > > change its level. Normally there are lots of AND and OR gates > > > feeding the state flipflops. Especially the gray coder could > > > dissipate more power than the less changing flipflops will save. > > > Have anybody really measured any numbers in a real circuit? > > > > > > Best Regards > > > Helmut > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 > > > > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Sender: artsb@mollis Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design References: From: Bas Arts Organization: Philips Research Laboratories Eindhoven, The Netherlands Date: 07 Oct 2002 09:19:28 +0200 Message-ID: X-Newsreader: Gnus v5.6.45/XEmacs 21.1 - "Big Bend" Lines: 16 NNTP-Posting-Host: gw-ehv05.pnl.philips.com X-Trace: 1033975173 read-nat.news.nl.uu.net 226 212.153.190.4 X-Complaints-To: abuse@nl.uu.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news-hub.siol.net!bnewsfeed00.bru.ops.eu.uu.net!bnewsifeed00.bru.ops.eu.uu.net!bnewspost00.bru.ops.eu.uu.net!emea.uu.net!read-nat.news.nl.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21690 Bas Arts writes: > > Can some one give me an introduction to low power SoC design . What is > > difference from an ordinary design and low power design in the design stage > > . Suppose I am designing a fsm based sequential logic , at which stage the > > "LOW POWER " Comes in . > > Dependent on the type of design you are planning to design, you might also want > to take a look at asynchronous design methods. If applicable, no synchronous > method can give you less power consumption. also, take a look at http://www.embedded.com/OEG20020913S0060 -- greetz, |\_____---_____ Bas |/ (__|||__) """ ###### From: "Ulises Hernandez" Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: Mon, 7 Oct 2002 11:08:14 +0100 Organization: ECS Technology Ltd. Lines: 60 Message-ID: <1033985306.125254@cswreg.cos.agilent.com> References: Reply-To: "Ulises Hernandez" NNTP-Posting-Host: cswreg.cos.agilent.com X-Trace: cswtrans.cos.agilent.com 1033985306 23990 130.29.154.45 (7 Oct 2002 10:08:26 GMT) X-Complaints-To: usenet@cswtrans.cos.agilent.com NNTP-Posting-Date: Mon, 7 Oct 2002 10:08:26 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Cache-Post-Path: cswreg.cos.agilent.com!unknown@sqf3448.britain.agilent.com X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!logbridge.uoregon.edu!ihnp4.ucsd.edu!sdd.hp.com!agilent.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21705 Hi Skilwood, Thanks for considering me a veteran, but I am still a young chap trying to work in this tough business in these years :o) and have a lot of things to learn from Ray, Rudolf, Peter Alfke and all these guys... Anyway, PowerTheatre (SEQUENCE tool), it is used in ASIC design, and it stimates the power consumed in your design using your RTL code. You can get a dirty first stimation only loading your RTL code, and a 'scenario technology' (for example 1.8V 0.18u technology, normally these libraries are specific to your ASIC silicon vendor). You can also add a VCD (Value Change Dump format) file, this file is an output of most os the simulation tools (Modelsim...) and it gives PowerTheatre stimation of your signals' toggling rate. As you see is dependant of your testbench, it gives you very detailed information about power consumption, for each entity you get a figure. You can also do a gate-simulation. There are some tips you get from the tool to optimise power like RAM splitting, enabling/disabling areas, encoding... I wonder if these libraries are available for FPGAs, it would be great but I guess is rather difficult to stimate that in SRAM based designs. More info: http://www.sequencedesign.com/2_solutions/2b_power_theater.html I hope it helps. Ulises Hernandez Design Enginner ECS Technology Ltd. www.ecs-tech.com "skillwood" wrote in message news:anrjtk$gu67t$1@ID-159866.news.dfncis.de... > Hi all, > > Can somebody answer this question ?? > > > > I saw the whole discussion, but I would be extremely gratefule if some > one > >could some resource as to what are the rules to be followed , while > >implementing low power designs in behavioral modeling. > > > > Is there a way to find the power consumption during the running. during > hdl > >simulation/ or is it necessary to perform spice simulations. > > Hope veterans like Ray Andraka, Ulises , Rudolf and others will come with > an answer. > > thanks > skillie > > > > ###### From: "Caillet" Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: Mon, 7 Oct 2002 17:16:51 +0200 Organization: Swisscom IP+ (post doesn't reflect views of Swisscom) Lines: 61 Message-ID: References: NNTP-Posting-Host: 212.243.58.174 X-Trace: rex.ip-plus.net 1034003798 7408 212.243.58.174 (7 Oct 2002 15:16:38 GMT) X-Complaints-To: abuse@ip-plus.net NNTP-Posting-Date: Mon, 7 Oct 2002 15:16:38 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21697 "skillwood" wrote in message news:... > Hi all, > Can some one give me an introduction to low power SoC design . What is > difference from an ordinary design and low power design in the design stage > . Suppose I am designing a fsm based sequential logic , at which stage the > "LOW POWER " Comes in . > > thanks > skillie To do a ASIC low power, 1-you choose a technology with a very low voltage around 1V 2-you try to reduce as you can the clock frequency [remember the power is Cp*F*V*V] 3-applied a gated-clock strategy 4-best way gated-power strategy If you want some power computing and so some high speed, try to work with some standart cells define with two voltage, the low voltage for the block-low speed, and the high voltage for the block-high speed (tools from Synopsys can do that) 5-Use PowerCompiler to generate a better netlist after your synthesis (witha VCD-SAIF file) 6-In your code try to reduce the number of register... 7-You can use for FSM the Grey code, the impact is not so important. . Good luck for your design, Regis PS : in the conference ISSCC2001, there is a good presentation on Low Power Technique : "Low Power Design Techniques for Microprocessors " ISSCC, Feb4th 2001 Simon Segard VP Engineerring, ARM Inc. ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga,comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi.cad Subject: Re: Low power design Date: Mon, 7 Oct 2002 16:17:28 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 12 Message-ID: References: NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1034007448 4609 128.32.112.203 (7 Oct 2002 16:17:28 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Mon, 7 Oct 2002 16:17:28 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21700 In article , Caillet wrote: >To do a ASIC low power, .... 8- Pipeline and parallelize as much as you damn well can. Since P ~= cv^2F, you want to pipeline heavily, then back off the clock, then take advantage of the lower clock but short stages to drop the voltage even further. -- Nicholas C. Weaver nweaver@cs.berkeley.edu