From: "Theron Hicks" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: USB2 in FPGA? Date: Tue, 1 Oct 2002 15:49:55 -0400 Organization: Michigan State University Lines: 14 Message-ID: NNTP-Posting-Host: dfti.egr.msu.edu X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!news.belwue.de!news.uni-stuttgart.de!news.iesy.de!troll.iesy.de!newsfeed.wirehub.nl!news.tele.dk!small.news.tele.dk!129.250.35.146!iad-peer.news.verio.net!news.verio.net!solaris.cc.vt.edu!news.vt.edu!msunews!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21508 Hello, I am developing an instrument that is currently communicating over a special high speed parallel board. The data rate is 6.4 million 8 bit words per second. The board works great but it costs in excess of $1600 US per copy. It also occupies a full sized PCI slot. We are considering implementing an alternative I/O arrangement such as USB2 or ethernet (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if absolutely necessary, Virtex2). Thanks, Theron ###### Message-ID: <3D99FE74.28F1@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 Date: Wed, 02 Oct 2002 07:58:44 +1200 NNTP-Posting-Host: 203.79.98.7 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1033502464 203.79.98.7 (Wed, 02 Oct 2002 08:01:04 NZST) NNTP-Posting-Date: Wed, 02 Oct 2002 08:01:04 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!howland.erols.net!cyclone-sf.pbi.net!216.218.192.242!news.he.net!news-out.spamkiller.net!propagator2-maxim!news-in.spamkiller.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21506 Theron Hicks wrote: > > Hello, > I am developing an instrument that is currently communicating over a > special high speed parallel board. The data rate is 6.4 million 8 bit words > per second. The board works great but it costs in excess of $1600 US per > copy. It also occupies a full sized PCI slot. We are considering > implementing an alternative I/O arrangement such as USB2 or ethernet > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > absolutely necessary, Virtex2). USB2 to-the-pins is likely to be a big ask, and probably not cost effective. IIRC Philips have a USB2 <-> FIFO interface, that does all the PHY and lowest layer bit serial stuff, giving the user a 30MHz 16 bit FIFO interface. Then Cypress, and TI have USB2 controllers, which are TurboC51 + USB2, and these have DMA schemes for similar 16 bit interface speeds. There are also USB2-ATA bridge devices, again mostly with C51 cores. There are USB2 links from our page http://www.designtools.co.nz/overview.htm -jg ###### From: "Paul Baxter" Newsgroups: comp.arch.fpga,comp.lang.vhdl References: Subject: Re: USB2 in FPGA? Date: Tue, 1 Oct 2002 21:07:44 +0100 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Lines: 22 Message-ID: <3d9a0049$0$8514$cc9e4d1f@news.dial.pipex.com> NNTP-Posting-Host: userda153.dsl.pipex.com X-Trace: 1033502793 news.dial.pipex.com 8514 62.190.224.153 X-Complaints-To: abuse@uk.uu.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!psinet-eu-nl!news-x2.support.nl!cleanfeed.casema.net!leda.casema.net!bnewspeer01.bru.ops.eu.uu.net!bnewsifeed03.bru.ops.eu.uu.net!lnewspost00.lnd.ops.eu.uu.net!emea.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21510 www.opencores.com is a brilliant place to bookmark. They even have a USB2 core :) "Theron Hicks" wrote in message news:anctr2$2brl$1@msunews.cl.msu.edu... > Hello, > I am developing an instrument that is currently communicating over a > special high speed parallel board. The data rate is 6.4 million 8 bit words > per second. The board works great but it costs in excess of $1600 US per > copy. It also occupies a full sized PCI slot. We are considering > implementing an alternative I/O arrangement such as USB2 or ethernet > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > absolutely necessary, Virtex2). > > Thanks, > Theron > > ###### From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? Date: Tue, 01 Oct 2002 16:08:43 -0400 Organization: Arius, Inc Lines: 35 Message-ID: <3D9A00CB.BBD63D45@yahoo.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZU1/XfzABZVt6h/9d++Z+JfYvM2NpzRC7Y2MiKft6++OYBjU2+vJYe X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Oct 2002 20:08:44 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed1.cidera.com!Cidera!dca6-feed2.news.algx.net!allegiance!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21503 Theron Hicks wrote: > > Hello, > I am developing an instrument that is currently communicating over a > special high speed parallel board. The data rate is 6.4 million 8 bit words > per second. The board works great but it costs in excess of $1600 US per > copy. It also occupies a full sized PCI slot. We are considering > implementing an alternative I/O arrangement such as USB2 or ethernet > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > absolutely necessary, Virtex2). > > Thanks, > Theron I know you asked for an FPGA core, but did you try going back to your board supplier and explaining to them the cost problem? If you are using sufficient quantities to justify a design change, I would bet they would be willing to come down on the price if they knew they would be losing a high volume customer. I don't know what is on the parallel board, but I bet it can be sold for well, well under $1600. Unless it has a large Virtex II part :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Theron Hicks (Terry)" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? Date: Tue, 01 Oct 2002 21:40:56 -0400 Organization: Michigan State University Lines: 53 Message-ID: <3D9A4EA8.7EBE1AFE@egr.msu.edu> References: <3D9A00CB.BBD63D45@yahoo.com> NNTP-Posting-Host: pm794-23.dialip.mich.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-AUTHid: hicksthe X-Mailer: Mozilla 4.51 [en] (WinNT; I) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!iad-peer.news.verio.net!news.verio.net!solaris.cc.vt.edu!news.vt.edu!msunews!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21523 Thanks to all of you for your advice and comments. The $1600 board is a little overkill for my application, but I need a board that will pass 16 bits at 3.2 MHz. It is actually a DATEL A/D board with an unpopulated converter. Having dealt with a cheaper and very inferior (and unreliable) board earlier in the project (at ~$200) I was very concerned about poor reliability in the hands of our customer. (So why am I going to a custom USB2 interface??? Sometimes I am not sure that I should.) In addition the quantities are quite small at this time (5 to 20 units per year?) However, at $1600 if I can put together a cheap USB2 solution then I can generate a little more profit for a start-up company on a shoe-string budget. The dedicated chip has some real possibilities and the Phillips chip sounds especially interesting. Thanks, Theron Hicks rickman wrote: > Theron Hicks wrote: > > > > Hello, > > I am developing an instrument that is currently communicating over a > > special high speed parallel board. The data rate is 6.4 million 8 bit words > > per second. The board works great but it costs in excess of $1600 US per > > copy. It also occupies a full sized PCI slot. We are considering > > implementing an alternative I/O arrangement such as USB2 or ethernet > > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > > absolutely necessary, Virtex2). > > > > Thanks, > > Theron > > I know you asked for an FPGA core, but did you try going back to your > board supplier and explaining to them the cost problem? If you are > using sufficient quantities to justify a design change, I would bet they > would be willing to come down on the price if they knew they would be > losing a high volume customer. I don't know what is on the parallel > board, but I bet it can be sold for well, well under $1600. Unless it > has a large Virtex II part :) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX ###### From: russelmann@hotmail.com (Rudolf Usselmann) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? Date: 1 Oct 2002 19:36:21 -0700 Organization: http://groups.google.com/ Lines: 34 Message-ID: References: <3d9a0049$0$8514$cc9e4d1f@news.dial.pipex.com> NNTP-Posting-Host: 203.152.41.201 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1033526181 28197 127.0.0.1 (2 Oct 2002 02:36:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 2 Oct 2002 02:36:21 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21548 "Paul Baxter" wrote in message news:<3d9a0049$0$8514$cc9e4d1f@news.dial.pipex.com>... > www.opencores.com is a brilliant place to bookmark. They even have a USB2 > core :) Paul ! How could you ?! You beat me to it ! Thats my line ! ;*) BTW, you will need an external single chip PHY with the OpenCores USB 2.0 IP core. Check out Agere(sic?) and SMCS web sites for PHYs. The USB 2.0 core is currently being tested by another customer of mine with an Spartan 2e ... Best Regards, rudi ---------------------------------------------- www.asics.ws - Solutions for your ASIC needs - > "Theron Hicks" wrote in message > news:anctr2$2brl$1@msunews.cl.msu.edu... > > Hello, > > I am developing an instrument that is currently communicating over a > > special high speed parallel board. The data rate is 6.4 million 8 bit > words > > per second. The board works great but it costs in excess of $1600 US per > > copy. It also occupies a full sized PCI slot. We are considering > > implementing an alternative I/O arrangement such as USB2 or ethernet > > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > > absolutely necessary, Virtex2). > > > > Thanks, > > Theron > > > > ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? References: <3d9a0049$0$8514$cc9e4d1f@news.dial.pipex.com> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 01 Oct 2002 21:42:18 -0700 Message-ID: Lines: 5 User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 209.66.107.17 X-Trace: 1 Oct 2002 22:01:51 -0700, 209.66.107.17 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!arclight.uoregon.edu!enews.sgi.com!news.spies.com!209.66.107.17 Xref: chonsp.franklin.ch comp.arch.fpga:21537 russelmann@hotmail.com (Rudolf Usselmann) writes: > The USB 2.0 core is currently being tested by another customer of > mine with an Spartan 2e ... How many LUTs does the USB 2.0 core require? ###### From: russelmann@hotmail.com (Rudolf Usselmann) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? Date: 3 Oct 2002 00:45:26 -0700 Organization: http://groups.google.com/ Lines: 29 Message-ID: References: <3d9a0049$0$8514$cc9e4d1f@news.dial.pipex.com> NNTP-Posting-Host: 203.152.41.201 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1033631126 30858 127.0.0.1 (3 Oct 2002 07:45:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 3 Oct 2002 07:45:26 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!paloalto-snf1.gtei.net!news.gtei.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21593 Eric Smith wrote in message news:... > russelmann@hotmail.com (Rudolf Usselmann) writes: > > The USB 2.0 core is currently being tested by another customer of > > mine with an Spartan 2e ... > > How many LUTs does the USB 2.0 core require? It depends on the configuration of the core. But to give you a basic idea: USB 2.0 with 4 endpoints: part: xc2s200e pq208-6 Total LUTs: 2837 (60%) clk_i 107.2 MHz phy_clk_pad_i 67.3 MHz (required 60MHz) USB 1.1 (including usb 1.1 PHY, with 8 endpoints but no endpoint FIFOs): part: xc2s200e ft256-6 Total LUTs: 876 (18%) clk_i 4.2 MHz (required 48MHz) Hope this helps ! Best regards, rudi ---------------------------------------------- www.asics.ws - Solutions for your ASIC needs - ###### Reply-To: "Martin Euredjian" <0_0_0_0_@pacbell.net> From: "Martin Euredjian" <0_0_0_0_@pacbell.net> Newsgroups: comp.arch.fpga,comp.lang.vhdl References: Subject: Re: USB2 in FPGA? Lines: 47 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: NNTP-Posting-Host: 64.170.224.250 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr21.news.prodigy.com 1033665950 ST000 64.170.224.250 (Thu, 03 Oct 2002 13:25:50 EDT) NNTP-Posting-Date: Thu, 03 Oct 2002 13:25:50 EDT Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: SCSGW\KE\RUYRPLYNCOF_W\@PJ_^PBQLGPQRZUEK@YUDUWYAKVUOPCW[ML\JXUCKVFDYZKBMSFX^OMSAFNTINTDDMVW[X\THOPXZRVOCJTUTPC\_JSBVX\KAOTBAJBVMZTYAKMNLDI_MFDSSOLXINH__FS^\WQGHGI^C@E[A_CF\AQLDQ\BTMPLDFNVUQ_VM Date: Thu, 03 Oct 2002 17:25:50 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news-mue1.dfn.de!newsfeed.stueberl.de!news-out.cwix.com!newsfeed.cwix.com!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr21.news.prodigy.com.POSTED!003b42bf!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21567 This is a bit far fetched, but might work very nicely for your application. Have you thought of using DVI I/O chips? DVI is a relatively recent connectivity methodology for computer displays. It is, in escence, serialized 8 bit RGB. A single link can deliver in the order of 5 or 6 Gigabits per second, if I recall. The chips (both TX and RX) are less than ten bucks a piece. You can certainly clock DVI at less then the max single link 165 MHz rate and transport your data to via a serial link. I think the chips will go down to 25 MHz clocking. At low data rates you can probably go many more feet than the standard provides for. Heck, you could have three redundant links delivered over a commodity cable. Anyhow, just a thought. Check out the Silicon Image site for more details: http://www.siimage.com/home.asp HTH, -- Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Theron Hicks" wrote in message news:anctr2$2brl$1@msunews.cl.msu.edu... > Hello, > I am developing an instrument that is currently communicating over a > special high speed parallel board. The data rate is 6.4 million 8 bit words > per second. The board works great but it costs in excess of $1600 US per > copy. It also occupies a full sized PCI slot. We are considering > implementing an alternative I/O arrangement such as USB2 or ethernet > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > absolutely necessary, Virtex2). > > Thanks, > Theron > > ###### From: russelmann@hotmail.com (Rudolf Usselmann) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? Date: 3 Oct 2002 18:13:20 -0700 Organization: http://groups.google.com/ Lines: 37 Message-ID: References: <3d9a0049$0$8514$cc9e4d1f@news.dial.pipex.com> NNTP-Posting-Host: 203.152.41.201 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1033694000 29074 127.0.0.1 (4 Oct 2002 01:13:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 4 Oct 2002 01:13:20 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21636 russelmann@hotmail.com (Rudolf Usselmann) wrote in message news:... > Eric Smith wrote in message news:... > > russelmann@hotmail.com (Rudolf Usselmann) writes: > > > The USB 2.0 core is currently being tested by another customer of > > > mine with an Spartan 2e ... > > > > How many LUTs does the USB 2.0 core require? > > > It depends on the configuration of the core. But to > give you a basic idea: > > USB 2.0 with 4 endpoints: > part: xc2s200e pq208-6 > Total LUTs: 2837 (60%) > clk_i 107.2 MHz > phy_clk_pad_i 67.3 MHz (required 60MHz) > > > USB 1.1 (including usb 1.1 PHY, with 8 endpoints but no > endpoint FIFOs): > part: xc2s200e ft256-6 > Total LUTs: 876 (18%) > clk_i 4.2 MHz (required 48MHz) Sorry this should have been 74.2Mhz (not 4.2 ;*) rudi ---------------------------------------------- www.asics.ws - Solutions for your ASIC needs - > > Hope this helps ! > Best regards, > rudi > ---------------------------------------------- > www.asics.ws - Solutions for your ASIC needs - ###### From: Bassman59a@yahoo.com (Andy Peters) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? Date: 7 Oct 2002 16:28:05 -0700 Organization: http://groups.google.com/ Lines: 25 Message-ID: <9a2c3a75.0210071528.17ed50f2@posting.google.com> References: NNTP-Posting-Host: 24.221.131.16 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1034033285 16811 127.0.0.1 (7 Oct 2002 23:28:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 7 Oct 2002 23:28:05 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21767 "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:... > Anyhow, just a thought. Check out the Silicon Image site for more details: > http://www.siimage.com/home.asp Good luck getting tech support from them. Unless, of course, your e-mail address ends in dell.com, or something. If you call their main phone number, you get dumped into a black hole. I tried to get a data sheet from them for one of their ATAPI controller chips, and the person at the switchboard didn't even know where to route my call. I finally got ahold of someone in sales, who told me that my REP (!) would have the datasheet. So, I called the rep, who said, "Huh?" A couple of days later, the rep's field apps guy called, and I told him that I wasn't going to even consider using one of their products in a design. I said that if I designed in a complex part without a direct line to vendor tech support, my boss would chew my ass all along I-8. Which is true. --ap ###### Message-ID: <3DA21E5F.8DD5ED3@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 36 Date: Mon, 07 Oct 2002 23:53:44 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034034824 68.15.41.165 (Mon, 07 Oct 2002 19:53:44 EDT) NNTP-Posting-Date: Mon, 07 Oct 2002 19:53:44 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21739 A while back we considered USB in the FPGA, but when push came to shove, it was cheaper to use an external USB chip. In our case, it was the original USB, and we used a National Semi chip, I think it was a USBN9603 which has both the controller and the PHY in one package for about $2.25. When we sized the USB for putting in the FPGA we still needed an external PHY, and it would have pushed us into a larger part costing far more than the off the shelf chip. I don't know if the situation is similar for USB2 or not, although I suspect that it is. Theron Hicks wrote: > Hello, > I am developing an instrument that is currently communicating over a > special high speed parallel board. The data rate is 6.4 million 8 bit words > per second. The board works great but it costs in excess of $1600 US per > copy. It also occupies a full sized PCI slot. We are considering > implementing an alternative I/O arrangement such as USB2 or ethernet > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > absolutely necessary, Virtex2). > > Thanks, > Theron -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Reply-To: "Martin Euredjian" <0_0_0_0_@pacbell.net> From: "Martin Euredjian" <0_0_0_0_@pacbell.net> Newsgroups: comp.arch.fpga,comp.lang.vhdl References: <9a2c3a75.0210071528.17ed50f2@posting.google.com> Subject: Re: USB2 in FPGA? Lines: 29 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: <3Tto9.1428$0p2.177367369@newssvr13.news.prodigy.com> NNTP-Posting-Host: 64.170.224.250 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr13.news.prodigy.com 1034054207 ST000 64.170.224.250 (Tue, 08 Oct 2002 01:16:47 EDT) NNTP-Posting-Date: Tue, 08 Oct 2002 01:16:47 EDT Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: [[PAPDONPZVABQ\YCJKDM^P@VZ\LPCXLLBWLOOAFEQR@ETUCCNSKQFCY@TXDX_WHSVB]ZEJLSNY\^J[CUVSA_QLFC^RQHUPH[P[NRWCCMLSNPOD_ESALHUK@TDFUZHBLJ\XGKL^NXA\EVHSP[D_C^B_^JCX^W]CHBAX]POG@SSAZQ\LE[DCNMUPG_VSC@VJM Date: Tue, 08 Oct 2002 05:16:47 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr13.news.prodigy.com.POSTED!003b42bf!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21733 "Andy Peters" wrote in message news:9a2c3a75.0210071528.17ed50f2@posting.google.com... > > Anyhow, just a thought. Check out the Silicon Image site for more details: > > http://www.siimage.com/home.asp > > Good luck getting tech support from them. Unless, of course, your > e-mail address ends in dell.com, or something. > > If you call their main phone number, you get dumped into a black hole. ... That certainly doesn't match my experience with them. -- Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" ###### From: "Theron Hicks" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? Date: Tue, 8 Oct 2002 12:36:34 -0400 Organization: Michigan State University Lines: 67 Message-ID: References: NNTP-Posting-Host: dfti.egr.msu.edu X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!newsfeed.r-kom.de!news0.de.colt.net!news-fra1.dfn.de!news-mue1.dfn.de!newsfeed.vmunix.org!iad-peer.news.verio.net!news.verio.net!solaris.cc.vt.edu!news.vt.edu!msunews!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21743 "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:y4%m9.1568$pk1.28677390@newssvr21.news.prodigy.com... > This is a bit far fetched, but might work very nicely for your application. > Have you thought of using DVI I/O chips? DVI is a relatively recent > connectivity methodology for computer displays. It is, in escence, > serialized 8 bit RGB. A single link can deliver in the order of 5 or 6 > Gigabits per second, if I recall. The chips (both TX and RX) are less than > ten bucks a piece. You can certainly clock DVI at less then the max single > link 165 MHz rate and transport your data to via a serial link. I think the > chips will go down to 25 MHz clocking. At low data rates you can probably > go many more feet than the standard provides for. Heck, you could have > three redundant links delivered over a commodity cable. > > Anyhow, just a thought. Check out the Silicon Image site for more details: > http://www.siimage.com/home.asp > > > HTH, > > > -- > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > > "Theron Hicks" wrote in message > news:anctr2$2brl$1@msunews.cl.msu.edu... > > Hello, > > I am developing an instrument that is currently communicating over a > > special high speed parallel board. The data rate is 6.4 million 8 bit > words > > per second. The board works great but it costs in excess of $1600 US per > > copy. It also occupies a full sized PCI slot. We are considering > > implementing an alternative I/O arrangement such as USB2 or ethernet > > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > > absolutely necessary, Virtex2). > > > > Thanks, > > Theron > > > > > > Ideally, I need something with a standard port in a typical PC. Otherwise, I can't get rid of the $1600 data card. I realize that USB2 is still new and not every PC has one but at least you can go to most any computer store and get one. Does the same apply to DVI? What is the typical cost? Thanks for the advice, Theron Hicks ###### From: "Theron Hicks" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? Date: Tue, 8 Oct 2002 12:44:50 -0400 Organization: Michigan State University Lines: 67 Message-ID: References: <3DA21E5F.8DD5ED3@andraka.com> NNTP-Posting-Host: dfti.egr.msu.edu X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!psinet-eu-nl!news-x2.support.nl!colt.net!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!uwm.edu!msunews!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21747 "Ray Andraka" wrote in message news:3DA21E5F.8DD5ED3@andraka.com... > A while back we considered USB in the FPGA, but when push came to shove, it was > cheaper to use an external USB chip. In our case, it was the original USB, and > we used a National Semi chip, I think it was a USBN9603 which has both the > controller and the PHY in one package for about $2.25. When we sized the USB > for putting in the FPGA we still needed an external PHY, and it would have > pushed us into a larger part costing far more than the off the shelf chip. I > don't know if the situation is similar for USB2 or not, although I suspect that > it is. > Ray, I am beginning to think along the same lines. The chips are about the same price ($2 to $3 or so) and the USB2 chip is proven. Why re-invent the wheel, especially when the quantities are so low. Just for grins I priced a USB2 core from MEMIC and the cost for net list only, was $30000. Then it takes about 1500 slices to implement it. That would more than quadruple the gate count on that particular card and we aren't using all that in the first place. Has anyone tried out any of the new USB2 chips? Any comments on support and availability for the small guy? (10 to 12 systems a year or less initially...) Even experience with USB1 would be of interest as I am uncertain as to exactly what I might be getting into in terms of degree of complexity. Thanks, Theron > Theron Hicks wrote: > > > Hello, > > I am developing an instrument that is currently communicating over a > > special high speed parallel board. The data rate is 6.4 million 8 bit words > > per second. The board works great but it costs in excess of $1600 US per > > copy. It also occupies a full sized PCI slot. We are considering > > implementing an alternative I/O arrangement such as USB2 or ethernet > > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > > absolutely necessary, Virtex2). > > > > Thanks, > > Theron > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > ###### Reply-To: "Martin Euredjian" <0_0_0_0_@pacbell.net> From: "Martin Euredjian" <0_0_0_0_@pacbell.net> Newsgroups: comp.arch.fpga,comp.lang.vhdl References: Subject: Re: USB2 in FPGA? Lines: 28 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: <5REo9.1517$Lq6.192865590@newssvr13.news.prodigy.com> NNTP-Posting-Host: 64.170.224.250 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr13.news.prodigy.com 1034099137 ST000 64.170.224.250 (Tue, 08 Oct 2002 13:45:37 EDT) NNTP-Posting-Date: Tue, 08 Oct 2002 13:45:37 EDT Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: [[OYR_CD[JWIRVH]^JKBOW@@YJ_ZTB\MV@BD]\YIJYWZUYICD^RAQBKZQTZTX\_I[^G_KGFNON[ZOE_AZNVO^\XGGNTCIRPIJH[@RQKBXLRZ@CD^HKANYVW@RLGEZEJN@\_WZJBNZYYKVIOR]T]MNMG_Z[YVWSCH_Q[GPC_A@CARQVXDSDA^M]@DRVUM@RBM Date: Tue, 08 Oct 2002 17:46:40 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!207.115.63.138!newscon04.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr13.news.prodigy.com.POSTED!003b42bf!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21732 > > "Theron Hicks" > Ideally, I need something with a standard port in a typical PC. Otherwise, > I can't get rid of the $1600 data card. I realize that USB2 is still new > and not every PC has one but at least you can go to most any computer store > and get one. Does the same apply to DVI? What is the typical cost? The DVI approach wouldn't work then. You'd need a custom card on the PC. I misunderstood and thought that you could consider this sort of an approach. Your 6.4 million bytes per second rate pretty much limits your options if you are looking for standard interfaces. USB2 might just be the most sensible way to go. I'd opt for an external USB2 device as oppose to an FPGA implementation. Is your 6.4 MB/s rate a continuous rate or a maximum burst rate? -- Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" ###### Message-ID: <3DA39122.2050104@netscape.net> From: bulletdog7 Reply-To: bulletdog7@nomore.spam.please.netscape.net User-Agent: Mozilla/5.0 (Windows; U; Win98; en-US; rv:0.9.4.1) Gecko/20020508 Netscape6/6.2.3 X-Accept-Language: en-us MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? References: <3DA21E5F.8DD5ED3@andraka.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Lines: 100 Date: Wed, 09 Oct 2002 02:15:26 GMT NNTP-Posting-Host: 68.99.227.87 X-Complaints-To: abuse@cox.net X-Trace: news1.west.cox.net 1034129726 68.99.227.87 (Tue, 08 Oct 2002 22:15:26 EDT) NNTP-Posting-Date: Tue, 08 Oct 2002 22:15:26 EDT Organization: Cox Communications Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!p01!news1.west.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21777 Theron, If you go the external route, you might look at Philips Semiconductors. I think they've got one with a PCI interface but I have no idea on price or availability. Just giving yet another vendor choice. Jerry Theron Hicks wrote: > "Ray Andraka" wrote in message > news:3DA21E5F.8DD5ED3@andraka.com... > >>A while back we considered USB in the FPGA, but when push came to shove, >> > it was > >>cheaper to use an external USB chip. In our case, it was the original >> > USB, and > >>we used a National Semi chip, I think it was a USBN9603 which has both the >>controller and the PHY in one package for about $2.25. When we sized the >> > USB > >>for putting in the FPGA we still needed an external PHY, and it would have >>pushed us into a larger part costing far more than the off the shelf chip. >> > I > >>don't know if the situation is similar for USB2 or not, although I suspect >> > that > >>it is. >> >> > Ray, > I am beginning to think along the same lines. The chips are about the > same price ($2 to $3 or so) and the USB2 chip is proven. Why re-invent the > wheel, especially when the quantities are so low. Just for grins I priced a > USB2 core from MEMIC and the cost for net list only, was $30000. Then it > takes about 1500 slices to implement it. That would more than quadruple the > gate count on that particular card and we aren't using all that in the first > place. > > Has anyone tried out any of the new USB2 chips? Any comments on support and > availability for the small guy? (10 to 12 systems a year or less > initially...) Even experience with USB1 would be of interest as I am > uncertain as to exactly what I might be getting into in terms of degree of > complexity. > > Thanks, > Theron > > >>Theron Hicks wrote: >> >> >>>Hello, >>> I am developing an instrument that is currently communicating over a >>>special high speed parallel board. The data rate is 6.4 million 8 bit >>> > words > >>>per second. The board works great but it costs in excess of $1600 US >>> > per > >>>copy. It also occupies a full sized PCI slot. We are considering >>>implementing an alternative I/O arrangement such as USB2 or ethernet >>>(TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some >>>other FPGA friendly technology? Note: target FPGA is a Spartan2E (or >>> > if > >>>absolutely necessary, Virtex2). >>> >>>Thanks, >>>Theron >>> >>-- >>--Ray Andraka, P.E. >>President, the Andraka Consulting Group, Inc. >>401/884-7930 Fax 401/884-7950 >>email ray@andraka.com >>http://www.andraka.com >> >> "They that give up essential liberty to obtain a little >> temporary safety deserve neither liberty nor safety." >> -Benjamin Franklin, 1759 >> >> >> > > ###### Message-ID: <3DA47FD2.19589F37@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? References: <3DA21E5F.8DD5ED3@andraka.com> <3DA39122.2050104@netscape.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 117 Date: Wed, 09 Oct 2002 19:13:58 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1034190838 68.15.41.165 (Wed, 09 Oct 2002 15:13:58 EDT) NNTP-Posting-Date: Wed, 09 Oct 2002 15:13:58 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!solnet.ch!solnet.ch!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21813 We stayed away from the phillips device because it has a PCI interface. PCI is fine if you are hanging it on a PCI bus, lousy if you need to make a PCI controller in the FPGA to talk to it. The NS part has a more conventional microcontroller style interface. bulletdog7 wrote: > Theron, > > If you go the external route, you might look at Philips Semiconductors. > I think they've got one with a PCI interface but I have no idea on price > or availability. Just giving yet another vendor choice. > > Jerry > > Theron Hicks wrote: > > > "Ray Andraka" wrote in message > > news:3DA21E5F.8DD5ED3@andraka.com... > > > >>A while back we considered USB in the FPGA, but when push came to shove, > >> > > it was > > > >>cheaper to use an external USB chip. In our case, it was the original > >> > > USB, and > > > >>we used a National Semi chip, I think it was a USBN9603 which has both the > >>controller and the PHY in one package for about $2.25. When we sized the > >> > > USB > > > >>for putting in the FPGA we still needed an external PHY, and it would have > >>pushed us into a larger part costing far more than the off the shelf chip. > >> > > I > > > >>don't know if the situation is similar for USB2 or not, although I suspect > >> > > that > > > >>it is. > >> > >> > > Ray, > > I am beginning to think along the same lines. The chips are about the > > same price ($2 to $3 or so) and the USB2 chip is proven. Why re-invent the > > wheel, especially when the quantities are so low. Just for grins I priced a > > USB2 core from MEMIC and the cost for net list only, was $30000. Then it > > takes about 1500 slices to implement it. That would more than quadruple the > > gate count on that particular card and we aren't using all that in the first > > place. > > > > Has anyone tried out any of the new USB2 chips? Any comments on support and > > availability for the small guy? (10 to 12 systems a year or less > > initially...) Even experience with USB1 would be of interest as I am > > uncertain as to exactly what I might be getting into in terms of degree of > > complexity. > > > > Thanks, > > Theron > > > > > >>Theron Hicks wrote: > >> > >> > >>>Hello, > >>> I am developing an instrument that is currently communicating over a > >>>special high speed parallel board. The data rate is 6.4 million 8 bit > >>> > > words > > > >>>per second. The board works great but it costs in excess of $1600 US > >>> > > per > > > >>>copy. It also occupies a full sized PCI slot. We are considering > >>>implementing an alternative I/O arrangement such as USB2 or ethernet > >>>(TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > >>>other FPGA friendly technology? Note: target FPGA is a Spartan2E (or > >>> > > if > > > >>>absolutely necessary, Virtex2). > >>> > >>>Thanks, > >>>Theron > >>> > >>-- > >>--Ray Andraka, P.E. > >>President, the Andraka Consulting Group, Inc. > >>401/884-7930 Fax 401/884-7950 > >>email ray@andraka.com > >>http://www.andraka.com > >> > >> "They that give up essential liberty to obtain a little > >> temporary safety deserve neither liberty nor safety." > >> -Benjamin Franklin, 1759 > >> > >> > >> > > > > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3DA48337.2DB92204@ecubics.com> Date: Wed, 09 Oct 2002 13:27:51 -0600 From: emanuel stiebler X-Mailer: Mozilla 4.79 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: USB2 in FPGA? References: <3DA21E5F.8DD5ED3@andraka.com> <3DA39122.2050104@netscape.net> <3DA47FD2.19589F37@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 10 NNTP-Posting-Host: 63.90.186.226 X-Trace: 1034191618 reader0.ash.ops.us.uu.net 10821 63.90.186.226 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.abs.net!uunet!dca.uu.net!ash.uu.net!spool0900.news.uu.net!reader0900.news.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21812 Ray Andraka wrote: > > We stayed away from the phillips device because it has a PCI interface. PCI is > fine if you are hanging it on a PCI bus, lousy if you need to make a PCI > controller in the FPGA to talk to it. The NS part has a more conventional > microcontroller style interface. So, anybody knows of a USB2 host controller without PCI ? cheers & thanks