From: "Ho Wong" Newsgroups: comp.arch.fpga Subject: Rounting of non-global IO pad to a GCLKIOB site. Date: Tue, 1 Oct 2002 16:41:51 +1000 Organization: University of Queensland Lines: 10 Message-ID: NNTP-Posting-Host: a311-8371.students.itee.uq.edu.au X-Trace: bunyip.cc.uq.edu.au 1033454511 6001 130.102.74.212 (1 Oct 2002 06:41:51 GMT) X-Complaints-To: news@uq.edu.au NNTP-Posting-Date: 1 Oct 2002 06:41:51 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!news1.optus.net.au!optus!bunyip.cc.uq.edu.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21482 Hello. I'm using a pin to drive a process but the thing is that it's already been soldered onto a normal IO pin. I've been trawling through past posts and newsgroups and I still haven't found a answer yet. I'm just a beginner to fpgas so i'm not very familiar with the low level logics. I tried doing PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN has illegal connection Would it be possible to short my normal IO to one of the dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE Webpack. ###### From: Dali Newsgroups: comp.arch.fpga Subject: Re: Rounting of non-global IO pad to a GCLKIOB site. Date: Mon, 30 Sep 2002 23:57:19 +0000 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3D98E4DF.3010100@ifrance.com> User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.0.0) Gecko/20020529 X-Accept-Language: en-us, en MIME-Version: 1.0 References: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@supernews.com Lines: 21 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.tele.dk!small.news.tele.dk!208.49.253.98!newsfeed.news2me.com!newsfeed-west.nntpserver.com!hub1.meganetnews.com!nntpserver.com!telocity-west!TELOCITY!sn-xit-03!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21469 It doesn't work that way. In order to take advantage of the clock tree brovided by the BUFG primitive you need to use an IBUFG instead of an IBUF. So a normal IO pins does not do the job. For further details, look at the Xilinx Handbook. Dali Ho Wong wrote: > Hello. I'm using a pin to drive a process but the thing is that it's already > been soldered onto a normal IO pin. I've been trawling through past posts > and newsgroups and I still haven't found a answer yet. I'm just a beginner > to fpgas so i'm not very familiar with the low level logics. I tried doing > PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN has > illegal connection Would it be possible to short my normal IO to one of the > dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE > Webpack. > > ###### From: Dali Newsgroups: comp.arch.fpga Subject: Re: Rounting of non-global IO pad to a GCLKIOB site. Date: Tue, 01 Oct 2002 01:50:25 +0000 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3D98FF61.402@ifrance.com> User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.0.0) Gecko/20020529 X-Accept-Language: en-us, en MIME-Version: 1.0 References: <3D98E4DF.3010100@ifrance.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@supernews.com Lines: 63 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!telocity-west!TELOCITY!sn-xit-03!sn-xit-01!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21502 How fast is your clock? If you can ignore signal integrity issues, I would say, put a wire from the actual pin and the pin the package that is connected to an IBUFG. The problem about general purpose IOs and routing is that the P&R tool does not guarantee any skew limits on the clock if you're not using a Global Buffer. I have seen 5 to 6ns skew on a VirtexE part when I used general purpose routing for a clock. Dali Ho Wong wrote: > So is there a way at all to clock this process without having to use the > bufg? And is it possible to short the two pins together? (current non-global > to a global one) > "Dali" wrote in message > news:3D98E4DF.3010100@ifrance.com... > >>It doesn't work that way. In order to take advantage of the clock tree >>brovided by the BUFG primitive you need to use an IBUFG instead of an >>IBUF. So a normal IO pins does not do the job. >> >>For further details, look at the Xilinx Handbook. >> >>Dali >> >>Ho Wong wrote: >> >>>Hello. I'm using a pin to drive a process but the thing is that it's >> > already > >>>been soldered onto a normal IO pin. I've been trawling through past >> > posts > >>>and newsgroups and I still haven't found a answer yet. I'm just a >> > beginner > >>>to fpgas so i'm not very familiar with the low level logics. I tried >> > doing > >>>PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN >> > has > >>>illegal connection Would it be possible to short my normal IO to one of >> > the > >>>dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE >>>Webpack. >>> >>> >> >> > > ###### From: "Ho Wong" Newsgroups: comp.arch.fpga Subject: Re: Rounting of non-global IO pad to a GCLKIOB site. Date: Tue, 1 Oct 2002 17:53:50 +1000 Organization: University of Queensland Lines: 34 Message-ID: References: <3D98E4DF.3010100@ifrance.com> NNTP-Posting-Host: a311-8371.students.itee.uq.edu.au X-Trace: bunyip.cc.uq.edu.au 1033458830 15403 130.102.74.212 (1 Oct 2002 07:53:50 GMT) X-Complaints-To: news@uq.edu.au NNTP-Posting-Date: 1 Oct 2002 07:53:50 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!feed.cgocable.net!newsfeed.mountaincable.net!news1.optus.net.au!optus!bunyip.cc.uq.edu.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21483 So is there a way at all to clock this process without having to use the bufg? And is it possible to short the two pins together? (current non-global to a global one) "Dali" wrote in message news:3D98E4DF.3010100@ifrance.com... > It doesn't work that way. In order to take advantage of the clock tree > brovided by the BUFG primitive you need to use an IBUFG instead of an > IBUF. So a normal IO pins does not do the job. > > For further details, look at the Xilinx Handbook. > > Dali > > Ho Wong wrote: > > Hello. I'm using a pin to drive a process but the thing is that it's already > > been soldered onto a normal IO pin. I've been trawling through past posts > > and newsgroups and I still haven't found a answer yet. I'm just a beginner > > to fpgas so i'm not very familiar with the low level logics. I tried doing > > PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN has > > illegal connection Would it be possible to short my normal IO to one of the > > dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE > > Webpack. > > > > > > ###### Sender: drogoff@DROGOFF-LAPTOP Newsgroups: comp.arch.fpga Subject: Re: Rounting of non-global IO pad to a GCLKIOB site. References: <3D98E4DF.3010100@ifrance.com> <3D98FF61.402@ifrance.com> From: David Rogoff Organization: The Rogoffs User-Agent: Gnus/5.0808 (Gnus v5.8.8) XEmacs/21.4 (Informed Management (Windows [1])) Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-GC-Trace: gv1-tizH72P9ti6RnTvaDT/rv0BI5drAihoYEE= NNTP-Posting-Date: Tue, 01 Oct 2002 13:04:53 CDT Lines: 70 X-Trace: sv3-dSsrghb2QLTrXSSXSgtFOjnN79Vh4EVAjYR82cH+bEL+VzLCH8lUBFo9LWSsb9yH2eEDCBHuGodq0l6!VaQ+XKSxV/udo5HPzDTc/451LmW8bWqoV8Xa3z37Mbf+iYu/Wg7bk2fO8N9K8w== X-Complaints-To: abuse@GigaNews.Com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.1 Date: Tue, 01 Oct 2002 18:04:53 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!feed.cgocable.net!newsfeed-east.nntpserver.com!nntpserver.com!border1.nntp.aus1.giganews.com!nntp.giganews.com!nntp3.aus1.giganews.com!bin5.nnrp.aus1.giganews.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21507 1) why can't you just lift the pin? Is it a BGA package? 2) I saw someone do this once on a Virtex where he had more clocks than GCLK pins. If you only need to clock a few things it may work. He manually instatiated an SRL16 in the HDL code and wired the CLK pin to a regular IO. You'll have to search the Xilinx site for more info. David Dali writes: > > Dali > > Ho Wong wrote: > > So is there a way at all to clock this process without having to use the > > bufg? And is it possible to short the two pins together? (current non-global > > to a global one) > > "Dali" wrote in message > > news:3D98E4DF.3010100@ifrance.com... > > > > >>It doesn't work that way. In order to take advantage of the clock tree > >>brovided by the BUFG primitive you need to use an IBUFG instead of an > >>IBUF. So a normal IO pins does not do the job. > >> > >>For further details, look at the Xilinx Handbook. > >> > >>Dali > >> > >>Ho Wong wrote: > >> > >>>Hello. I'm using a pin to drive a process but the thing is that it's > >> > > already > > > > >>>been soldered onto a normal IO pin. I've been trawling through past > >> > > posts > > > > >>>and newsgroups and I still haven't found a answer yet. I'm just a > >> > > beginner > > > > >>>to fpgas so i'm not very familiar with the low level logics. I tried > >> > > doing > > > > >>>PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN > >> > > has > > > > >>>illegal connection Would it be possible to short my normal IO to one of > >> > > the > > > > >>>dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE > >>>Webpack. > >>> > >>> > >> > >> > > ###### Message-ID: <3D9A4743.34A25226@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Rounting of non-global IO pad to a GCLKIOB site. References: <3D98E4DF.3010100@ifrance.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 41 Date: Wed, 02 Oct 2002 01:03:43 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1033520623 68.15.41.165 (Tue, 01 Oct 2002 21:03:43 EDT) NNTP-Posting-Date: Tue, 01 Oct 2002 21:03:43 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!cox.net!p01!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21516 Bad information. You certainly can run a clock in on a regular I/O pin. Instantiate an IBUF at the pin and feed that to a BUFG. I don't think the tools will automatically infer the BUFG in this case, but instantiation gets around it just fine. The main thing to note is that your clock will not have the controlled pin to BUFG delay it had with the IBUFG so if your clock relationship with other I/O pins is critical you need to be careful (and use a CLKDLL). Dali wrote: > It doesn't work that way. In order to take advantage of the clock tree > brovided by the BUFG primitive you need to use an IBUFG instead of an > IBUF. So a normal IO pins does not do the job. > > For further details, look at the Xilinx Handbook. > > Dali > > Ho Wong wrote: > > Hello. I'm using a pin to drive a process but the thing is that it's already > > been soldered onto a normal IO pin. I've been trawling through past posts > > and newsgroups and I still haven't found a answer yet. I'm just a beginner > > to fpgas so i'm not very familiar with the low level logics. I tried doing > > PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN has > > illegal connection Would it be possible to short my normal IO to one of the > > dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE > > Webpack. > > > > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3D9A3CD5.9020402@ifrance.com> From: Dali User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.0.0) Gecko/20020529 X-Accept-Language: en-us, en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Rounting of non-global IO pad to a GCLKIOB site. References: <3D98E4DF.3010100@ifrance.com> <3D9A4743.34A25226@andraka.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-GC-Trace: gv1-/MV0PA6llbr2Q3m0l3fmpg5ddvssoi41KkwBXVaXOyQr8lPdDCw97rtny/tRcKiQg== X-GC-Trace: gv1-jgZ50Ia6h3RnqZLaVWH9yfm9qPrVExKqmSSMx+NcWZfuaEbvlYf9cdZ+yNUjXA= NNTP-Posting-Date: Wed, 02 Oct 2002 02:36:23 CDT Organization: Giganews.Com - Premium News Outsourcing Lines: 55 X-Trace: sv3-sDbAXZmt6QJ10t7Lgloiiu8zN0ZeITT7nIgHkGkZRsvoEKKBFKM69cGy+Ulk/YEINUJ5fa3KmMg+0a+!mB8nXmCyIFIs7atY0jVeRAVEefKABmtzbqfzk3i6T3VPp02fee6uJrl+tsWBpJA= X-Complaints-To: abuse@GigaNews.Com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.1 Date: Wed, 02 Oct 2002 07:36:23 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.news2me.com!border1.nntp.aus1.giganews.com!nntp.giganews.com!nntp3.aus1.giganews.com!bin4.nnrp.aus1.giganews.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21515 Mea Culpa. Looks like I read the Xilinx Handbook too fast. Thanks Ray for the correction. Dali Ray Andraka wrote: > Bad information. You certainly can run a clock in on a regular I/O pin. > Instantiate an IBUF at the pin and feed that to a BUFG. I don't think the tools > will automatically infer the BUFG in this case, but instantiation gets around it > just fine. The main thing to note is that your clock will not have the controlled > pin to BUFG delay it had with the IBUFG so if your clock relationship with other > I/O pins is critical you need to be careful (and use a CLKDLL). > > Dali wrote: > > >>It doesn't work that way. In order to take advantage of the clock tree >>brovided by the BUFG primitive you need to use an IBUFG instead of an >>IBUF. So a normal IO pins does not do the job. >> >>For further details, look at the Xilinx Handbook. >> >>Dali >> >>Ho Wong wrote: >> >>>Hello. I'm using a pin to drive a process but the thing is that it's already >>>been soldered onto a normal IO pin. I've been trawling through past posts >>>and newsgroups and I still haven't found a answer yet. I'm just a beginner >>>to fpgas so i'm not very familiar with the low level logics. I tried doing >>>PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN has >>>illegal connection Would it be possible to short my normal IO to one of the >>>dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE >>>Webpack. >>> >>> >> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >