From: Jarmo Newsgroups: comp.arch.fpga Subject: PCB Design for Altera FPGA Date: Wed, 25 Sep 2002 11:22:06 +0300 Organization: University of Oulu Lines: 20 Message-ID: NNTP-Posting-Host: paju.oulu.fi Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Trace: ousrvr3.oulu.fi 1032942128 4701 130.231.240.20 (25 Sep 2002 08:22:08 GMT) X-Complaints-To: news@news.oulu.fi NNTP-Posting-Date: 25 Sep 2002 08:22:08 GMT X-X-Sender: jarmoma@paju.oulu.fi Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news.telebyte.nl!news1.spb.su!newsfeed1.funet.fi!newsfeeds.funet.fi!ousrvr3.oulu.fi!paju.oulu.fi!jarmoma Xref: chonsp.franklin.ch comp.arch.fpga:21289 Hey I want to make Printed Circuit Board (PCB) for Altera Flex 8000 family. Problem is that I don't find any datasheet telling me how to do the powering for the Altera. Should I add decoupling capasitors and what values they should be? Is there internal clock in Altera or should I add a crystall to my PCB? If you are wondering why I want to use OLD Altera Flex 8000, because I want to add only 2 layers to my PCB. I think that new Alteras need separate power and ground layers, so 2 layers is not enough. is there some websites/tutorials how to do PCBs for FPGAs? - Jarmo jarmoma@mail.student.oulu.fi ###### Message-ID: <3D9188F1.6040901@esr.phys.chem.ethz.ch> Date: Wed, 25 Sep 2002 11:59:13 +0200 From: Rene Tschaggelar User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-us, en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: PCB Design for Altera FPGA References: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit NNTP-Posting-Host: sanadze.ethz.ch X-Trace: pfaff.ethz.ch 1032947892 sanadze.ethz.ch (25 Sep 2002 11:58:12 +0200) Organization: Swiss Federal Institute of Technology (ETHZ) Lines: 32 Path: chonsp.franklin.ch!pfaff.ethz.ch Xref: chonsp.franklin.ch comp.arch.fpga:21278 I do Altera ACEX1k, Max7000 and Max3000 on twosided boards. No problems. I place the decoupling caps on the backside, a selection amongst 10 and 100nF 1206. The backside is split between Vcc and GND in the vicinity of the Altera. It did work up too 100MHz till now. I didn't have higher clocked designs yet. As clock I use clockgenerators, not just crystals. Rene Jarmo wrote: > Hey > > I want to make Printed Circuit Board (PCB) for Altera Flex 8000 family. > Problem is that I don't find any datasheet telling me how to do the > powering for the Altera. Should I add decoupling capasitors and what > values they should be? > > Is there internal clock in Altera or should I add a crystall to my PCB? > > If you are wondering why I want to use OLD Altera Flex 8000, because I > want to add only 2 layers to my PCB. I think that new Alteras need > separate power and ground layers, so 2 layers is not enough. > > is there some websites/tutorials how to do PCBs for FPGAs? ###### From: kayrock66@yahoo.com (Jay) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for Altera FPGA Date: 25 Sep 2002 08:16:32 -0700 Organization: http://groups.google.com/ Lines: 34 Message-ID: References: NNTP-Posting-Host: 66.81.28.166 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1032966992 25036 127.0.0.1 (25 Sep 2002 15:16:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 25 Sep 2002 15:16:32 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21298 Using power planes is just a rule of thumb; its the EASIEST way of guaranteeing a low impedance supply path. But depending on the size of your design, the number of outputs you switch at once, and other things, isn't not entirely necessary. On a 2 layer board you can do a copper pour of ground after you route it, while its not as good as full plane its better than just routes. You can route your supply pins with wide traces, and before routing anything else, bypass every supply pin as close to the pin as you can. Use an on board supply. If your design fits on an 8000 family part, then your talking about a really tiny design, so it will be a small part in any family. Regards Jarmo wrote in message news:... > Hey > > I want to make Printed Circuit Board (PCB) for Altera Flex 8000 family. > Problem is that I don't find any datasheet telling me how to do the > powering for the Altera. Should I add decoupling capasitors and what > values they should be? > > Is there internal clock in Altera or should I add a crystall to my PCB? > > If you are wondering why I want to use OLD Altera Flex 8000, because I > want to add only 2 layers to my PCB. I think that new Alteras need > separate power and ground layers, so 2 layers is not enough. > > is there some websites/tutorials how to do PCBs for FPGAs? > > - Jarmo > jarmoma@mail.student.oulu.fi ###### From: steen@tech-forge.com (Steen Larsen) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for Altera FPGA Date: 26 Sep 2002 14:03:45 -0700 Organization: http://groups.google.com/ Lines: 40 Message-ID: <3e8d96d6.0209261303.2163efb2@posting.google.com> References: NNTP-Posting-Host: 134.134.136.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1033074225 784 127.0.0.1 (26 Sep 2002 21:03:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 26 Sep 2002 21:03:45 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21387 Jarmo wrote in message news:... > Hey > > I want to make Printed Circuit Board (PCB) for Altera Flex 8000 family. > Problem is that I don't find any datasheet telling me how to do the > powering for the Altera. Should I add decoupling capasitors and what > values they should be? > Just generally speaking for board layout FPGAs will be similar to more specialized chips. You may find good general PCB guidelines in app notes from the major silicon vendors (they want you to be successfull in order to buy more of their silicon). Decoupling caps are certainly a good idea. Generally put a larger bulk cap >100uF someplace on the board to remove slow voltage variations. Put smaller .1uF caps close to the chip power/gnd signals to remove high frequency oscillations. If you are doing the board, put as many pads as you easily can, and you can populate appropriately later on based on oscilloscope readings. > Is there internal clock in Altera or should I add a crystall to my PCB? > Unless you have an external clock source or doing a design that is totally asynchronous, you will need either a crystal or clock driver. > If you are wondering why I want to use OLD Altera Flex 8000, because I > want to add only 2 layers to my PCB. I think that new Alteras need > separate power and ground layers, so 2 layers is not enough. > I am finishing a PCI 33MHz board (www.tech-forge.com) with two layers and have not seen much of a power decoupling problem. (Plenty of design problems though!) > is there some websites/tutorials how to do PCBs for FPGAs? > I would look at how other boards with FPGAs are done, such as www.optimagic.com Good luck, -Steen ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: PCB Design for Altera FPGA Date: Thu, 26 Sep 2002 18:32:03 -0400 Organization: Arius, Inc Lines: 98 Message-ID: <3D938AE3.7911562F@yahoo.com> References: <3e8d96d6.0209261303.2163efb2@posting.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVacfCvowyizalmrDUe7RSEWY2FpQe45UBvu8pPouvMI3Yf8Wyo7qOMz X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 26 Sep 2002 22:32:06 GMT X-Mailer: Mozilla 4.79 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!zen.net.uk!news.cabal.org.uk!news-peer.gradwell.net!newsfeed.media.kyoto-u.ac.jp!newsfeed.mesh.ad.jp!jpix!newsfeed.gol.com!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21400 Allow me to add my two cents worth. I have been designing PCBs with all sorts of chips for a long time and I have not found any compelling reasons to change the way I do decoupling on any but the most speciallized designs. For an Altera 8000 series part I would recommend that you use one 0.1 uF ceramic cap in the 0603 package for each power pin on the chip. The cap should be situated so that the loop from the power pin through the trace, cap, trace and to the ground pin (and of course the path inside the chip which you can't see but can approximate with a straight line) has the minimum area. For SOIC and QFPs this means finding power and ground pins close to one another for each cap. On fancier packages like BGAs and chip scale packaging it is often required that you put the chip on one side of the board and the caps on the other. You will have some added inductance from the vias, but this will be small compared to the long path to get outside the chip footprint working on the same side of the board. Some designers like to use a combination of 0.1, 0.01 and even 0.001 ceramic caps since they have different resonant frequencies and conceptually can provide a very low ESR over a wider freq range. But they can also interact in unpredictable ways and produce anti-resonances where you might not expect. So I avoid this practice. Then add a single tantalum or electrolytic bulk cap for the entire board. I can't say how large as that will depend on the rest of your circuit. But a 100 uF will normally do. Some designers like to scatter around bulk caps, but that is pointless since they have high inductance and ESR at the higher frequencies. At the lower frequencies (<1 MHz) they have lower ESR and the circuit board path is of no (or very little) consequence. So one larger one is as good a several smaller ones unless you are trying to lower the internal ESR of the cap by using parallel bulk caps. Normally is is cheaper to use a single low ESR part than several higher ESR caps and you can save board space. So unless you are running GHz designs or are switching high voltage or high current (and I am not talking about the 50 to 100 mA from switching bus signals) you will be well served by the outline above. Just keep the loops small for your 0.1 uF ceramics and you will have working boards. Steen Larsen wrote: > > Jarmo wrote in message news:... > > Hey > > > > I want to make Printed Circuit Board (PCB) for Altera Flex 8000 family. > > Problem is that I don't find any datasheet telling me how to do the > > powering for the Altera. Should I add decoupling capasitors and what > > values they should be? > > > Just generally speaking for board layout FPGAs will be similar to more > specialized chips. You may find good general PCB guidelines in app > notes from the major silicon vendors (they want you to be successfull > in order to buy more of their silicon). Decoupling caps are certainly > a good idea. Generally put a larger bulk cap >100uF someplace on the > board to remove slow voltage variations. Put smaller .1uF caps close > to the chip power/gnd signals to remove high frequency oscillations. > If you are doing the board, put as many pads as you easily can, and > you can populate appropriately later on based on oscilloscope > readings. > > > Is there internal clock in Altera or should I add a crystall to my PCB? > > > Unless you have an external clock source or doing a design that is > totally asynchronous, you will need either a crystal or clock driver. > > > If you are wondering why I want to use OLD Altera Flex 8000, because I > > want to add only 2 layers to my PCB. I think that new Alteras need > > separate power and ground layers, so 2 layers is not enough. > > > > I am finishing a PCI 33MHz board (www.tech-forge.com) with two layers > and have not seen much of a power decoupling problem. (Plenty of > design problems though!) > > > is there some websites/tutorials how to do PCBs for FPGAs? > > > I would look at how other boards with FPGAs are done, such as > www.optimagic.com > > Good luck, > -Steen -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: Jarmo Newsgroups: comp.arch.fpga Subject: Re: PCB Design for Altera FPGA Date: Fri, 4 Oct 2002 14:23:21 +0300 Organization: University of Oulu Lines: 16 Message-ID: References: NNTP-Posting-Host: paju.oulu.fi Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Trace: ousrvr3.oulu.fi 1033730602 9149 130.231.240.20 (4 Oct 2002 11:23:22 GMT) X-Complaints-To: news@news.oulu.fi NNTP-Posting-Date: 4 Oct 2002 11:23:22 GMT To: Jay X-X-Sender: jarmoma@paju.oulu.fi In-Reply-To: Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news.tele.dk!small.news.tele.dk!195.54.122.107!newsfeed1.bredband.com!bredband!newsfeed1.telenordia.se!algonet!newsfeed1.funet.fi!newsfeeds.funet.fi!ousrvr3.oulu.fi!paju.oulu.fi!jarmoma Xref: chonsp.franklin.ch comp.arch.fpga:21637 On 25 Sep 2002, Jay wrote: > If your design fits on an 8000 family part, then your talking about a > really tiny design, so it will be a small part in any family. What chip do you suggest to me?? I don't know how big my design is going to be, so bigger fpga would be better, of course. Only thing is, the chip have to work on 2 layers PCB. If you somebody know good web-sites where is design examples about PCB's done for any FPGAs, please send me links!! - Jarmo jarmoma@mail.student.oulu.fi ###### From: "Noddy" Newsgroups: comp.arch.fpga Subject: Re: PCB Design for Altera FPGA Date: Fri, 4 Oct 2002 15:04:16 +0200 Organization: Rhodes University, Grahamstown, South Africa Lines: 24 Message-ID: <1033736444.231961@turtle.ru.ac.za> References: NNTP-Posting-Host: turtle.ru.ac.za X-Trace: hippo.ru.ac.za 1033736444 85567 146.231.128.8 (4 Oct 2002 13:00:44 GMT) X-Complaints-To: usenet@hippo.ru.ac.za NNTP-Posting-Date: Fri, 4 Oct 2002 13:00:44 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Cache-Post-Path: turtle.ru.ac.za!phat@big-ears.phys.ru.ac.za X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!logbridge.uoregon.edu!newspeer1.nac.net!infeed.is.co.za!feeder.is.co.za!146.231.128.1.MISMATCH!hippo.ru.ac.za!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21675 Have a look at techXclusives on the xilinx website. If I remember correctly, there is a useful artical on PCB design issues for FPGAs Adrian > On 25 Sep 2002, Jay wrote: > > > If your design fits on an 8000 family part, then your talking about a > > really tiny design, so it will be a small part in any family. > > What chip do you suggest to me?? I don't know how big my design is going > to be, so bigger fpga would be better, of course. Only thing is, the > chip have to work on 2 layers PCB. > > If you somebody know good web-sites where is design examples about PCB's > done for any FPGAs, please send me links!! > > - Jarmo > jarmoma@mail.student.oulu.fi > > ###### From: steen@tech-forge.com (Steen Larsen) Newsgroups: comp.arch.fpga Subject: Re: PCB Design for Altera FPGA Date: 18 Oct 2002 17:53:38 -0700 Organization: http://groups.google.com/ Lines: 98 Message-ID: <3e8d96d6.0210181653.4856249e@posting.google.com> References: <3e8d96d6.0209261303.2163efb2@posting.google.com> NNTP-Posting-Host: 134.134.136.3 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1034988818 13961 127.0.0.1 (19 Oct 2002 00:53:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 19 Oct 2002 00:53:38 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!enews.sgi.com!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:22216 Kevin, thanks for your comments. I would be interested in your reaction to my responses below. > > While I have never designed a printed circuit board, PCI specification > seems to imply that you need to use at least a 4 layer PCB. Agreed, there were a lot of variables and I wanted to keep costs down. I was prepared to scale the PC system speed down to a frequency that could be used to debug and figure all the other requirements before spinning another board. Currently I am running at 25MHz. > Also, looking at the picture of the PCI card you designed, your PCI > card doesn't seem to have any high-speed ceramic capacitors near the > edge connector in which the specification says you need to have. High-speed .1uF caps are on the bottom of the card, under the FPGA. (My hand soldering skills are not that great, so I do not advertise that more than I have to) As you say, PCI spec requires a certain number of caps near the edge connector. (I once looked for cards that followed that spec and quickly found 3 that did not have small caps near the card edge, so it seems a lightly followed spec) > Another thing I will say from my experience of developing a > PCI IP core is that perhaps the use of an Altera device is not > terribly a good idea for PCI. I seem to hear that a lot, :-) I started this well before Insight released their Xilinx PCI product. One thought was that there may be demand albeit small for a non-Xilinx card. > Looking at your PCI card, you are using a FLEX10K30E-3 which is the > slowest FLEX10KE available. > Not only that particular part of FLEX10KE is not guaranteed to meet > PCI's V/I curve (You need a speed grade -1 FLEX10KE part to meet 5V > PCI's V/I curve according to FLEX10KE datasheet.), but also I will bet > you that with FLEX10K30E-3, your PCI interface probably won't meet the > setup time requirement of Tsu < 7ns that easily unless you heavily > floorplan it because FLEX10K30E-3's 4-input LUT's delay (tLUT) is > already at 1.1ns, and some unregistered signals usually have to pass > through 3 to 4 levels of 4-input LUT before reaching a FF. (Also, you > have to add the interconnect delay between LUTs which is very > unpredictable in Altera FLEX because the fitter is so flaky, input pin > delay, and FF setup time.) Agreed, I am certainly not rigorously following PCI spec. Although I am certainly hoping to evolve into some sort of small business, if there is no market for this, it will be an interesting hobby. > The problem I had with Altera floorplanner is that even if I place a > certain LUT to a certain LAB, often the fitter will duplicate the LUT > for some reason, and when the LUT is duplicated, the placement > information gets ignored. (i.e., ix7342 gets duplicated as ix7342~1 by > the fitter. The fitter will ignore ix7342's placement information when > placing ix7342~1.) > That problem pretty much makes the Altera floorplanner useless. > Besides the Altera floorplanner problem, Altera's fitter does a pretty > poor job of meeting setup time timings, and usually meeting the setup > time is the hardest part of developing a PCI IP core. (To Altera's > credit, Altera fitter does a good job of maximizing fmax, but since > meeting fmax of 33.3MHz isn't too hard with most recent FPGAs, that's > not a big deal.) I'm currently taking defaults in Quartus II V2.1 allowing for the config cycle access and would like to get memory accesses working before opening the fitter can of worms. (Maybe by then Altera will have better parts as you point out) > Personally, I have used Xilinx Spartan-II to test my PCI IP > core, and unlike when I ported my PCI IP core to Altera > FLEX10K100EFC484-1 (tLUT = 0.7ns), Xilinx's software (ISE WebPACK) met > Tsu < 7ns without having to use the floorplanner. > Meeting Tval < 11ns and Thold <= 0ns requirement of PCI was also much > easier with Spartan-II than FLEX10KE because unlike FLEX10KE IOE which > has only one FF, Spartan-II IOB has three FFs for input, output, and > tri-state control. > If you still want to stick with Altera which I don't recommend, you > may want to consider using ACEX 1K instead which is much cheaper than > FLEX10KE, but essentially has the same features FLEX10KE has. I started this just when ACEX was coming on market (I think they were expensive), so will probably spin the board for that (or maybe Cyclone) (If I go to Xilinx, I think I would be competing too much with Insight...?) > I hate to be a nay-sayer, but since Insight Electronics sells > a well constructed Spartan-II XC2S200-based PCI prototype card with > 8MB of SDRAM for $250, I am not sure how many people will buying your > 2 layer PCB-based PCI card with FLEX10K30E-3 without external SDRAM > even if you give out the a PCI IP core for free. With Insight Electronics, don't you have to buy or license the PCI core? Some people may not want to do this and just have a manner to get high bandwith IO to/from the CPU with GPIOs that can be easily configured. (at least that is an idea...) > My suggestion will be that you may want to use 4 layer PCB, use a > larger ACEX1K (Consider using ACEX1K EP1K100-1 if you want to stick > with Altera.), have an SDRAM SO-DIMM slot, and have an expansion > connector just like what Insight Electronics Spartan-II PCI card has. Good points, but before I invest a lot of time and money, I am really curious if there is a viable marketplace out there for this sort of thing. Thanks again Kevin, -Steen