From: jjjkkl@hotmail.com (John) Newsgroups: comp.arch.fpga Subject: external switch to CPLD input Date: 21 Sep 2002 16:42:11 -0700 Organization: http://groups.google.com/ Lines: 6 Message-ID: <4a50e479.0209211542.118aab7a@posting.google.com> NNTP-Posting-Host: 24.69.255.237 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1032651732 14676 127.0.0.1 (21 Sep 2002 23:42:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 21 Sep 2002 23:42:12 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!eusc.inter.net!newsfeed.freenet.de!newsfeed.news2me.com!canoe.uoregon.edu!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21174 I would like to use a push-button switch (either normally open or normally closed) to drive a logic one (3V) or logic zero to a Xilinx CoolRunner XPLA3 CPLD. The input current should be no more than a few uA. Can anyone suggest a circuit for this using my switch, 3V supply, and hopefully just a small amount of resistors (and caps, if necessary)? ###### Message-ID: <3D8D2E62.4B25@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: external switch to CPLD input References: <4a50e479.0209211542.118aab7a@posting.google.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 31 Date: Sun, 22 Sep 2002 14:43:46 +1200 NNTP-Posting-Host: 203.79.98.241 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1032662763 203.79.98.241 (Sun, 22 Sep 2002 14:46:03 NZST) NNTP-Posting-Date: Sun, 22 Sep 2002 14:46:03 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!telocity-west!TELOCITY!news-out.spamkiller.net!propagator2-maxim!news-in.spamkiller.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21166 John wrote: > > I would like to use a push-button switch (either normally open or > normally closed) to drive a logic one (3V) or logic zero to a Xilinx > CoolRunner XPLA3 CPLD. The input current should be no more than a few > uA. Can anyone suggest a circuit for this using my switch, 3V supply, > and hopefully just a small amount of resistors (and caps, if > necessary)? See also other postings on this The smallest/simplest switch connection is using a SPCO Vcc -----\ o--------- PIN GND ----- This works best with a pin-keeper, and draws no current in either state. It also has bounce-removal. Some CPLDs have symmetric pinkeepers built in, on the others, you can drive the OP-IP to create a pinkeeper. For SPNO (tact ) type switches, you need a pullup (10-100K), and then Icc is drawn when pressed, and you also have bounce to handle. If you want a 'clean edges' signal, then use a TinyLogic HC1G14 and a pullup, plus series RC to filter the bounce. - jg ###### Reply-To: "Blackie Beard" From: "Blackie Beard" Newsgroups: comp.arch.fpga References: <4a50e479.0209211542.118aab7a@posting.google.com> Subject: Re: external switch to CPLD input Lines: 19 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: <_Maj9.7262$7i2.7132@nwrddc02.gnilink.net> Date: Sun, 22 Sep 2002 03:27:54 GMT NNTP-Posting-Host: 4.43.177.233 X-Complaints-To: abuse@verizon.net X-Trace: nwrddc02.gnilink.net 1032665274 4.43.177.233 (Sat, 21 Sep 2002 23:27:54 EDT) NNTP-Posting-Date: Sat, 21 Sep 2002 23:27:54 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed1.cidera.com!Cidera!cyclone2.gnilink.net!cyclone1.gnilink.net!spamfinder.gnilink.net!nwrddc02.gnilink.net.POSTED!fb931ecd!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21170 Normally open w/ 10K pullup, other side of switch to ground, is the most common, I think. Invert the input at top level. You will want to provide logic to reduce metastability and debounce using your clock signal. You can use a simple up/down counter to do both. Experiment with the count. Then you don't need any RC and schmitt trigger to do the debouncing externally. "John" wrote in message news:4a50e479.0209211542.118aab7a@posting.google.com... > I would like to use a push-button switch (either normally open or > normally closed) to drive a logic one (3V) or logic zero to a Xilinx > CoolRunner XPLA3 CPLD. The input current should be no more than a few > uA. Can anyone suggest a circuit for this using my switch, 3V supply, > and hopefully just a small amount of resistors (and caps, if > necessary)? ###### Message-ID: <3D8F6E45.15D8@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: external switch to CPLD input References: <4a50e479.0209211542.118aab7a@posting.google.com> <3D8D2E62.4B25@designtools.co.nz> <4a50e479.0209230948.3a102f3d@posting.google.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 85 Date: Tue, 24 Sep 2002 07:40:53 +1200 NNTP-Posting-Host: 203.79.98.130 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1032810192 203.79.98.130 (Tue, 24 Sep 2002 07:43:12 NZST) NNTP-Posting-Date: Tue, 24 Sep 2002 07:43:12 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!enews.sgi.com!news-hog.berkeley.edu!ucberkeley!nntp-relay.ihug.net!ihug.co.nz!news-out.newsfeeds.com!propagator2-maxim!news-in.spamkiller.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21207 John wrote: > > Jim Granville wrote in message news:<3D8D2E62.4B25@designtools.co.nz>... > > John wrote: > > > > > > I would like to use a push-button switch (either normally open or > > > normally closed) to drive a logic one (3V) or logic zero to a Xilinx > > > CoolRunner XPLA3 CPLD. The input current should be no more than a few > > > uA. Can anyone suggest a circuit for this using my switch, 3V supply, > > > and hopefully just a small amount of resistors (and caps, if > > > necessary)? > > > > See also other postings on this > > > > The smallest/simplest switch connection is using a SPCO > > > > Vcc -----\ > > o--------- PIN > > GND ----- > > > > This works best with a pin-keeper, and draws no current in either > > state. > > It also has bounce-removal. > > Some CPLDs have symmetric pinkeepers built in, on the others, > > you can drive the OP-IP to create a pinkeeper. > > Can I connect Vcc or GND directly to the input pin (with no > resistors), regardless of whether I have a pin-keeper? yes ( use Vccio ) > How do I calculate the current drawn this way.. There is nominally zero static current in either state > can I just model the CPLD side > of the input pin as some resistor value to ground? No, a pineeper is a snap-action current source > I don't think the Xilinx CoolRunner XPLA3 has a pin-keeper. When you > suggest creating one, do you mean on the CPLD using HDL or using > external components? See Peter A's post - you make a 'pinkeep' using regen pin drive ( but this does mean consuming a IO pin ) Vcc-----\ Pin IPb o-------|---+------|>----+---> GND ---- | OPb | +------<|----+ Here, the pin is an OP, set to == the IP, ie async regen path. ( some synthesis tools will love this :) The switch has to deliver enough brief current to force the Output buffer past the IP buffer threshold, thereafter it snaps, and holds that state until pulled the other way. ( If the option is there, set the OPb for the lowest drive ) > > > For SPNO (tact ) type switches, you need a pullup (10-100K), > > and then Icc is drawn when pressed, and you also have > > bounce to handle. > I'm handling debouncing in logic. > > When the switch is in its open state, the pin would be left floating. > Should I connect it directly to ground, or to ground using a pulldown? using a pull down > When the switch is closed, how would I find the current and voltage at > the pin when I'm using the 10-100K pullup (ie. again, how do I model > the CPLD side of the input)? 100K at 3V, is 3V/0.1M -> 30uA - this is drawn only during button press. > > Thanks a lot for your response.. I'm kinda new to all this as you can > probably tell, so thanks for helping me out! > > > If you want a 'clean edges' signal, then use a TinyLogic HC1G14 and > > a pullup, plus series RC to filter the bounce. > > > > - jg