From: jjjkkl@hotmail.com (John) Newsgroups: comp.arch.fpga Subject: using CPLD's inverter in oscillator circuit Date: 18 Sep 2002 09:52:22 -0700 Organization: http://groups.google.com/ Lines: 12 Message-ID: <4a50e479.0209180852.7406e147@posting.google.com> NNTP-Posting-Host: 207.232.118.241 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1032367942 30806 127.0.0.1 (18 Sep 2002 16:52:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 18 Sep 2002 16:52:22 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21061 I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making an oscillator circuit do drive the clock. The circuit is a basic one I've found for a 32.768kHz signal and consists of the crystal, two resistors, two capacitors, and an inverter. I am aiming for a low-power, low-cost design, and it seems that external inverters cost around 50 cents. Would it be okay to use one of the CPLD's inverters? I know that for my oscillator circuit the inverter must be unbuffered (ie one inverter in the package instead of the standard three) to avoid distortion. Would I have too much distortion using the CPLD? If so, is anyone aware of any alternate solutions (aside from a pre-built oscillator circuit.. these seem to require too much power)? Thanks a lot! ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: using CPLD's inverter in oscillator circuit Date: Wed, 18 Sep 2002 11:03:27 -0700 Organization: Xilinx,Inc Lines: 26 Message-ID: <3D88BFEF.601C5896@xilinx.com> References: <4a50e479.0209180852.7406e147@posting.google.com> NNTP-Posting-Host: peter.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: John Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!arclight.uoregon.edu!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21037 From personal experience years ago, let me warn you. It might work, but you will be using a multi-stage amplifier biased in the linear region. Plenty of opportunity for high power consumption and strange behavior, like overtone oscillation, poor start-up when Vcc is applied fast of slowly, etc. Investigate it well, for people have been "burnt". I would go for a canned oscillator package. Look at Maxim's ( formerly Dallas) ultra-accurate oscillator. Peter Alfke ============================== John wrote: > I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making > an oscillator circuit do drive the clock. The circuit is a basic one > I've found for a 32.768kHz signal and consists of the crystal, two > resistors, two capacitors, and an inverter. > I am aiming for a low-power, low-cost design, and it seems that > external inverters cost around 50 cents. Would it be okay to use one > of the CPLD's inverters? I know that for my oscillator circuit the > inverter must be unbuffered (ie one inverter in the package instead of > the standard three) to avoid distortion. Would I have too much > distortion using the CPLD? If so, is anyone aware of any alternate > solutions (aside from a pre-built oscillator circuit.. these seem to > require too much power)? Thanks a lot! ###### Message-ID: <3D88D4E7.10ED@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: using CPLD's inverter in oscillator circuit References: <4a50e479.0209180852.7406e147@posting.google.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 44 Date: Thu, 19 Sep 2002 07:32:55 +1200 NNTP-Posting-Host: 203.79.98.223 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1032377711 203.79.98.223 (Thu, 19 Sep 2002 07:35:11 NZST) NNTP-Posting-Date: Thu, 19 Sep 2002 07:35:11 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.news2me.com!newsfeed-west.nntpserver.com!hub1.meganetnews.com!nntpserver.com!telocity-west!TELOCITY!news-out.spamkiller.net!propagator2-maxim!news-in.spamkiller.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21045 John wrote: > > I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making > an oscillator circuit do drive the clock. The circuit is a basic one > I've found for a 32.768kHz signal and consists of the crystal, two > resistors, two capacitors, and an inverter. > I am aiming for a low-power, low-cost design, and it seems that > external inverters cost around 50 cents. In what volumes ? HEF4069 show appx 12c / 2500 ? > Would it be okay to use one > of the CPLD's inverters? I know that for my oscillator circuit the > inverter must be unbuffered (ie one inverter in the package instead of > the standard three) to avoid distortion. Would I have too much > distortion using the CPLD? If so, is anyone aware of any alternate > solutions (aside from a pre-built oscillator circuit.. these seem to > require too much power)? Thanks a lot! Using CPLD inverter : Quick answer NO. ( which will actually be much more than THREE inverters .. ) Besides the main issue of stability, there are also ones of phase margin, and linear-region current. Options: For 32KHz, you need low drive, to get the correct phase margin. Depending on your Vcc, look at the HEF4069, or AHCU04 ( same pinout, try both ? ). Use one inverter to make the OSC, and the other 5 to squareup the sine wave to edges fast enough to clock the CPLD. You need fast edges to miminise the linear region current, as well as avoid ground bounce multiple clocking effects. With a little care, you can also use HEF40106 (Schmitt) - choose a large Rfb, so it oscillates < 32KHz in RC mode, and then the XTAL will 'lock' the oscillation once it starts. 32KHz xtals have a long startup time. - jg ###### From: Tom Burgess Newsgroups: comp.arch.fpga Subject: Re: using CPLD's inverter in oscillator circuit Date: Wed, 18 Sep 2002 13:39:43 -0700 Organization: National Research Council of Canada Lines: 28 Message-ID: References: <4a50e479.0209180852.7406e147@posting.google.com> NNTP-Posting-Host: callisto.drao.nrc.ca Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: moonstone.imsb.nrc.ca 1032381630 21586 192.139.21.42 (18 Sep 2002 20:40:30 GMT) X-Complaints-To: news@moonstone.imsb.nrc.ca NNTP-Posting-Date: 18 Sep 2002 20:40:30 GMT User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.1) Gecko/20020826 X-Accept-Language: en-us, en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed1.cidera.com!Cidera!torn!moonstone.imsb.nrc.ca!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21055 The single transistor oscillator portion of this app note might be of some use to you: http://www.maxim-ic.com/appnotes.cfm/appnote_number/181 The remaining challenge is to find a cheap, low-power way to amplify and square up the slow oscillator output so it can be used as a clock. The Coolrunner 3 seems to want rise/fall times of less than 20 ns on its clocks. You MIGHT think about trying to use a CPLD inverter to do this - biasing the AC-coupled input to VCC/2 and driving the clock pin with the inverter output, but since the inverter input spends so much time in the linear region it will likely consume significant amounts of power - possibly several mA. Maybe another transistor gain stage would help? regards, Tom John wrote: > I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making > an oscillator circuit do drive the clock. The circuit is a basic one > I've found for a 32.768kHz signal and consists of the crystal, two > resistors, two capacitors, and an inverter. > I am aiming for a low-power, low-cost design, and it seems that > external inverters cost around 50 cents. Would it be okay to use one > of the CPLD's inverters? I know that for my oscillator circuit the > inverter must be unbuffered (ie one inverter in the package instead of > the standard three) to avoid distortion. Would I have too much > distortion using the CPLD? If so, is anyone aware of any alternate > solutions (aside from a pre-built oscillator circuit.. these seem to > require too much power)? Thanks a lot! ###### From: Marcin E. Hamerla Newsgroups: comp.arch.fpga Subject: Re: using CPLD's inverter in oscillator circuit Date: Thu, 19 Sep 2002 10:01:16 +0200 Organization: news.onet.pl Lines: 30 Sender: 87594553@pro.onet.pl@212.160.130.254 Message-ID: References: <4a50e479.0209180852.7406e147@posting.google.com> <3D88BFEF.601C5896@xilinx.com> NNTP-Posting-Host: 212.160.130.254 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.onet.pl 1032422489 2070 212.160.130.254 (19 Sep 2002 08:01:29 GMT) X-Complaints-To: abuse@onet.pl NNTP-Posting-Date: 19 Sep 2002 08:01:29 GMT X-Posting-Agent: Hamster/1.3.19.0 X-Newsreader: Forte Agent 1.7/32.534 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!news-mue1.dfn.de!news-fra1.dfn.de!news.man.poznan.pl!news.internetia.pl!newsfeed.gazeta.pl!news.onet.pl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:21073 Peter Alfke napisal(a): >Investigate it well, for people have been "burnt". A friend of mine used spare gate of Altera 7128 to built an oscillator. Everything worked Ok up to next purchase of crystals. Some Altera's stoped working after shipping to client. I helped him to investigate the problem and I found that there was about 10V sine signal amplitude on the inverter input. >I would go for a canned oscillator package. Look at Maxim's ( formerly >Dallas) ultra-accurate oscillator. > >> I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making >> an oscillator circuit do drive the clock. The circuit is a basic one >> I've found for a 32.768kHz signal and consists of the crystal, two >> resistors, two capacitors, and an inverter. >> I am aiming for a low-power, low-cost design, and it seems that >> external inverters cost around 50 cents. Would it be okay to use one >> of the CPLD's inverters? I know that for my oscillator circuit the >> inverter must be unbuffered (ie one inverter in the package instead of >> the standard three) to avoid distortion. Would I have too much >> distortion using the CPLD? If so, is anyone aware of any alternate >> solutions (aside from a pre-built oscillator circuit.. these seem to >> require too much power)? Thanks a lot! -- Pozdrowienia, Marcin E. Hamerla "Nienawidze turystow."