Message-ID: <3D7BED91.7FFDD8B8@qut.edu.au> Date: Mon, 09 Sep 2002 10:38:41 +1000 From: John Williams X-Mailer: Mozilla 4.78 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: minimalist FPGA system Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: hpc2.scsn.bee.qut.edu.au X-Trace: 9 Sep 2002 10:40:13 +1000, hpc2.scsn.bee.qut.edu.au Lines: 23 X-Authenticated-User: williaj2 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!bunyip.cc.uq.edu.au!news.qut.edu.au!hpc2.scsn.bee.qut.edu.au Xref: chonsp.franklin.ch comp.arch.fpga:20713 Hi folks, I am pondering the requirements for a minimalist FPGA-based device: Power supply Clock generator FPGA JTAG header for configuration via Xilinx parellel cable or similar Have I missed anything? Secondly, for the device to do its own FPGA configuration, I would expect to add flash (or serial prom) small CPLD for configuration control Any comments and useful references? Thanks, John ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system Date: Mon, 9 Sep 2002 00:52:40 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 42 Message-ID: References: <3D7BED91.7FFDD8B8@qut.edu.au> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1031532760 75307 128.32.112.203 (9 Sep 2002 00:52:40 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Mon, 9 Sep 2002 00:52:40 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:20739 In article <3D7BED91.7FFDD8B8@qut.edu.au>, John Williams wrote: >Hi folks, > >I am pondering the requirements for a minimalist FPGA-based device: > >Power supply Depending on the FPGA and the IO, you may need 2 or even 3 voltages. I remember seeing some cute little switching power supplies which did this. >Clock generator Probably want it socketed, but not necessarily. If soldered on, make it high frequency, its easier to downclock then upclock. >FPGA >JTAG header for configuration via Xilinx parellel cable or similar > >Have I missed anything? Bypass capacitors. Probably a blinkenlight and a reset button, and probably a power button too. You might also want to toss on a small LCD display, they are cheap and only need a few pins, but can convey a lot of information that way. Also, an FPGA which can't talk to anything is pretty useless. I'd say include a high density connector to a daughtercard which you can put whatever sorts of IOs you want. >Secondly, for the device to do its own FPGA configuration, I would >expect to add > >flash (or serial prom) >small CPLD for configuration control Xilinx makes an ASIC to do this (SystemACE), you can hook it up to a compact flash part. IF you use flash, use compact flash, having removability and program-anywhere is nice. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### Message-ID: <3D7C14CE.9EBACA13@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,de,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system References: <3D7BED91.7FFDD8B8@qut.edu.au> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 17 Date: Mon, 09 Sep 2002 03:26:13 GMT NNTP-Posting-Host: 209.179.199.164 X-Complaints-To: abuse@earthlink.net X-Trace: newsread2.prod.itd.earthlink.net 1031541973 209.179.199.164 (Sun, 08 Sep 2002 20:26:13 PDT) NNTP-Posting-Date: Sun, 08 Sep 2002 20:26:13 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!opentransit.net!newsfeed.news2me.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread2.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:20730 John Williams wrote: > Secondly, for the device to do its own FPGA configuration, I would > expect to add > > flash (or serial prom) > small CPLD for configuration control > > You do not need any CPLD. The FPGA is "smart enough" to pull its configuration out of a serial PROM. ( using CCLK ) Peter Alfke, Xilinx Applications ###### Reply-To: "Tony Burch" From: "Tony Burch" Newsgroups: comp.arch.fpga References: <3D7BED91.7FFDD8B8@qut.edu.au> Subject: Re: minimalist FPGA system Date: Mon, 9 Sep 2002 13:28:58 +1000 Organization: Burch Electronic Designs X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Lines: 65 Message-ID: <3d7c1560$0$28864$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 210.49.90.27 X-Trace: 1031542112 28864 210.49.90.27 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!news0.de.colt.net!news-fra1.dfn.de!news-han1.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!spool01.syd.optusnet.com.au!spool.optusnet.com.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:20755 Hi John, What you have just described is essentially the BurchED board... http://www.burched.com.au/B5Spartan2.html Our philosophy has always been to provide users with the "minimalist" flexible system, which gives access to ALL of the user I/Os, and allows it to be used as a base platform for prototyping a new system, or building into equipment (one-offs, or OEM). The B5-Spartan2e+ has * Spartan2E 300K gate XC2S300E device * JTAG and serial mode configuration download pod cable * Header programmable PLL oscillator (1 - 100MHz) * All the cables and hardware you need for a basic FPGA system Oh, yes, and you also get one test pushbutton switch (which I almost always use for the system Rst), and one test LED. The B5-Spartan2e+ board is US$179. We also supply plug-on modules, for easily expanding system resources. In eight days time, we are releasing a flash prom configuration module, which plugs onto the B5-Spartan2e+. Hope that is of interest, Best regards Tony Burch http://www.BurchED.com Low cost FPGA boards, for System-On-Chip prototyping and education "John Williams" wrote in message news:3D7BED91.7FFDD8B8@qut.edu.au... > Hi folks, > > I am pondering the requirements for a minimalist FPGA-based device: > > Power supply > Clock generator > FPGA > JTAG header for configuration via Xilinx parellel cable or similar > > Have I missed anything? > > Secondly, for the device to do its own FPGA configuration, I would > expect to add > > flash (or serial prom) > small CPLD for configuration control > > > Any comments and useful references? > > Thanks, > > John ###### From: nospam Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system Date: Mon, 09 Sep 2002 13:22:43 +0100 Organization: http://extra.newsguy.com Lines: 17 Message-ID: References: <3D7BED91.7FFDD8B8@qut.edu.au> <3D7C14CE.9EBACA13@earthlink.net> NNTP-Posting-Host: p-389.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Newsreader: Forte Agent 1.92/32.572 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!pln-w!spln!dex!extra.newsguy.com!newsp.newsguy.com!enews3 Xref: chonsp.franklin.ch comp.arch.fpga:20768 Peter Alfke wrote: >> Secondly, for the device to do its own FPGA configuration, I would >> expect to add >> flash (or serial prom) >> small CPLD for configuration control >You do not need any CPLD. The FPGA is "smart enough" to pull its >configuration out of a serial PROM. ( using CCLK ) >Peter Alfke, Xilinx Applications Given an FPGA with serial PROM connected to the configuration pins do the Xilinx tools and download cables support in circuit programming of the PROM through the FPGA JTAG port? ###### From: jerry@quickcores.com (Jerry D. Harthcock) Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system Date: 9 Sep 2002 07:26:00 -0700 Organization: http://groups.google.com/ Lines: 80 Message-ID: References: <3D7BED91.7FFDD8B8@qut.edu.au> <3d7c1560$0$28864$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 63.68.138.67 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1031581560 28705 127.0.0.1 (9 Sep 2002 14:26:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 9 Sep 2002 14:26:00 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:20759 "Tony Burch" wrote in message news:<3d7c1560$0$28864$afc38c87@news.optusnet.com.au>... > Hi John, > > What you have just described is essentially > the BurchED board... > http://www.burched.com.au/B5Spartan2.html > > Our philosophy has always been to provide > users with the "minimalist" flexible system, which > gives access to ALL of the user I/Os, and > allows it to be used as a base platform for > prototyping a new system, or building into > equipment (one-offs, or OEM). > > The B5-Spartan2e+ has > * Spartan2E 300K gate XC2S300E device > * JTAG and serial mode configuration download pod cable > * Header programmable PLL oscillator (1 - 100MHz) > * All the cables and hardware you need for a basic FPGA system > > Oh, yes, and you also get one test pushbutton > switch (which I almost always use for the > system Rst), and one test LED. > > The B5-Spartan2e+ board is US$179. > > We also supply plug-on modules, for easily > expanding system resources. In eight days time, > we are releasing a flash prom configuration module, > which plugs onto the B5-Spartan2e+. > > Hope that is of interest, > > Best regards > Tony Burch > http://www.BurchED.com > Low cost FPGA boards, for System-On-Chip > prototyping and education > > "John Williams" wrote in message > news:3D7BED91.7FFDD8B8@qut.edu.au... > > Hi folks, > > > > I am pondering the requirements for a minimalist FPGA-based device: > > > > Power supply > > Clock generator > > FPGA > > JTAG header for configuration via Xilinx parellel cable or similar > > > > Have I missed anything? > > > > Secondly, for the device to do its own FPGA configuration, I would > > expect to add > > > > flash (or serial prom) > > small CPLD for configuration control > > > > > > Any comments and useful references? > > > > Thanks, > > > > John The Musketeer (all-for-one) FPGA stamp, is actually both a minimalist and maximalist FPGA development platform, especially for FPGA-embeddable microcontrollers. For about $175 you get everything. JTAG real-time debugger, JTAG boundary scan controller, device programmer. No need for serial FLASH because the Musketeer's on board FPGA is an Actel ProASIC+, re-programmable FPGA with ASIC-like features. There is a product brief and news release you can download at: www.quickcores.com. There are also some ready-made microcontroller designs (STAPL format) that you can download. Regards Jerry ###### Message-ID: <3D7D2D90.E14FFF66@qut.edu.au> Date: Tue, 10 Sep 2002 09:24:00 +1000 From: John Williams X-Mailer: Mozilla 4.78 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system References: <3D7BED91.7FFDD8B8@qut.edu.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: hpc2.scsn.bee.qut.edu.au X-Trace: 10 Sep 2002 09:25:35 +1000, hpc2.scsn.bee.qut.edu.au Lines: 57 X-Authenticated-User: williaj2 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!news1.optus.net.au!optus!bunyip.cc.uq.edu.au!news.qut.edu.au!hpc2.scsn.bee.qut.edu.au Xref: chonsp.franklin.ch comp.arch.fpga:20790 "Nicholas C. Weaver" wrote: > > Depending on the FPGA and the IO, you may need 2 or even 3 voltages. > I remember seeing some cute little switching power supplies which did > this. Any useful links? I'm targetting very low power consumption (who isn't?!), so the provision of several voltages is potentially problematic. Certainly don't want the heating/resistive losses associated with voltage regulators, so maybe miniature switched mode might be the way to go. > >Clock generator > > Probably want it socketed, but not necessarily. If soldered on, make > it high frequency, its easier to downclock then upclock. I haven't played with Xilinx clock management yet, DCM and all that. But if I have a fixed external clock, say 133MHz, can I expect to achieve reasonable application sdpecific clock frequencies within the device? ie 133MHz coming in, down-clock that to 100, or 66, or 50, or whatever? Obviously integer clock division is trivial, but what about non-integer? Also, can I get the FPGA to down-clock, and also export that reduced clock to external circuitry? > >Have I missed anything? > > Bypass capacitors. Probably a blinkenlight and a reset button, and > probably a power button too. Yep, good call, especially for prototyping. "Is it working? Yes, I've got a 2 HZ blinking light, just like I expected!" > You might also want to toss on a small > LCD display, they are cheap and only need a few pins, but can convey a > lot of information that way. Hmm interesting idea, once again could be very useful for prototyping. > Also, an FPGA which can't talk to anything is pretty useless. I'd say > include a high density connector to a daughtercard which you can put > whatever sorts of IOs you want. Yup. > Xilinx makes an ASIC to do this (SystemACE), you can hook it up to a > compact flash part. IF you use flash, use compact flash, having > removability and program-anywhere is nice. I read the system ACE doco - very interesting stuff. Thanks for your reply. John ###### From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system Date: Mon, 9 Sep 2002 23:40:01 +0000 (UTC) Organization: University of California, Berkeley, EECS Department Lines: 63 Message-ID: References: <3D7BED91.7FFDD8B8@qut.edu.au> <3D7D2D90.E14FFF66@qut.edu.au> NNTP-Posting-Host: ribbit.cs.berkeley.edu X-Trace: agate.berkeley.edu 1031614801 98784 128.32.112.203 (9 Sep 2002 23:40:01 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Mon, 9 Sep 2002 23:40:01 +0000 (UTC) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Originator: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:20813 In article <3D7D2D90.E14FFF66@qut.edu.au>, John Williams wrote: >> Depending on the FPGA and the IO, you may need 2 or even 3 voltages. >> I remember seeing some cute little switching power supplies which did >> this. > >Any useful links? I'm targetting very low power consumption (who >isn't?!), so the provision of several voltages is potentially >problematic. Certainly don't want the heating/resistive losses >associated with voltage regulators, so maybe miniature switched mode >might be the way to go. I remember seeing ones from Lucent a couple years ago, but can't find a reference. Some companies make small ones that BGA mount for cellphone applications (4-6V input, 1.5V output or similar), but the current was only 1/2 an amp (so under a watt, you probably want to be ABLE to draw a few watts), that google was able to find. http://www.vishay.com/document/10106/10106.pdf has ones that are 1.5W max power, 85-90% efficient, 3.6 to 6V input, 1.5 to 3.6V output (settable by a resister). I don't know if these in particular can be run in parallel, but the lucent ones could. >I haven't played with Xilinx clock management yet, DCM and all that. >But if I have a fixed external clock, say 133MHz, can I expect to >achieve reasonable application sdpecific clock frequencies within the >device? ie 133MHz coming in, down-clock that to 100, or 66, or 50, or >whatever? Obviously integer clock division is trivial, but what about >non-integer? Integer power of two is easy. Integer any power is easy if you don't mind a 50/50 duty cycle. You could feed it back through the DLL to give you back a 50/50 duty cycle IIRC. >Also, can I get the FPGA to down-clock, and also export that reduced >clock to external circuitry? No problem. And you can PLL it so it is the same phase as the internal one, at least on the virtex families, IIRC. >> Bypass capacitors. Probably a blinkenlight and a reset button, and >> probably a power button too. > >Yep, good call, especially for prototyping. "Is it working? Yes, I've >got a 2 HZ blinking light, just like I expected!" You probably want a hard reset, a "soft" reset (a signal pin), and 2 blinkenlights. You can just use surface mount LEDs and switches. >> You might also want to toss on a small >> LCD display, they are cheap and only need a few pins, but can convey a >> lot of information that way. > >Hmm interesting idea, once again could be very useful for prototyping. Probably overall, they ARE cheap. And it is amazing teh amount of information you can convey for debugging purposes. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: "Jan Gray" Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system Date: Mon, 9 Sep 2002 18:55:12 -0700 Organization: Gray Research LLC Lines: 19 Message-ID: References: <3D7BED91.7FFDD8B8@qut.edu.au> <3D7D2D90.E14FFF66@qut.edu.au> NNTP-Posting-Host: a5.f7.c9.e5 X-Server-Date: 10 Sep 2002 02:01:45 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.news2me.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!stamper.news.atl.earthlink.net!harp.news.atl.earthlink.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:20823 > >> You might also want to toss on a small > >> LCD display, they are cheap and only need a few pins, but can convey a > >> lot of information that way. > Probably overall, they ARE cheap. And it is amazing teh amount of > information you can convey for debugging purposes. For prototyping, I have an on-chip text display generator core that uses a handful of LUTs and two 512 B BRAMs to drive a VGA monitor at (5+1)*32 pixels by (8+2)*3*16 lines, ~60 Hz. The second BRAM is used as a 96x5x8 character generator ROM for display of ASCII characters 0x20-0x7F. Externally, IIRC, it requires 3 pins, a couple of resistors, and a VGA connector. (I'll grant you that if all you've got on hand is a 21" monitor, it looks a little funny.) Jan Gray, Gray Research LLC ###### Message-ID: <3D7D6749.2C56C5EB@qut.edu.au> Date: Tue, 10 Sep 2002 13:30:17 +1000 From: John Williams X-Mailer: Mozilla 4.78 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system References: <3D7BED91.7FFDD8B8@qut.edu.au> <3D7D2D90.E14FFF66@qut.edu.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: hpc2.scsn.bee.qut.edu.au X-Trace: 10 Sep 2002 13:31:52 +1000, hpc2.scsn.bee.qut.edu.au Lines: 28 X-Authenticated-User: williaj2 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!news1.optus.net.au!optus!bunyip.cc.uq.edu.au!news.qut.edu.au!hpc2.scsn.bee.qut.edu.au Xref: chonsp.franklin.ch comp.arch.fpga:20788 Jan Gray wrote: > > > >> You might also want to toss on a small > > >> LCD display, they are cheap and only need a few pins, but can convey a > > >> lot of information that way. > > > Probably overall, they ARE cheap. And it is amazing teh amount of > > information you can convey for debugging purposes. > > For prototyping, I have an on-chip text display generator core that uses a > handful of LUTs and two 512 B BRAMs to drive a VGA monitor at (5+1)*32 > pixels by (8+2)*3*16 lines, ~60 Hz. Anyone for Pong?! :) > (I'll grant you that if all you've got on hand is a 21" monitor, > it looks a little funny.) A bit like plugging an Atari 2600 into a video projector! Still, it's an interesting and cheap solution to get info out of the FPGA during prototyping. A couple of resistors and a VGA socket are much cheaper than the serial-driven LCD displays I've seen around the place. John ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system Date: Tue, 10 Sep 2002 04:59:21 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <3D7BED91.7FFDD8B8@qut.edu.au> <3D7D2D90.E14FFF66@qut.edu.au> X-Complaints-To: abuse@supernews.com Lines: 16 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!freenix!sn-xit-05!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:20820 > Yep, good call, especially for prototyping. "Is it working? Yes, I've > got a 2 HZ blinking light, just like I expected!" I'd go slightly farther and suggest several debugging connections - places where you can conveniently connect a scope and/or an external input. Might as well put LEDs on them unless you are really tight on board space. But I like LEDs. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### From: Silvio Lauckner Newsgroups: comp.arch.fpga Subject: Re: minimalist FPGA system Date: Tue, 10 Sep 2002 13:07:57 +0200 Organization: Ilmenau Technical University Lines: 28 Message-ID: <3D7DD28D.7D3ABCCC@inf-technik.tu-ilmenau.de> References: <3D7BED91.7FFDD8B8@qut.edu.au> NNTP-Posting-Host: hektor.inf-technik.tu-ilmenau.de Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------C60DE99D24C8DDAB6E53733D" X-Trace: piggy.rz.tu-ilmenau.de 1031655981 13165 141.24.93.19 (10 Sep 2002 11:06:21 GMT) X-Complaints-To: usenet@piggy.rz.tu-ilmenau.de NNTP-Posting-Date: Tue, 10 Sep 2002 11:06:21 +0000 (UTC) X-Mailer: Mozilla 4.61 [en] (X11; I; SunOS 5.7 sun4m) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!news-mue1.dfn.de!news-lei1.dfn.de!news.uni-jena.de!news_alt.tu-ilmenau.de!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:20827 --------------C60DE99D24C8DDAB6E53733D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I just built up my own development board a couple years ago. Have a look at: www.inf-technik.tu-ilmenau.de/~lauckner/misc.html Silvio --------------C60DE99D24C8DDAB6E53733D Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit I just built up my own development board a couple years ago.
Have a look at:  www.inf-technik.tu-ilmenau.de/~lauckner/misc.html

Silvio
  


 

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