Newsgroups: comp.arch.fpga Date: Fri, 2 Aug 2002 15:18:29 -0400 From: David Wentzlaff Subject: Silicon Area for Xilinx FPGAs Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Lines: 33 NNTP-Posting-Host: catfish.lcs.mit.edu X-Trace: 1028315913 senator-bedfellow.mit.edu 3933 18.111.0.152 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.mathworks.com!bloom-beacon.mit.edu!senator-bedfellow.mit.edu!dreaderd!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19804 Hi Comp.Arch.FPGAers, I am working on my master's thesis and in it I am trying to compare modern architectures, Raw (What my group does and I built part of), FPGAs and ASICs for some applications. To properly do this comparison I need to get some area numbers for Xilinx FPGAs. I have scoured pretty heavily and surprisingly I have had a hard time figuring out even the total die size of any current Virtex II FPGA. This surprised me because the overall die size doesn't tell anything secret, or at least info I couldn't get from simply disassembling a Virtex II part. Anyways I was wondering if anybody has area numbers for the die size of a Virtex II part(Any one will do because I will normalize it)? Ultimately what I really want is the area in mm^2 of a Slice/CLB on this architecture. I am most interested in those numbers because I want to try to mitigate area expansion caused by block RAMs. Unfortunately even Slice/CLB size is not completely accurate because of area caused by the switches but I can try a fudge factor. Oh, some of you may be wondering why I want Virtex II specifically, well the comparisons I am making are all in 0.15um and I have heard that the UMC process that Xilinx is using for these is very similar to the 0.15um that we are using with IBM, and thus a fair comparison. But if anybody knows of these area numbers for a Virtex-E that would also be appreciated. Also if anybody knows of a good document with these numbers, all pointers will be appreciated, and rewarded with some cookies, yes I am willing to mail cookies to get accurate numbers for my thesis. Thanks, David Wentzlaff ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Silicon Area for Xilinx FPGAs Date: 03 Aug 2002 00:31:20 +0200 Organization: My own Private Self Lines: 73 Message-ID: <6u4recriyv.fsf@chonsp.franklin.ch> References: NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1028327481 1102 10.0.3.2 (2 Aug 2002 22:31:21 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Aug 2002 22:31:21 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:19811 David Wentzlaff writes: > scoured pretty heavily and surprisingly I have had a hard time figuring > out even the total die size of any current Virtex II FPGA. This surprised > me because the overall die size doesn't tell anything secret, It apparently scares some types of customers who do size->transistors calculations for reliability calculations. Problem is that FPGAs have an far higher tolerance for failled transistors, because most are never used. So the vendors want gate level comparisons, not chip size or transistor counts. So they make such calculations as difficult as possible. > Ultimately what I really want is the area in mm^2 of a Slice/CLB on this > architecture. > > Oh, some of you may be wondering why I want Virtex II > comparison. But if anybody knows of these area numbers for a Virtex-E > that would also be appreciated. Well I can not give you Virtex-II data, because I have none. Such data is still sparse. But for the better documented Virtex, Virtex-E, Virtex-EM, Spartan-II and Spartan-IIE my calculation goes: 1 CLB = 48x18 (=864) bits. That is 864*5 (=4320) transistors config SRAM, about 700 transistors PIPs, about 4*200 transistors LUTs and a bit of "left over" stuff. Gives about 6k transistors/CLB, so equivalent of an 1k SRAM chip for each CLB. 1 BRAM = (64+27)*72 (= 6552) config bits. That with 6 transistors per bit in the "27" section and most likely more (8-10?) in the "64" section. So make them about 50k transistors/BRAM, or one 8k SRAM for each BRAM. So an XCV1000 would be 64*96*6k + 32*50k (= 36864k + 1600k). Add the IOBs and programming circuits and that is about an 40mio transistor chip. And an XCV1000E just does 2*16->6*16 BRAMs, so it adds about 3.2mio. And an XCV405E (Virtex-EM extra memory) would be 40*60*6k + 14*10*50k (= 14400k + 7000k) so about 22 mio, 2/3 CLB and 1/3 BRAM. > architecture. I am most interested in those numbers because I want to try > to mitigate area expansion caused by block RAMs. Unfortunately even A further known number for the older ones is, that one BRAM is 4 CLBs high and 2.5 CLBs wide. > Also if anybody knows of a good document with these numbers, all > pointers will be appreciated, XAPP138 and XAPP151 from the Xilinx Application notes are about the best low level docu. See: http://www.xilinx.com/apps/xapp.htm > and rewarded with some cookies, yes I am > willing to mail cookies to get accurate numbers for my thesis. :-) -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domain ###### From: Kevin Brace Newsgroups: comp.arch.fpga Subject: Re: Silicon Area for Xilinx FPGAs Date: Fri, 02 Aug 2002 22:10:32 -0500 Organization: None Lines: 63 Sender: kevinbraceusenet@hotmail.com Message-ID: References: NNTP-Posting-Host: 0-1pool32-117.nas11.oakbrook1.il.us.da.qwest.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: newsreader.mailgate.org 1028344025 13165 63.155.32.117 (3 Aug 2002 03:07:05 GMT) X-Complaints-To: abuse@mailgate.org NNTP-Posting-Date: Sat, 3 Aug 2002 03:07:05 +0000 (UTC) X-Mailer: Mozilla 4.79 [en] (Win98; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsreader.mailgate.org!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19815 David Wentzlaff wrote: > > Hi Comp.Arch.FPGAers, > > I am working on my master's thesis and in it I am trying to > compare modern architectures, Raw (What my group does and I built part > of), FPGAs and ASICs for some applications. To properly do this > comparison I need to get some area numbers for Xilinx FPGAs. I have > scoured pretty heavily and surprisingly I have had a hard time figuring > out even the total die size of any current Virtex II FPGA. This surprised > me because the overall die size doesn't tell anything secret, or at least > info I couldn't get from simply disassembling a Virtex II part. > > Anyways I was wondering if anybody has area numbers for the die > size of a Virtex II part(Any one will do because I will normalize it)? > Ultimately what I really want is the area in mm^2 of a Slice/CLB on this > architecture. I am most interested in those numbers because I want to try > to mitigate area expansion caused by block RAMs. Unfortunately even > Slice/CLB size is not completely accurate because of area caused by the > switches but I can try a fudge factor. > I am sure for your purpose, if there were published information about the die size of various FPGAs, it will make your life easier, but if it is so hard to get the information, why not buy a Virtex-E and a Virtex-II from a Xilinx distributor, and open up the package? It will cost you couple hundred dollars (Assuming that you purchased a smaller part.), but at least you won't have to keep wasting time trying to get that information. After you open up the package, why not keep the chip as a souvenir? I have heard of a company called Chipworks (http://www.chipworks.com) that specializes in analyzing semiconductor devices. Several months ago, I saw die pictures of Altera and Xilinx parts, but I can no longer seem to find them. > Oh, some of you may be wondering why I want Virtex II > specifically, well the comparisons I am making are all in 0.15um and I > have heard that the UMC process that Xilinx is using for these is very > similar to the 0.15um that we are using with IBM, and thus a fair > comparison. But if anybody knows of these area numbers for a Virtex-E > that would also be appreciated. > > > Thanks, > David Wentzlaff I believe IBM, Infineon, and UMC collaborated on a common bulk CMOS process technology (I believe it is called WorldLogic.), and if I remember it correctly, 0.13u process is the first process technology out of that collaboration. I heard that currently Virtex-II Pro is being manufactured by IBM, but it will be transferred to UMC eventually, presumably to cut cost. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) ###### From: Uwe Bonnes Newsgroups: comp.arch.fpga Subject: Re: Silicon Area for Xilinx FPGAs Date: Sat, 3 Aug 2002 09:21:38 +0000 (UTC) Organization: TU Darmstadt Lines: 24 Message-ID: References: NNTP-Posting-Host: elektron.ikp.physik.tu-darmstadt.de X-Trace: news.tu-darmstadt.de 1028366498 24296 130.83.24.72 (3 Aug 2002 09:21:38 GMT) X-Complaints-To: news@news.tu-darmstadt.de NNTP-Posting-Date: Sat, 3 Aug 2002 09:21:38 +0000 (UTC) User-Agent: tin/1.4.2-20000205 ("Possession") (UNIX) (Linux/2.2.18 (i586)) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.usenet-edu.net!usenet-edu.net!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!news.belwue.de!news.tu-darmstadt.de!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19813 David Wentzlaff wrote: : Hi Comp.Arch.FPGAers, : I am working on my master's thesis and in it I am trying to : compare modern architectures, Raw (What my group does and I built part : of), FPGAs and ASICs for some applications. To properly do this : comparison I need to get some area numbers for Xilinx FPGAs. I have : scoured pretty heavily and surprisingly I have had a hard time figuring : out even the total die size of any current Virtex II FPGA. This surprised : me because the overall die size doesn't tell anything secret, or at least : info I couldn't get from simply disassembling a Virtex II part. : Anyways I was wondering if anybody has area numbers for the die : size of a Virtex II part(Any one will do because I will normalize it)? : Ultimately what I really want is the area in mm^2 of a Slice/CLB on this : architecture. I am most interested in those numbers because I want to try What about X-Raying the packaged chip, perhaps at a friendly dentist? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------