From: "Tom D" Newsgroups: comp.arch.fpga Subject: Spartan clock mirroring Date: Mon, 15 Jul 2002 13:48:54 +0100 Organization: University College London Lines: 19 Message-ID: NNTP-Posting-Host: connell.ee.ucl.ac.uk X-Trace: uns-a.ucl.ac.uk 1026737037 15488 128.40.42.223 (15 Jul 2002 12:43:57 GMT) X-Complaints-To: usenet@ucl.ac.uk NNTP-Posting-Date: 15 Jul 2002 12:43:57 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!mango.news.easynet.net!easynet.net!Quza.UK.peer!nntp.gblx.net!newspeer.clara.net!news.clara.net!server3.netnews.ja.net!ucl.ac.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19294 I wish to use a stable crystal based oscillator to clock a Spartan IIE, preferably either at 200MHz, or if not possible then at 100MHz. The design also includes a DDS and ADC which need to be clocked at 200MHz, so I intend to use the same oscillator connected directly to these peripherals. I also need to drive a PLL with a reference frequency less than 40MHz to create an RF output at 2.4GHz which should be phase coherent with the stable oscillator. I hoped to use a DLL on the FPGA to divide the clock by 4 or 8 to create a 25MHz clock output, but the propagation delay is about 8ns which is highly significant at this frequency. Can the clock mirroring technique be used with clock division in order to create an output clock which is phase coherent with the master clock? (aside from the jitter created by the DLL which should hopefully be small). Thanks Tom ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Spartan clock mirroring Date: Mon, 15 Jul 2002 08:03:27 -0700 Organization: Xilinx Lines: 45 Message-ID: <3D32E43F.BD48607A@xilinx.com> References: NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.79 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!newsfeed.media.kyoto-u.ac.jp!spring.edu.tw!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19283 Tom, All of the DLL outputs are phase locked to the CLKIN of the DLL. Thus the CLKDV will also be phase aligned with the rising edge of CLKIN. The jitter of the DLL should be attenuated well by the external PLL creating the 2.4 GHz, as all of the power in the jitter spectrum of a DLL are at high frequencies (updates to taps are made every 6 times the "jitter filter" register values number of input clocks), which get attenuated well by frequency multipliers. It is low frequency jitter that can not be attenuated well by a frequency multiplier. To shift the jitter power spectral density up in frequency, set the jitter filter to 0xFFFFh (2's complement number, or every 6 input clocks a tap is updated). Jitter on the CLKDV output will be ~ 200 -> 300 ps P-P, which should not be a problem for the reference to the frequency multiplier. Use of a master oscillator which then goes to the DDS, the ADC, and the FPGA fed from a clock buffer that drives all three using LVDS or LVPECL is highly recommended. Integrated Circuits Systems, Inc (ICST.com) has a lot of good parts just for this purpose. Their 8745 PLL is also great for attenuating jitter (tested in the FPGA Lab). Austin Tom D wrote: > I wish to use a stable crystal based oscillator to clock a Spartan IIE, > preferably either at 200MHz, or if not possible then at 100MHz. The design > also includes a DDS and ADC which need to be clocked at 200MHz, so I intend > to use the same oscillator connected directly to these peripherals. > > I also need to drive a PLL with a reference frequency less than 40MHz to > create an RF output at 2.4GHz which should be phase coherent with the stable > oscillator. I hoped to use a DLL on the FPGA to divide the clock by 4 or 8 > to create a 25MHz clock output, but the propagation delay is about 8ns which > is highly significant at this frequency. Can the clock mirroring technique > be used with clock division in order to create an output clock which is > phase coherent with the master clock? (aside from the jitter created by the > DLL which should hopefully be small). > > Thanks > > Tom