From: stevetshannon@yahoo.com (Steve T Shannon) Newsgroups: comp.arch.fpga Subject: serial configuration in parallel? Xilinx Spartan-II Date: 13 Jul 2002 08:52:52 -0700 Organization: http://groups.google.com/ Lines: 14 Message-ID: NNTP-Posting-Host: 18.114.0.138 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1026575572 8858 127.0.0.1 (13 Jul 2002 15:52:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 13 Jul 2002 15:52:52 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19256 Hello! I am designing a system with a series of identical add-in data acq. cards. Each card interfaces with a shared bus via a Spartan-II from xilinx. I am trying to avoid the expensive serial PROM configuration option, and instead would like to configure each device in slave serial mode. Each FPGA (of which there will be 1/board, or ~16) will be running identical code. Since both the /INIT and DONE lines are open-drain, can i just wire all the DIN, CCLK, /INIT, and DONE lines for each FPGA in parallel, and clock data in like it's a single FPGA? All FPGAs would need to be ready to receive the bitstream (i.e. have /INIT high) in order for the aggregate /INIT to actually be high; similar behavior would be apparent with DONE. Is there any reason why this won't work?? Thanks, Steve ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: serial configuration in parallel? Xilinx Spartan-II Date: Sat, 13 Jul 2002 16:46:29 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: X-Complaints-To: newsabuse@supernews.com Lines: 21 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!sn-xit-05!sn-xit-06!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:19251 >in slave serial mode. Each FPGA (of which there will be 1/board, or >~16) will be running identical code. Since both the /INIT and DONE >lines are open-drain, can i just wire all the DIN, CCLK, /INIT, and >DONE lines for each FPGA in parallel, and clock data in like it's a >single FPGA? All FPGAs would need to be ready to receive the bitstream >(i.e. have /INIT high) in order for the aggregate /INIT to actually be >high; similar behavior would be apparent with DONE. Is there any >reason why this won't work?? Beware of glitches and cooties on your clock signals. Other than that, I can't see any reason it won't work. You might want some way to isolate the DONE signals for debugging so you can figure out which board isn't working right. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam. ###### Message-ID: <3D30CD84.F1753F1C@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net Organization: home X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: serial configuration in parallel? Xilinx Spartan-II References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 19 Date: Sun, 14 Jul 2002 01:01:39 GMT NNTP-Posting-Host: 209.179.199.83 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1026608499 209.179.199.83 (Sat, 13 Jul 2002 18:01:39 PDT) NNTP-Posting-Date: Sat, 13 Jul 2002 18:01:39 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!upp1.onvoy!onvoy.com!news-out.visi.com!hermes.visi.com!newsfeed1.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!3ab61c21!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19265 This will work! :-) Peter Alfke, Xilinx Applications Steve T Shannon wrote: > Hello! I am designing a system with a series of identical add-in data > acq. cards. Each card interfaces with a shared bus via a Spartan-II > from xilinx. I am trying to avoid the expensive serial PROM > configuration option, and instead would like to configure each device > in slave serial mode. Each FPGA (of which there will be 1/board, or > ~16) will be running identical code. Since both the /INIT and DONE > lines are open-drain, can i just wire all the DIN, CCLK, /INIT, and > DONE lines for each FPGA in parallel, and clock data in like it's a > single FPGA? All FPGAs would need to be ready to receive the bitstream > (i.e. have /INIT high) in order for the aggregate /INIT to actually be > high; similar behavior would be apparent with DONE. Is there any > reason why this won't work?? > > Thanks, Steve