From: Steve Charlwood Newsgroups: comp.arch.fpga Subject: What proportion of an FPGA's configuration data is used for routing? Date: Sat, 13 Jul 2002 20:05:25 +0100 Organization: The University of Birmingham news server Lines: 19 Message-ID: <3D3079F5.8060207@bham.ac.uk> NNTP-Posting-Host: eee122.bham.ac.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: sun3.bham.ac.uk 1026587347 21241 147.188.145.42 (13 Jul 2002 19:09:07 GMT) X-Complaints-To: usenet@sun3.bham.ac.uk NNTP-Posting-Date: Sat, 13 Jul 2002 19:09:07 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows; U; WinNT4.0; en-GB; rv:0.9.4) Gecko/20011019 Netscape6/6.2 X-Accept-Language: en-gb, en-us Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.usenet-edu.net!usenet-edu.net!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!lnewspeer00.lnd.ops.eu.uu.net!emea.uu.net!server1.netnews.ja.net!news.bham.ac.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19261 Hi all, Does anyone have any good estimates of the proportion of an FPGA's configuration memory used for defining the interconnect, or can provide me with a sensible way of estimating the number of configuration bits used by a Xilinx Virtex CLB (not including routing external to the CLB)? This information could probably be determined for Xilinx devices by someone with the JBits toolkit (and time on their hands). Has anyone done this? I would be interested in any data, but especially for Xilinx chips: XC4000X, Virtex and later architectures. Any help would be appreciated. From XAPP151 I've estimated the total number of coniguration bits per CLB and per IOB _including_ the routing, and would like to split this figure up. Regards, Steve ###### From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Newsgroups: comp.arch.fpga Subject: Re: What proportion of an FPGA's configuration data is used for routing? Date: Sat, 13 Jul 2002 19:31:19 +0000 (UTC) Organization: Unknown Lines: 27 Message-ID: References: <3D3079F5.8060207@bham.ac.uk> NNTP-Posting-Host: soda.csua.berkeley.edu X-Trace: agate.berkeley.edu 1026588679 57548 128.32.247.226 (13 Jul 2002 19:31:19 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Sat, 13 Jul 2002 19:31:19 +0000 (UTC) Originator: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19245 In article <3D3079F5.8060207@bham.ac.uk>, Steve Charlwood wrote: >Hi all, > >Does anyone have any good estimates of the proportion of an FPGA's >configuration memory used for defining the interconnect, or can provide >me with a sensible way of estimating the number of configuration bits >used by a Xilinx Virtex CLB (not including routing external to the CLB)? >This information could probably be determined for Xilinx devices by >someone with the JBits toolkit (and time on their hands). Has anyone >done this? I would be interested in any data, but especially for Xilinx >chips: XC4000X, Virtex and later architectures. > >Any help would be appreciated. From XAPP151 I've estimated the total >number of coniguration bits per CLB and per IOB _including_ the routing, > and would like to split this figure up. Easy way: A virtex slice contains 32 bits for LUT configuration, and ~25 bits (I may miscount by one or two) for the internal slice routing and configuration (based on the slice internals diagram for Jbits). So just subtract. So what's the number? -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: Steve Charlwood Newsgroups: comp.arch.fpga Subject: Re: What proportion of an FPGA's configuration data is used for routing? Date: Sat, 13 Jul 2002 22:58:17 +0100 Organization: The University of Birmingham news server Lines: 25 Message-ID: <3D30A279.2090601@bham.ac.uk> References: <3D3079F5.8060207@bham.ac.uk> NNTP-Posting-Host: eee122.bham.ac.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Trace: sun3.bham.ac.uk 1026597719 1066 147.188.145.42 (13 Jul 2002 22:01:59 GMT) X-Complaints-To: usenet@sun3.bham.ac.uk NNTP-Posting-Date: Sat, 13 Jul 2002 22:01:59 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows; U; WinNT4.0; en-GB; rv:0.9.4) Gecko/20011019 Netscape6/6.2 X-Accept-Language: en-gb, en-us Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!newsfeed.esat.net!lnewspeer01.lnd.ops.eu.uu.net!lnewspeer00.lnd.ops.eu.uu.net!emea.uu.net!server1.netnews.ja.net!news.bham.ac.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19260 Hi all, Based on Nick Weaver's estimate (Thanks, Nick) of configuration bits for a slice (57), and XAPP151, from which I've derived a figure of 864 bits/CLB (including both logic and routing), the proportion of configuation bits used for routing the logic in Virtex is 86.8%. I've had a look at the routing diagram for the XC4000X devices (Figure 27 of the 4000E/X datasheet), and estimate the configuration bits for routing to be ~580. However, an XC4085XL requires 1,924,240 bits of configuration data in total. It also has 3,136 CLBs and 448 IOBs. Even assuming that the IOBs require NO configuration at all (!), this would only leave 614 bits per CLB, which implies that the estimate of 580 is too high (each CLB requiring 32 bits for the LUTs, plus some for local interconnect). In arriving at this figure of 580, I've assumed 6 bits for each of the elements of the swtich matrix, and six for the three corner-turning connections of the quadlines (marked as diamonds in the diagram). Does anyone have any idea where an error is being introduced? Regards, Steve