From: Weifeng Xu Newsgroups: comp.arch.fpga Subject: Bitstream Verification (JBITS) Date: Tue, 02 Jul 2002 12:02:49 -0400 Organization: College of Engineering, University of Massachusetts Lines: 12 Message-ID: <3D21CEA9.21A0C443@ecs.umass.edu> NNTP-Posting-Host: kendall.ecs.umass.edu Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: odo.ecs.umass.edu 1025625784 20776 128.119.85.79 (2 Jul 2002 16:03:04 GMT) X-Complaints-To: usenet@news.ecs.umass.edu NNTP-Posting-Date: 2 Jul 2002 16:03:04 GMT X-Mailer: Mozilla 4.7 [en] (Win98; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!elk.ncren.net!news.umass.edu!news.ecs.umass.edu!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18983 Hi, I am developping a Java program based on JBITS which can generate a bitstream to configure the Xilinx Virtex FPGA directly. But I don't know whether there's some kind of tools can help check whether this bitstream can actually work on FPGA instead of burnning it. I know there's Virtex Device Simulator can do some simulation on bitstream, will the simulator check the bitstream and give some warning if there're two dirvers for one line? Thanks! Weifeng ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Bitstream Verification (JBITS) Date: 03 Jul 2002 00:50:37 +0200 Organization: My own Private Self Lines: 22 Message-ID: <6ufzz1zqv6.fsf@chonsp.franklin.ch> References: <3D21CEA9.21A0C443@ecs.umass.edu> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1025650237 309 10.0.3.2 (2 Jul 2002 22:50:37 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Jul 2002 22:50:37 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:18989 Weifeng Xu writes: > I am developping a Java program based on JBITS which can generate a > bitstream to configure the Xilinx Virtex FPGA directly. But I don't know > whether there's some kind of tools can help check whether this bitstream > can actually work on FPGA instead of burnning it. The generation process of JBits should ensure that, as long as you use the automatic routing. If you set individual PIPs, all bets are off. > I know there's Virtex Device Simulator can do some simulation on > bitstream, will the simulator check the bitstream and give some warning > if there're two dirvers for one line? Do not know that one. I would doubt it. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domain ###### From: Weifeng Xu Newsgroups: comp.arch.fpga Subject: Re: Bitstream Verification (JBITS) Date: Wed, 03 Jul 2002 11:50:04 -0400 Organization: College of Engineering, University of Massachusetts Lines: 33 Message-ID: <3D231D2C.9E97BD3E@ecs.umass.edu> References: <3D21CEA9.21A0C443@ecs.umass.edu> <6ufzz1zqv6.fsf@chonsp.franklin.ch> NNTP-Posting-Host: kendall.ecs.umass.edu Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: odo.ecs.umass.edu 1025711438 17483 128.119.85.79 (3 Jul 2002 15:50:38 GMT) X-Complaints-To: usenet@news.ecs.umass.edu NNTP-Posting-Date: 3 Jul 2002 15:50:38 GMT X-Mailer: Mozilla 4.7 [en] (Win98; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!elk.ncren.net!news.umass.edu!news.ecs.umass.edu!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18997 Unfortunately, I have to use some low level JBITS.set to make PIP connections. But I am wondering whether it's enough to apply some mechanism such as lookup table to check whether one routing wire has been drived before.I am not sure what's in Xilinx's checking process. Weifeng Neil Franklin wrote: > Weifeng Xu writes: > > > I am developping a Java program based on JBITS which can generate a > > bitstream to configure the Xilinx Virtex FPGA directly. But I don't know > > whether there's some kind of tools can help check whether this bitstream > > can actually work on FPGA instead of burnning it. > > The generation process of JBits should ensure that, as long as you use > the automatic routing. If you set individual PIPs, all bets are off. > > > I know there's Virtex Device Simulator can do some simulation on > > bitstream, will the simulator check the bitstream and give some warning > > if there're two dirvers for one line? > > Do not know that one. I would doubt it. > > -- > Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ > Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer > - Make your code truely free: put it into the public domain ###### From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Newsgroups: comp.arch.fpga Subject: Re: Bitstream Verification (JBITS) Date: Wed, 3 Jul 2002 16:21:06 +0000 (UTC) Organization: Unknown Lines: 19 Message-ID: References: <3D21CEA9.21A0C443@ecs.umass.edu> <6ufzz1zqv6.fsf@chonsp.franklin.ch> <3D231D2C.9E97BD3E@ecs.umass.edu> NNTP-Posting-Host: soda.csua.berkeley.edu X-Trace: agate.berkeley.edu 1025713266 96177 128.32.247.226 (3 Jul 2002 16:21:06 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Wed, 3 Jul 2002 16:21:06 +0000 (UTC) Originator: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19004 In article <3D231D2C.9E97BD3E@ecs.umass.edu>, Weifeng Xu wrote: > Unfortunately, I have to use some low level JBITS.set to make PIP >connections. But I am wondering whether it's enough to apply some >mechanism such as lookup table to check whether one routing wire has >been drived before.I am not sure what's in Xilinx's checking process. What are you trying to accomplish? An upstream-independant toolflow, or slightly higher level work? IF the later, you might consider outputting xdl instead, converting it to ncd, and pushing it throuh the xilinx router/static timing analysis/ and bitfile generator. I was going down the Jbits route myself for a while, and am now much happier using XDL. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: Weifeng Xu Newsgroups: comp.arch.fpga Subject: Re: Bitstream Verification (JBITS) Date: Wed, 03 Jul 2002 13:21:34 -0400 Organization: College of Engineering, University of Massachusetts Lines: 27 Message-ID: <3D23329E.FC9A2D6@ecs.umass.edu> References: <3D21CEA9.21A0C443@ecs.umass.edu> <6ufzz1zqv6.fsf@chonsp.franklin.ch> <3D231D2C.9E97BD3E@ecs.umass.edu> NNTP-Posting-Host: kendall.ecs.umass.edu Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: odo.ecs.umass.edu 1025716935 23303 128.119.85.79 (3 Jul 2002 17:22:15 GMT) X-Complaints-To: usenet@news.ecs.umass.edu NNTP-Posting-Date: 3 Jul 2002 17:22:15 GMT X-Mailer: Mozilla 4.7 [en] (Win98; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!snoopy.risq.qc.ca!elk.ncren.net!news.umass.edu!news.ecs.umass.edu!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18996 Actually, I wanna use JBITS to generate the bitstream based on output of some academic CAD tools. Those academic tools do have some design check. But I am afraid it's not enough. So I am wonderring whether there're some tools I can generate ncd from the bitstream. Nicholas Weaver wrote: > In article <3D231D2C.9E97BD3E@ecs.umass.edu>, > Weifeng Xu wrote: > > > Unfortunately, I have to use some low level JBITS.set to make PIP > >connections. But I am wondering whether it's enough to apply some > >mechanism such as lookup table to check whether one routing wire has > >been drived before.I am not sure what's in Xilinx's checking process. > > What are you trying to accomplish? An upstream-independant toolflow, > or slightly higher level work? > > IF the later, you might consider outputting xdl instead, converting it > to ncd, and pushing it throuh the xilinx router/static timing > analysis/ and bitfile generator. > > I was going down the Jbits route myself for a while, and am now much > happier using XDL. > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Bitstream Verification (JBITS) Date: 03 Jul 2002 20:54:38 +0200 Organization: My own Private Self Lines: 39 Message-ID: <6uznx84p75.fsf@chonsp.franklin.ch> References: <3D21CEA9.21A0C443@ecs.umass.edu> <6ufzz1zqv6.fsf@chonsp.franklin.ch> <3D231D2C.9E97BD3E@ecs.umass.edu> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1025722478 474 10.0.3.2 (3 Jul 2002 18:54:38 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 3 Jul 2002 18:54:38 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:19025 Weifeng Xu writes: [text reordered, newer response after older text, in proper chronological order, please post in proper order] > Neil Franklin wrote: > > > Weifeng Xu writes: > > > > > whether there's some kind of tools can help check whether this bitstream > > > can actually work on FPGA instead of burnning it. > > > > The generation process of JBits should ensure that, as long as you use > > the automatic routing. If you set individual PIPs, all bets are off. > Unfortunately, I have to use some low level JBITS.set to make PIP > connections. Oh, then you have no JBits safeguards. > But I am wondering whether it's enough to apply some mechanism such as lookup > table Lookup table is no use, as it does not know about routing or PIPs. > to check whether one routing wire has been drived before.I am not sure what's > in Xilinx's > checking process. Experiment. Make an bitfile which deliberately has an double driven line. Loead it into BoardScope and see if it complains. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domain ###### From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Newsgroups: comp.arch.fpga Subject: Re: Bitstream Verification (JBITS) Date: Wed, 3 Jul 2002 19:58:10 +0000 (UTC) Organization: Unknown Lines: 11 Message-ID: References: <3D21CEA9.21A0C443@ecs.umass.edu> <3D231D2C.9E97BD3E@ecs.umass.edu> <3D23329E.FC9A2D6@ecs.umass.edu> NNTP-Posting-Host: soda.csua.berkeley.edu X-Trace: agate.berkeley.edu 1025726290 8843 128.32.247.226 (3 Jul 2002 19:58:10 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Wed, 3 Jul 2002 19:58:10 +0000 (UTC) Originator: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:19042 In article <3D23329E.FC9A2D6@ecs.umass.edu>, Weifeng Xu wrote: >Actually, I wanna use JBITS to generate the bitstream based on output of some >academic CAD tools. Those academic tools do have some design check. But I am >afraid it's not enough. So I am wonderring whether there're some tools I can >generate ncd from the bitstream. Why not generate .xdl files with placement but no routing, and let the xilinx router (slow but pretty good) handle it? -- Nicholas C. Weaver nweaver@cs.berkeley.edu