From: "Young-Su Kwon" Newsgroups: comp.arch.fpga Subject: Virtex-E Readback. Date: Wed, 26 Jun 2002 18:15:49 +0900 Organization: Korea Research Environment Open Network Lines: 25 Message-ID: NNTP-Posting-Host: sunny.kaist.ac.kr X-Trace: news.kreonet.re.kr 1025082969 26873 143.248.239.119 (26 Jun 2002 09:16:09 GMT) X-Complaints-To: usenet@news.kreonet.re.kr NNTP-Posting-Date: Wed, 26 Jun 2002 09:16:09 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!newsfeed.dacom.co.kr!nntp.kreonet.re.kr!news.kreonet.re.kr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18849 Dear, I am doing Xilinx Virtex-E(XCV1000E) readback to capture register states. When I have compared "mydesign.rbb" to "readbackdata.bin" under "mydesign.msk" according to the Xilinx application note, it has failed. In other words, I have failed to verify the configuration data. It seems that the device works ok when I have probed some signals using Logic Analyzer. I have designed my C program according to the xilinx application note. Anybody has an idea why I have failed to verify configuration data or anybody has a customized C program that compares *.rbb and *.msk to the readback data? -- *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- Young-Su Kwon, Ph. D Student VLSI Systems Lab, KAIST yskwon@vslab.kaist.ac.kr *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- ###### Message-ID: <3d19971e@pfaff.ethz.ch> From: Christian Plessl Subject: Re: Virtex-E Readback. Newsgroups: comp.arch.fpga Date: Wed, 26 Jun 2002 12:27:43 +0200 References: Lines: 64 User-Agent: KNode/0.6.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit NNTP-Posting-Host: tec-pc-cp.ethz.ch X-Trace: pfaff.ethz.ch 1025087262 tec-pc-cp.ethz.ch (26 Jun 2002 12:27:42 +0200) Organization: Swiss Federal Institute of Technology (ETHZ) Path: chonsp.franklin.ch!pfaff.ethz.ch Xref: chonsp.franklin.ch comp.arch.fpga:18893 Hi We had similar problems using Virtex-1000 devices (not Virtex E). I guess your refer to Xilinx appnote 138, which explains the comparison of the original and the readback bitstream. If I remember right, its quite a while since then, there were 2 problems: a) the bitstream that is read back from the board starts with a spurious superflous word. Although Xilinx confirmed that certain devices show this behavior, we did not find out, what this additional word actually means, so we just ignored it. b) there was/is an error in xapp 138. According to xapp 132 the rbb file starts with a header and a padding word, which must be skipped (32 bytes). What xapp 138 does _not_ tell you, is that this header is followed by a pad frame and a padding word (156 bytes in the case of a XVC1000) which must _also_ be skipped. For the maskfile we also assume also that tehre is an error in the documentation. xapp138 tells you to skip the header (28 bytes for XVC1000). Again, we found that xapp138 doesnt tell that this header is again followed by a padding word (4bytes) and a padframe+paddingword (once again 156 bytes for a XVC1000) which must also be skipped. After correcting these 2 problems verification of the readback bitstream worked for us. I will send you the C-code that worked for us, by private mail. Regards, Chris Young-Su Kwon wrote: > Dear, > > I am doing Xilinx Virtex-E(XCV1000E) readback to capture register states. > When I have compared "mydesign.rbb" to "readbackdata.bin" under > "mydesign.msk" according to the Xilinx application note, it has failed. > In other words, I have failed to verify the configuration data. > It seems that the device works ok when I have probed some signals > using Logic Analyzer. > I have designed my C program according to the xilinx application note. > Anybody has an idea why I have failed to verify configuration data > or anybody has a customized C program that compares *.rbb and *.msk > to the readback data? > > > -- > > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- > Young-Su Kwon, > Ph. D Student > VLSI Systems Lab, KAIST > yskwon@vslab.kaist.ac.kr > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- -- Christian Plessl remove 'remove' from email-address when replying