From: John_H Newsgroups: comp.arch.fpga Subject: Re: Internal oscillator in CPLD? Date: Mon, 17 Jun 2002 19:42:53 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3D0E9E2D.E7FC314D@mail.com> X-Mailer: Mozilla 4.73 [en] (Win98; U) X-Accept-Language: en MIME-Version: 1.0 References: <3D0E68F1.92509487@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 46 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18583 ??? ------ |B +----|---'\/\/\,--+ | |A | +-<|-|-----||-----+ | | | +|>o-|---'\/\/\,--+ |C ------ This looks like the junction of the three devices will always be (Voh+Vol)/2. I feel like I'm missing something big but there's a real interesting concept here that I've misinterpreted. I'd love to understand the details. Peter Alfke wrote: > > If you can afford to dedicate three pins ( 2 outputs and one input) to > this task, it is easy: > Input A internally drives output B non-inverted, and also output C > inverted. > Connect a resistor to pin A, the same value resistor to pin C, and a > capacitor to pin B, and interconnect the other ends of these three > components together. > Start with two 1 kilohm resistors and 470 pF > Surprisingly (not really, there is mathematical proof) stable over > temperature and voltage. > > Peter Alfke, Xilinx Applications > ==================================== > David Rogoff wrote: > > > Hi. > > > > I trying to put together a really small, cheap circuit using a CPLD > > (probably Xilinx 9500). I don't want to have to use a seperate > > oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz > > (doesn't need to be accurate) clock wtih only the CPLD. I checked the > > archives, and a Xilinx data book, but didn't see anything. > > > > Thanks! > > > > David ###### Message-ID: <3D0EA06C.7090303@intellidesign.com.au> From: James Kennedy Organization: IntelliDesign Pty Ltd User-Agent: Mozilla/5.0 (Windows; U; Win98; en-US; rv:1.0.0) Gecko/20020530 X-Accept-Language: en-us, en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Internal oscillator in CPLD? References: <3D0E68F1.92509487@xilinx.com> <3D0E9E2D.E7FC314D@mail.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Lines: 66 Date: Tue, 18 Jun 2002 02:53:56 GMT NNTP-Posting-Host: 203.45.133.192 X-Complaints-To: news@bigpond.net.au X-Trace: news-server.bigpond.net.au 1024368836 203.45.133.192 (Tue, 18 Jun 2002 12:53:56 EST) NNTP-Posting-Date: Tue, 18 Jun 2002 12:53:56 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!newsfeed.belnet.be!news.belnet.be!newsfeed.news2me.com!logbridge.uoregon.edu!newsfeed.stanford.edu!headwall.stanford.edu!newsfeed-west.nntpserver.com!hub1.meganetnews.com!nntpserver.com!intgwpad.nntp.telstra.net!news.telstra.net!news-server.bigpond.net.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18549 You've got the resistor on B and the cap on A around the wrong way... should be cap on B and resistor on A. Cheers, James John_H wrote: > ??? > > ------ > |B > +----|---'\/\/\,--+ > | |A | > +-<|-|-----||-----+ > | | | > +|>o-|---'\/\/\,--+ > |C > ------ > > This looks like the junction of the three devices will always be > (Voh+Vol)/2. I feel like I'm missing something big but there's a real > interesting concept here that I've misinterpreted. I'd love to > understand the details. > > > Peter Alfke wrote: > >>If you can afford to dedicate three pins ( 2 outputs and one input) to >>this task, it is easy: >>Input A internally drives output B non-inverted, and also output C >>inverted. >>Connect a resistor to pin A, the same value resistor to pin C, and a >>capacitor to pin B, and interconnect the other ends of these three >>components together. >>Start with two 1 kilohm resistors and 470 pF >>Surprisingly (not really, there is mathematical proof) stable over >>temperature and voltage. >> >>Peter Alfke, Xilinx Applications >>==================================== >>David Rogoff wrote: >> >> >>>Hi. >>> >>>I trying to put together a really small, cheap circuit using a CPLD >>>(probably Xilinx 9500). I don't want to have to use a seperate >>>oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz >>>(doesn't need to be accurate) clock wtih only the CPLD. I checked the >>>archives, and a Xilinx data book, but didn't see anything. >>> >>>Thanks! >>> >>> David >> -- James Kennedy Electronics/Computer Design Engineer IntelliDesign Brisbane, Australia Tel: +61 7 3366 6478 Fax: +61 7 3366 6471 ###### Message-ID: <3D0EAF37.1693@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Internal oscillator in CPLD? References: <3D0E68F1.92509487@xilinx.com> <3D0E9E2D.E7FC314D@mail.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 68 Date: Tue, 18 Jun 2002 15:55:35 +1200 NNTP-Posting-Host: 203.79.102.48 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1024372634 203.79.102.48 (Tue, 18 Jun 2002 15:57:14 NZST) NNTP-Posting-Date: Tue, 18 Jun 2002 15:57:14 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!colt.net!newspeer.clara.net!news.clara.net!skynet.be!skynet.be!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18541 John_H wrote: > > ??? > > ------ > |B > +----|---'\/\/\,--+ > | |A | > +-<|-|-----||-----+ > | | | > +|>o-|---'\/\/\,--+ > |C > ------ > > This looks like the junction of the three devices will always be > (Voh+Vol)/2. I feel like I'm missing something big but there's a real > interesting concept here that I've misinterpreted. I'd love to > understand the details. ------ |A Ri +------|---'\/\/\,--+ | |B | +-|>-+-|-----||-----+ \ |\ | | | C | \ | \ | +----+ | | | / | / | |C Rf | |/ |/ +|>o---|---'\/\/\,--+ | -------- This is the best performance topology for a 3 terminal oscillator. Note that A -> B is positive feedback (non inv), and that B -> C is megative feedback (inv). Importantly, the REGEN output _must_ occur first, so C = !B; is better than C = !A; The circuit is stable at DC, but unstable at AC, and so oscillates. Terminal A, is very noise prone, and should be adjacent to a GND pin, terminal B should be adjacent to A, to give parasitic C positive feedback. Ri is a limiting resistor, and for best stability is larger than Rf, but they can be the same to reduce the BOM. Osc time constant is Constant.Rf.C, with a small Ri influence. Also, check that terminal A has a Vcc clamp diode, and is not a Vpp pin :) - jg > Peter Alfke wrote: > > > > If you can afford to dedicate three pins ( 2 outputs and one input) to > > this task, it is easy: > > Input A internally drives output B non-inverted, and also output C > > inverted. > > Connect a resistor to pin A, the same value resistor to pin C, and a > > capacitor to pin B, and interconnect the other ends of these three > > components together. > > Start with two 1 kilohm resistors and 470 pF > > Surprisingly (not really, there is mathematical proof) stable over > > temperature and voltage. > > > > Peter Alfke, Xilinx Applications ###### Message-ID: <3D0EB684.360A5424@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Internal oscillator in CPLD? References: <3D0E68F1.92509487@xilinx.com> <3D0E9E2D.E7FC314D@mail.com> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 51 Date: Tue, 18 Jun 2002 04:26:55 GMT NNTP-Posting-Host: 216.244.43.93 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1024374415 216.244.43.93 (Mon, 17 Jun 2002 21:26:55 PDT) NNTP-Posting-Date: Mon, 17 Jun 2002 21:26:55 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!newsfeed.vmunix.org!newsfeed.belnet.be!news.belnet.be!newsfeed.news2me.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!3ab61c21!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18531 John, just follow the instructions: resistor to A and to C, capacitor to B. Peter John_H wrote: > ??? > > ------ > |B > +----|---'\/\/\,--+ > | |A | > +-<|-|-----||-----+ > | | | > +|>o-|---'\/\/\,--+ > |C > ------ > > This looks like the junction of the three devices will always be > (Voh+Vol)/2. I feel like I'm missing something big but there's a real > interesting concept here that I've misinterpreted. I'd love to > understand the details. > > Peter Alfke wrote: > > > > If you can afford to dedicate three pins ( 2 outputs and one input) to > > this task, it is easy: > > Input A internally drives output B non-inverted, and also output C > > inverted. > > Connect a resistor to pin A, the same value resistor to pin C, and a > > capacitor to pin B, and interconnect the other ends of these three > > components together. > > Start with two 1 kilohm resistors and 470 pF > > Surprisingly (not really, there is mathematical proof) stable over > > temperature and voltage. > > > > Peter Alfke, Xilinx Applications > > ==================================== > > David Rogoff wrote: > > > > > Hi. > > > > > > I trying to put together a really small, cheap circuit using a CPLD > > > (probably Xilinx 9500). I don't want to have to use a seperate > > > oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz > > > (doesn't need to be accurate) clock wtih only the CPLD. I checked the > > > archives, and a Xilinx data book, but didn't see anything. > > > > > > Thanks! > > > > > > David ###### Message-ID: <3D0EB699.78E095E0@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Internal oscillator in CPLD? References: <3D0E68F1.92509487@xilinx.com> <3D0E9E2D.E7FC314D@mail.com> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 51 Date: Tue, 18 Jun 2002 04:27:12 GMT NNTP-Posting-Host: 216.244.43.93 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1024374432 216.244.43.93 (Mon, 17 Jun 2002 21:27:12 PDT) NNTP-Posting-Date: Mon, 17 Jun 2002 21:27:12 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!cox.net!newsfeed1.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!3ab61c21!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18533 John, just follow the instructions: resistor to A and to C, capacitor to B. Peter John_H wrote: > ??? > > ------ > |B > +----|---'\/\/\,--+ > | |A | > +-<|-|-----||-----+ > | | | > +|>o-|---'\/\/\,--+ > |C > ------ > > This looks like the junction of the three devices will always be > (Voh+Vol)/2. I feel like I'm missing something big but there's a real > interesting concept here that I've misinterpreted. I'd love to > understand the details. > > Peter Alfke wrote: > > > > If you can afford to dedicate three pins ( 2 outputs and one input) to > > this task, it is easy: > > Input A internally drives output B non-inverted, and also output C > > inverted. > > Connect a resistor to pin A, the same value resistor to pin C, and a > > capacitor to pin B, and interconnect the other ends of these three > > components together. > > Start with two 1 kilohm resistors and 470 pF > > Surprisingly (not really, there is mathematical proof) stable over > > temperature and voltage. > > > > Peter Alfke, Xilinx Applications > > ==================================== > > David Rogoff wrote: > > > > > Hi. > > > > > > I trying to put together a really small, cheap circuit using a CPLD > > > (probably Xilinx 9500). I don't want to have to use a seperate > > > oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz > > > (doesn't need to be accurate) clock wtih only the CPLD. I checked the > > > archives, and a Xilinx data book, but didn't see anything. > > > > > > Thanks! > > > > > > David ###### From: John_H Newsgroups: comp.arch.fpga Subject: Re: Internal oscillator in CPLD? Date: Mon, 17 Jun 2002 22:48:11 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3D0EC99B.8B15E12E@mail.com> X-Mailer: Mozilla 4.73 [en] (Win98; U) X-Accept-Language: en MIME-Version: 1.0 References: <3D0E68F1.92509487@xilinx.com> <3D0E9E2D.E7FC314D@mail.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 60 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!sn-xit-03!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18581 I hate it when I just don't see. Thanks all for pointing out my temporary blindness :-) Ever look for something you *know* is there but you just can't find it? Particular thanks to Jim for a little more detail. I started thinking the resister to A (Ri) had some unusual role beyond my immediate grasp. It's nice to know it's indeed to limit the current into A (since the swing at the junction is beyond the rails). John_H wrote: > > ??? ------ |B +----|-----||-----+ | |A | +-<|-|---'\/\/\,--+ | | | +|>o-|---'\/\/\,--+ |C ------ [ much better ] > This looks like the junction of the three devices will always be > (Voh+Vol)/2. I feel like I'm missing something big but there's a real > interesting concept here that I've misinterpreted. I'd love to > understand the details. > > Peter Alfke wrote: > > > > If you can afford to dedicate three pins ( 2 outputs and one input) to > > this task, it is easy: > > Input A internally drives output B non-inverted, and also output C > > inverted. > > Connect a resistor to pin A, the same value resistor to pin C, and a > > capacitor to pin B, and interconnect the other ends of these three > > components together. > > Start with two 1 kilohm resistors and 470 pF > > Surprisingly (not really, there is mathematical proof) stable over > > temperature and voltage. > > > > Peter Alfke, Xilinx Applications > > ==================================== > > David Rogoff wrote: > > > > > Hi. > > > > > > I trying to put together a really small, cheap circuit using a CPLD > > > (probably Xilinx 9500). I don't want to have to use a seperate > > > oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz > > > (doesn't need to be accurate) clock wtih only the CPLD. I checked the > > > archives, and a Xilinx data book, but didn't see anything. > > > > > > Thanks! > > > > > > David ###### From: "Leon Heller" Newsgroups: comp.arch.fpga Subject: Re: Internal oscillator in CPLD? Date: Tue, 18 Jun 2002 22:09:39 +0000 (UTC) Organization: BT Openworld Lines: 22 Message-ID: References: <3D0E68F1.92509487@xilinx.com> <3D0E9E2D.E7FC314D@mail.com> <3D0EB699.78E095E0@earthlink.net> NNTP-Posting-Host: host213-122-160-196.in-addr.btopenworld.com X-Trace: helle.btinternet.com 1024438179 10590 213.122.160.196 (18 Jun 2002 22:09:39 GMT) X-Complaints-To: news-complaints@lists.btinternet.com NNTP-Posting-Date: Tue, 18 Jun 2002 22:09:39 +0000 (UTC) X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MSMail-Priority: Normal X-Priority: 3 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!colt.net!newspeer.clara.net!news.clara.net!btnet-peer!btnet-peer0!btnet-feed5!btnet!news.btopenworld.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18552 "Peter Alfke" wrote in message news:3D0EB699.78E095E0@earthlink.net... > John, just follow the instructions: resistor to A and to C, capacitor to B. > Peter I just tried it, and it works fine with a couple of 1K5 resistors and a 100n cap. I used an Altera Flex 10K10. Sorry about that, Peter, but my Xilinx Parallel Cable III doesn't seem to be working, otherwise I'd have tried a Xilinx device. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.com